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Compile from UNIX to cygwin32.
[binutils-gdb.git] / sim / v850 / simops.c
1 #include <signal.h>
2 #include "v850_sim.h"
3 #include "simops.h"
4 /* FIXME - should be including a version of syscall.h that does not
5 pollute the name space */
6 #include "../../libgloss/v850/sys/syscall.h"
7 #include "bfd.h"
8 #include <errno.h>
9 #if !defined(__GO32__) && !defined(_WIN32)
10 #include <sys/stat.h>
11 #include <sys/times.h>
12 #include <sys/time.h>
13 #endif
14
15 enum op_types
16 {
17 OP_UNKNOWN,
18 OP_NONE,
19 OP_TRAP,
20 OP_REG,
21 OP_REG_REG,
22 OP_REG_REG_CMP,
23 OP_REG_REG_MOVE,
24 OP_IMM_REG,
25 OP_IMM_REG_CMP,
26 OP_IMM_REG_MOVE,
27 OP_COND_BR,
28 OP_LOAD16,
29 OP_STORE16,
30 OP_LOAD32,
31 OP_STORE32,
32 OP_JUMP,
33 OP_IMM_REG_REG,
34 OP_UIMM_REG_REG,
35 OP_BIT,
36 OP_EX1,
37 OP_EX2,
38 OP_LDSR,
39 OP_STSR,
40 /* start-sanitize-v850e */
41 OP_BIT_CHANGE,
42 OP_REG_REG_REG,
43 OP_REG_REG3,
44 /* end-sanitize-v850e */
45 /* start-sanitize-v850eq */
46 OP_IMM_REG_REG_REG,
47 OP_PUSHPOP1,
48 OP_PUSHPOP2,
49 OP_PUSHPOP3,
50 /* end-sanitize-v850eq */
51 };
52
53 /* start-sanitize-v850e */
54 /* This is an array of the bit positions of registers r20 .. r31 in that order in a prepare/dispose instruction. */
55 static int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
56 /* end-sanitize-v850e */
57 /* start-sanitize-v850eq */
58 /* This is an array of the bit positions of registers r16 .. r31 in that order in a push/pop instruction. */
59 static int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
60 /* This is an array of the bit positions of registers r1 .. r15 in that order in a push/pop instruction. */
61 static int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
62 /* end-sanitize-v850eq */
63
64 #ifdef DEBUG
65 static void trace_input PARAMS ((char *name, enum op_types type, int size));
66 static void trace_output PARAMS ((enum op_types result));
67 static int init_text_p = 0;
68 static asection *text;
69 static bfd_vma text_start;
70 static bfd_vma text_end;
71 extern bfd *prog_bfd;
72
73 #ifndef SIZE_INSTRUCTION
74 #define SIZE_INSTRUCTION 6
75 #endif
76
77 #ifndef SIZE_OPERANDS
78 #define SIZE_OPERANDS 16
79 #endif
80
81 #ifndef SIZE_VALUES
82 #define SIZE_VALUES 11
83 #endif
84
85 #ifndef SIZE_LOCATION
86 #define SIZE_LOCATION 40
87 #endif
88
89
90 static void
91 trace_input (name, type, size)
92 char *name;
93 enum op_types type;
94 int size;
95 {
96 char buf[1024];
97 char *p;
98 uint32 values[3];
99 int num_values, i;
100 char *cond;
101 asection *s;
102 const char *filename;
103 const char *functionname;
104 unsigned int linenumber;
105
106 if ((v850_debug & DEBUG_TRACE) == 0)
107 return;
108
109 buf[0] = '\0';
110 if (!init_text_p)
111 {
112 init_text_p = 1;
113 for (s = prog_bfd->sections; s; s = s->next)
114 if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
115 {
116 text = s;
117 text_start = bfd_get_section_vma (prog_bfd, s);
118 text_end = text_start + bfd_section_size (prog_bfd, s);
119 break;
120 }
121 }
122
123 if (text && PC >= text_start && PC < text_end)
124 {
125 filename = (const char *)0;
126 functionname = (const char *)0;
127 linenumber = 0;
128 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
129 &filename, &functionname, &linenumber))
130 {
131 p = buf;
132 if (linenumber)
133 {
134 sprintf (p, "Line %5d ", linenumber);
135 p += strlen (p);
136 }
137
138 if (functionname)
139 {
140 sprintf (p, "Func %s ", functionname);
141 p += strlen (p);
142 }
143 else if (filename)
144 {
145 char *q = (char *) strrchr (filename, '/');
146 sprintf (p, "File %s ", (q) ? q+1 : filename);
147 p += strlen (p);
148 }
149
150 if (*p == ' ')
151 *p = '\0';
152 }
153 }
154
155 (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
156 (unsigned)PC,
157 SIZE_LOCATION, SIZE_LOCATION, buf,
158 SIZE_INSTRUCTION, name);
159
160 switch (type)
161 {
162 default:
163 case OP_UNKNOWN:
164 case OP_NONE:
165 strcpy (buf, "unknown");
166 break;
167
168 case OP_TRAP:
169 sprintf (buf, "%d", OP[0]);
170 break;
171
172 case OP_REG:
173 sprintf (buf, "r%d", OP[0]);
174 break;
175
176 case OP_REG_REG:
177 case OP_REG_REG_CMP:
178 case OP_REG_REG_MOVE:
179 sprintf (buf, "r%d,r%d", OP[0], OP[1]);
180 break;
181
182 case OP_IMM_REG:
183 case OP_IMM_REG_CMP:
184 case OP_IMM_REG_MOVE:
185 sprintf (buf, "%d,r%d", OP[0], OP[1]);
186 break;
187
188 case OP_COND_BR:
189 sprintf (buf, "%d", SEXT9 (OP[0]));
190 break;
191
192 case OP_LOAD16:
193 sprintf (buf, "%d[r30],r%d", OP[1] * size, OP[0]);
194 break;
195
196 case OP_STORE16:
197 sprintf (buf, "r%d,%d[r30]", OP[0], OP[1] * size);
198 break;
199
200 case OP_LOAD32:
201 sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
202 break;
203
204 case OP_STORE32:
205 sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
206 break;
207
208 case OP_JUMP:
209 sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
210 break;
211
212 case OP_IMM_REG_REG:
213 sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
214 break;
215
216 case OP_UIMM_REG_REG:
217 sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
218 break;
219
220 case OP_BIT:
221 sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
222 break;
223
224 case OP_EX1:
225 switch (OP[0] & 0xf)
226 {
227 default: cond = "?"; break;
228 case 0x0: cond = "v"; break;
229 case 0x1: cond = "c"; break;
230 case 0x2: cond = "z"; break;
231 case 0x3: cond = "nh"; break;
232 case 0x4: cond = "s"; break;
233 case 0x5: cond = "t"; break;
234 case 0x6: cond = "lt"; break;
235 case 0x7: cond = "le"; break;
236 case 0x8: cond = "nv"; break;
237 case 0x9: cond = "nc"; break;
238 case 0xa: cond = "nz"; break;
239 case 0xb: cond = "h"; break;
240 case 0xc: cond = "ns"; break;
241 case 0xd: cond = "sa"; break;
242 case 0xe: cond = "ge"; break;
243 case 0xf: cond = "gt"; break;
244 }
245
246 sprintf (buf, "%s,r%d", cond, OP[1]);
247 break;
248
249 case OP_EX2:
250 strcpy (buf, "EX2");
251 break;
252
253 case OP_LDSR:
254 case OP_STSR:
255 sprintf (buf, "r%d,s%d", OP[0], OP[1]);
256 break;
257
258 case OP_PUSHPOP1:
259 for (i = 0; i < 12; i++)
260 if (OP[3] & (1 << type1_regs[i]))
261 strcat (buf, "r%d ", i + 20);
262 break;
263
264 case OP_PUSHPOP2:
265 for (i = 0; i < 16; i++)
266 if (OP[3] & (1 << type2_regs[i]))
267 strcat (buf, "r%d ", i + 16);
268 if (OP[3] & (1 << 19))
269 strcat (buf, "F/EIPC, F/EIPSW " );
270 break;
271
272 case OP_PUSHPOP3:
273 for (i = 0; i < 15; i++)
274 if (OP[3] & (1 << type3_regs[i]))
275 strcat (buf, "r%d ", i + 1);
276 if (OP[3] & (1 << 3))
277 strcat (buf, "PSW " );
278 if (OP[3] & (1 << 19))
279 strcat (buf, "F/EIPC, F/EIPSW " );
280 break;
281
282 case OP_BIT_CHANGE:
283 sprintf (buf, "r%d, [r%d]", OP[1], OP[0] );
284 break;
285 }
286
287 if ((v850_debug & DEBUG_VALUES) == 0)
288 {
289 (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
290 }
291 else
292 {
293 (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
294 switch (type)
295 {
296 default:
297 case OP_UNKNOWN:
298 case OP_NONE:
299 case OP_TRAP:
300 num_values = 0;
301 break;
302
303 case OP_REG:
304 case OP_REG_REG_MOVE:
305 values[0] = State.regs[OP[0]];
306 num_values = 1;
307 break;
308
309 case OP_BIT_CHANGE:
310 case OP_REG_REG:
311 case OP_REG_REG_CMP:
312 values[0] = State.regs[OP[1]];
313 values[1] = State.regs[OP[0]];
314 num_values = 2;
315 break;
316
317 case OP_IMM_REG:
318 case OP_IMM_REG_CMP:
319 values[0] = SEXT5 (OP[0]);
320 values[1] = OP[1];
321 num_values = 2;
322 break;
323
324 case OP_IMM_REG_MOVE:
325 values[0] = SEXT5 (OP[0]);
326 num_values = 1;
327 break;
328
329 case OP_COND_BR:
330 values[0] = State.pc;
331 values[1] = SEXT9 (OP[0]);
332 values[2] = PSW;
333 num_values = 3;
334 break;
335
336 case OP_LOAD16:
337 values[0] = OP[1] * size;
338 values[1] = State.regs[30];
339 num_values = 2;
340 break;
341
342 case OP_STORE16:
343 values[0] = State.regs[OP[0]];
344 values[1] = OP[1] * size;
345 values[2] = State.regs[30];
346 num_values = 3;
347 break;
348
349 case OP_LOAD32:
350 values[0] = SEXT16 (OP[2]);
351 values[1] = State.regs[OP[0]];
352 num_values = 2;
353 break;
354
355 case OP_STORE32:
356 values[0] = State.regs[OP[1]];
357 values[1] = SEXT16 (OP[2]);
358 values[2] = State.regs[OP[0]];
359 num_values = 3;
360 break;
361
362 case OP_JUMP:
363 values[0] = SEXT22 (OP[0]);
364 values[1] = State.pc;
365 num_values = 2;
366 break;
367
368 case OP_IMM_REG_REG:
369 values[0] = SEXT16 (OP[0]) << size;
370 values[1] = State.regs[OP[1]];
371 num_values = 2;
372 break;
373
374 case OP_UIMM_REG_REG:
375 values[0] = (OP[0] & 0xffff) << size;
376 values[1] = State.regs[OP[1]];
377 num_values = 2;
378 break;
379
380 case OP_BIT:
381 num_values = 0;
382 break;
383
384 case OP_EX1:
385 values[0] = PSW;
386 num_values = 1;
387 break;
388
389 case OP_EX2:
390 num_values = 0;
391 break;
392
393 case OP_LDSR:
394 values[0] = State.regs[OP[0]];
395 num_values = 1;
396 break;
397
398 case OP_STSR:
399 values[0] = State.sregs[OP[1]];
400 num_values = 1;
401 }
402
403 for (i = 0; i < num_values; i++)
404 (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
405
406 while (i++ < 3)
407 (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
408 }
409 }
410
411 static void
412 trace_output (result)
413 enum op_types result;
414 {
415 if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
416 {
417 switch (result)
418 {
419 default:
420 case OP_UNKNOWN:
421 case OP_NONE:
422 case OP_TRAP:
423 case OP_REG:
424 case OP_REG_REG_CMP:
425 case OP_IMM_REG_CMP:
426 case OP_COND_BR:
427 case OP_STORE16:
428 case OP_STORE32:
429 case OP_BIT:
430 case OP_EX2:
431 break;
432
433 case OP_LOAD16:
434 case OP_STSR:
435 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
436 (unsigned long)State.regs[OP[0]]);
437 break;
438
439 case OP_REG_REG:
440 case OP_REG_REG_MOVE:
441 case OP_IMM_REG:
442 case OP_IMM_REG_MOVE:
443 case OP_LOAD32:
444 case OP_EX1:
445 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
446 (unsigned long)State.regs[OP[1]]);
447 break;
448
449 case OP_IMM_REG_REG:
450 case OP_UIMM_REG_REG:
451 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
452 (unsigned long)State.regs[OP[2]]);
453 break;
454
455 case OP_JUMP:
456 if (OP[1] != 0)
457 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
458 (unsigned long)State.regs[OP[1]]);
459 break;
460
461 case OP_LDSR:
462 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
463 (unsigned long)State.sregs[OP[1]]);
464 break;
465 }
466
467 (*v850_callback->printf_filtered) (v850_callback, "\n");
468 }
469 }
470
471 #else
472 #define trace_input(NAME, IN1, IN2)
473 #define trace_output(RESULT)
474
475 //#define trace_input(NAME, IN1, IN2) fprintf (stderr, NAME "\n" );
476
477 #endif
478
479 \f
480 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
481 static unsigned int
482 condition_met (unsigned code)
483 {
484 unsigned int psw = PSW;
485
486 switch (code & 0xf)
487 {
488 case 0x0: return ((psw & PSW_OV) != 0);
489 case 0x1: return ((psw & PSW_CY) != 0);
490 case 0x2: return ((psw & PSW_Z) != 0);
491 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
492 case 0x4: return ((psw & PSW_S) != 0);
493 /*case 0x5: return 1;*/
494 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
495 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
496 case 0x8: return ((psw & PSW_OV) == 0);
497 case 0x9: return ((psw & PSW_CY) == 0);
498 case 0xa: return ((psw & PSW_Z) == 0);
499 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
500 case 0xc: return ((psw & PSW_S) == 0);
501 case 0xd: return ((psw & PSW_SAT) != 0);
502 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
503 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
504 }
505
506 return 1;
507 }
508
509 static unsigned long
510 Add32 (unsigned long a1, unsigned long a2, int * carry)
511 {
512 unsigned long result = (a1 + a2);
513
514 * carry = (result < a1);
515
516 return result;
517 }
518
519 static void
520 Multiply64 (boolean sign, unsigned long op0)
521 {
522 unsigned long op1;
523 unsigned long lo;
524 unsigned long mid1;
525 unsigned long mid2;
526 unsigned long hi;
527 unsigned long RdLo;
528 unsigned long RdHi;
529 int carry;
530
531 op1 = State.regs[ OP[1] ];
532
533 if (sign)
534 {
535 /* Compute sign of result and adjust operands if necessary. */
536
537 sign = (op0 ^ op1) & 0x80000000;
538
539 if (((signed long) op0) < 0)
540 op0 = - op0;
541
542 if (((signed long) op1) < 0)
543 op1 = - op1;
544 }
545
546 /* We can split the 32x32 into four 16x16 operations. This ensures
547 that we do not lose precision on 32bit only hosts: */
548 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
549 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
550 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
551 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
552
553 /* We now need to add all of these results together, taking care
554 to propogate the carries from the additions: */
555 RdLo = Add32 (lo, (mid1 << 16), & carry);
556 RdHi = carry;
557 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
558 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
559
560 if (sign)
561 {
562 /* Negate result if necessary. */
563
564 RdLo = ~ RdLo;
565 RdHi = ~ RdHi;
566 if (RdLo == 0xFFFFFFFF)
567 {
568 RdLo = 0;
569 RdHi += 1;
570 }
571 else
572 RdLo += 1;
573 }
574
575 State.regs[ OP[1] ] = RdLo;
576 State.regs[ OP[2] >> 11 ] = RdHi;
577
578 return;
579 }
580
581 \f
582 /* sld.b */
583 int
584 OP_300 ()
585 {
586 unsigned long result;
587
588 result = load_mem (State.regs[30] + (OP[3] & 0x7f), 1);
589
590 /* start-sanitize-v850eq */
591 #ifdef ARCH_v850eq
592 trace_input ("sld.bu", OP_LOAD16, 1);
593
594 State.regs[ OP[1] ] = result;
595 #else
596 /* end-sanitize-v850eq */
597 trace_input ("sld.b", OP_LOAD16, 1);
598
599 State.regs[ OP[1] ] = SEXT8 (result);
600 /* start-sanitize-v850eq */
601 #endif
602 /* end-sanitize-v850eq */
603
604 trace_output (OP_LOAD16);
605
606 return 2;
607 }
608
609 /* sld.h */
610 int
611 OP_400 ()
612 {
613 unsigned long result;
614
615 result = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2);
616
617 /* start-sanitize-v850eq */
618 #ifdef ARCH_v850eq
619 trace_input ("sld.hu", OP_LOAD16, 2);
620
621 State.regs[ OP[1] ] = result;
622 #else
623 /* end-sanitize-v850eq */
624 trace_input ("sld.h", OP_LOAD16, 2);
625
626 State.regs[ OP[1] ] = SEXT16 (result);
627 /* start-sanitize-v850eq */
628 #endif
629 /* end-sanitize-v850eq */
630
631 trace_output (OP_LOAD16);
632
633 return 2;
634 }
635
636 /* sld.w */
637 int
638 OP_500 ()
639 {
640 trace_input ("sld.w", OP_LOAD16, 4);
641
642 State.regs[ OP[1] ] = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 4);
643
644 trace_output (OP_LOAD16);
645
646 return 2;
647 }
648
649 /* sst.b */
650 int
651 OP_380 ()
652 {
653 trace_input ("sst.b", OP_STORE16, 1);
654
655 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
656
657 trace_output (OP_STORE16);
658
659 return 2;
660 }
661
662 /* sst.h */
663 int
664 OP_480 ()
665 {
666 trace_input ("sst.h", OP_STORE16, 2);
667
668 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
669
670 trace_output (OP_STORE16);
671
672 return 2;
673 }
674
675 /* sst.w */
676 int
677 OP_501 ()
678 {
679 trace_input ("sst.w", OP_STORE16, 4);
680
681 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
682
683 trace_output (OP_STORE16);
684
685 return 2;
686 }
687
688 /* ld.b */
689 int
690 OP_700 ()
691 {
692 int adr;
693
694 trace_input ("ld.b", OP_LOAD32, 1);
695
696 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
697
698 State.regs[ OP[1] ] = SEXT8 (load_mem (adr, 1));
699
700 trace_output (OP_LOAD32);
701
702 return 4;
703 }
704
705 /* ld.h */
706 int
707 OP_720 ()
708 {
709 int adr;
710
711 trace_input ("ld.h", OP_LOAD32, 2);
712
713 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
714 adr &= ~0x1;
715
716 State.regs[ OP[1] ] = SEXT16 (load_mem (adr, 2));
717
718 trace_output (OP_LOAD32);
719
720 return 4;
721 }
722
723 /* ld.w */
724 int
725 OP_10720 ()
726 {
727 int adr;
728
729 trace_input ("ld.w", OP_LOAD32, 4);
730
731 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
732 adr &= ~0x3;
733
734 State.regs[ OP[1] ] = load_mem (adr, 4);
735
736 trace_output (OP_LOAD32);
737
738 return 4;
739 }
740
741 /* st.b */
742 int
743 OP_740 ()
744 {
745 trace_input ("st.b", OP_STORE32, 1);
746
747 store_mem (State.regs[ OP[0] ] + SEXT16 (OP[2]), 1, State.regs[ OP[1] ]);
748
749 trace_output (OP_STORE32);
750
751 return 4;
752 }
753
754 /* st.h */
755 int
756 OP_760 ()
757 {
758 int adr;
759
760 trace_input ("st.h", OP_STORE32, 2);
761
762 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
763 adr &= ~1;
764
765 store_mem (adr, 2, State.regs[ OP[1] ]);
766
767 trace_output (OP_STORE32);
768
769 return 4;
770 }
771
772 /* st.w */
773 int
774 OP_10760 ()
775 {
776 int adr;
777
778 trace_input ("st.w", OP_STORE32, 4);
779
780 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
781 adr &= ~3;
782
783 store_mem (adr, 4, State.regs[ OP[1] ]);
784
785 trace_output (OP_STORE32);
786
787 return 4;
788 }
789
790 static int
791 branch (int code)
792 {
793 unsigned int psw;
794 int op0;
795
796 trace_input ("Bcond", OP_COND_BR, 0);
797 trace_output (OP_COND_BR);
798
799 if (condition_met (code))
800 return SEXT9 (((OP[3] & 0x70) >> 3) | ((OP[3] & 0xf800) >> 7));
801 else
802 return 2;
803 }
804
805 /* bv disp9 */
806 int
807 OP_580 ()
808 {
809 return branch (0);
810 }
811
812 /* bl disp9 */
813 int
814 OP_581 ()
815 {
816 return branch (1);
817 }
818
819 /* be disp9 */
820 int
821 OP_582 ()
822 {
823 return branch (2);
824 }
825
826 /* bnh disp 9*/
827 int
828 OP_583 ()
829 {
830 return branch (3);
831 }
832
833 /* bn disp9 */
834 int
835 OP_584 ()
836 {
837 return branch (4);
838 }
839
840 /* br disp9 */
841 int
842 OP_585 ()
843 {
844 return branch (5);
845 }
846
847 /* blt disp9 */
848 int
849 OP_586 ()
850 {
851 return branch (6);
852 }
853
854 /* ble disp9 */
855 int
856 OP_587 ()
857 {
858 return branch (7);
859 }
860
861 /* bnv disp9 */
862 int
863 OP_588 ()
864 {
865 return branch (8);
866 }
867
868 /* bnl disp9 */
869 int
870 OP_589 ()
871 {
872 return branch (9);
873 }
874
875 /* bne disp9 */
876 int
877 OP_58A ()
878 {
879 return branch (10);
880 }
881
882 /* bh disp9 */
883 int
884 OP_58B ()
885 {
886 return branch (11);
887 }
888
889 /* bp disp9 */
890 int
891 OP_58C ()
892 {
893 return branch (12);
894 }
895
896 /* bsa disp9 */
897 int
898 OP_58D ()
899 {
900 return branch (13);
901 }
902
903 /* bge disp9 */
904 int
905 OP_58E ()
906 {
907 return branch (14);
908 }
909
910 /* bgt disp9 */
911 int
912 OP_58F ()
913 {
914 return branch (15);
915 }
916
917 /* jmp [reg1] */
918 /* sld.bu disp4[ep], reg2 */
919 int
920 OP_60 ()
921 {
922 if (OP[1] == 0)
923 {
924 trace_input ("jmp", OP_REG, 0);
925
926 PC = State.regs[ OP[0] ];
927
928 trace_output (OP_REG);
929
930 return 0; /* Add nothing to the PC, we have already done it. */
931 }
932 /* start-sanitize-v850e */
933 else
934 {
935 unsigned long result;
936
937 result = load_mem (State.regs[30] + (OP[3] & 0xf), 1);
938
939 /* start-sanitize-v850eq */
940 #ifdef ARCH_v850eq
941 trace_input ("sld.b", OP_LOAD16, 1);
942
943 State.regs[ OP[1] ] = SEXT8 (result);
944 #else
945 /* end-sanitize-v850eq */
946 trace_input ("sld.bu", OP_LOAD16, 1);
947
948 State.regs[ OP[1] ] = result;
949 /* start-sanitize-v850eq */
950 #endif
951 /* end-sanitize-v850eq */
952
953 trace_output (OP_LOAD16);
954
955 return 2;
956 }
957 /* end-sanitize-v850e */
958 }
959
960 /* jarl/jr disp22, reg */
961 int
962 OP_780 ()
963 {
964 trace_input ("jarl/jr", OP_JUMP, 0);
965
966 if (OP[ 1 ] != 0)
967 State.regs[ OP[1] ] = PC + 4;
968
969 trace_output (OP_JUMP);
970
971 return SEXT22 (((OP[3] & 0x3f) << 16) | OP[2]);
972 }
973
974 /* add reg, reg */
975 int
976 OP_1C0 ()
977 {
978 unsigned int op0, op1, result, z, s, cy, ov;
979
980 trace_input ("add", OP_REG_REG, 0);
981
982 /* Compute the result. */
983
984 op0 = State.regs[ OP[0] ];
985 op1 = State.regs[ OP[1] ];
986
987 result = op0 + op1;
988
989 /* Compute the condition codes. */
990 z = (result == 0);
991 s = (result & 0x80000000);
992 cy = (result < op0 || result < op1);
993 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
994 && (op0 & 0x80000000) != (result & 0x80000000));
995
996 /* Store the result and condition codes. */
997 State.regs[OP[1]] = result;
998 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
999 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1000 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1001 trace_output (OP_REG_REG);
1002
1003 return 2;
1004 }
1005
1006 /* add sign_extend(imm5), reg */
1007 int
1008 OP_240 ()
1009 {
1010 unsigned int op0, op1, result, z, s, cy, ov;
1011 int temp;
1012
1013 trace_input ("add", OP_IMM_REG, 0);
1014
1015 /* Compute the result. */
1016 temp = SEXT5 (OP[0]);
1017 op0 = temp;
1018 op1 = State.regs[OP[1]];
1019 result = op0 + op1;
1020
1021 /* Compute the condition codes. */
1022 z = (result == 0);
1023 s = (result & 0x80000000);
1024 cy = (result < op0 || result < op1);
1025 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1026 && (op0 & 0x80000000) != (result & 0x80000000));
1027
1028 /* Store the result and condition codes. */
1029 State.regs[OP[1]] = result;
1030 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1031 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1032 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1033 trace_output (OP_IMM_REG);
1034
1035 return 2;
1036 }
1037
1038 /* addi sign_extend(imm16), reg, reg */
1039 int
1040 OP_600 ()
1041 {
1042 unsigned int op0, op1, result, z, s, cy, ov;
1043
1044 trace_input ("addi", OP_IMM_REG_REG, 0);
1045
1046 /* Compute the result. */
1047
1048 op0 = SEXT16 (OP[2]);
1049 op1 = State.regs[ OP[0] ];
1050 result = op0 + op1;
1051
1052 /* Compute the condition codes. */
1053 z = (result == 0);
1054 s = (result & 0x80000000);
1055 cy = (result < op0 || result < op1);
1056 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1057 && (op0 & 0x80000000) != (result & 0x80000000));
1058
1059 /* Store the result and condition codes. */
1060 State.regs[OP[1]] = result;
1061 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1062 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1063 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1064 trace_output (OP_IMM_REG_REG);
1065
1066 return 4;
1067 }
1068
1069 /* sub reg1, reg2 */
1070 int
1071 OP_1A0 ()
1072 {
1073 unsigned int op0, op1, result, z, s, cy, ov;
1074
1075 trace_input ("sub", OP_REG_REG, 0);
1076 /* Compute the result. */
1077 op0 = State.regs[ OP[0] ];
1078 op1 = State.regs[ OP[1] ];
1079 result = op1 - op0;
1080
1081 /* Compute the condition codes. */
1082 z = (result == 0);
1083 s = (result & 0x80000000);
1084 cy = (op1 < op0);
1085 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1086 && (op1 & 0x80000000) != (result & 0x80000000));
1087
1088 /* Store the result and condition codes. */
1089 State.regs[OP[1]] = result;
1090 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1091 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1092 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1093 trace_output (OP_REG_REG);
1094
1095 return 2;
1096 }
1097
1098 /* subr reg1, reg2 */
1099 int
1100 OP_180 ()
1101 {
1102 unsigned int op0, op1, result, z, s, cy, ov;
1103
1104 trace_input ("subr", OP_REG_REG, 0);
1105 /* Compute the result. */
1106 op0 = State.regs[ OP[0] ];
1107 op1 = State.regs[ OP[1] ];
1108 result = op0 - op1;
1109
1110 /* Compute the condition codes. */
1111 z = (result == 0);
1112 s = (result & 0x80000000);
1113 cy = (op0 < op1);
1114 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1115 && (op0 & 0x80000000) != (result & 0x80000000));
1116
1117 /* Store the result and condition codes. */
1118 State.regs[OP[1]] = result;
1119 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1120 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1121 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1122 trace_output (OP_REG_REG);
1123
1124 return 2;
1125 }
1126
1127 /* sxh reg1 */
1128 /* mulh reg1, reg2 */
1129 int
1130 OP_E0 ()
1131 {
1132 /* start-sanitize-v850e */
1133 if (OP[1] == 0)
1134 {
1135 trace_input ("sxh", OP_REG, 0);
1136
1137 State.regs[ OP[0] ] = SEXT16 (State.regs[ OP[0] ]);
1138
1139 trace_output (OP_REG);
1140 }
1141 else
1142 /* end-sanitize-v850e */
1143 {
1144 trace_input ("mulh", OP_REG_REG, 0);
1145
1146 State.regs[ OP[1] ] = (SEXT16 (State.regs[ OP[1] ]) * SEXT16 (State.regs[ OP[0] ]));
1147
1148 trace_output (OP_REG_REG);
1149 }
1150
1151 return 2;
1152 }
1153
1154 /* mulh sign_extend(imm5), reg2 */
1155 int
1156 OP_2E0 ()
1157 {
1158 trace_input ("mulh", OP_IMM_REG, 0);
1159
1160 State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
1161
1162 trace_output (OP_IMM_REG);
1163
1164 return 2;
1165 }
1166
1167 /* mulhi imm16, reg1, reg2 */
1168 int
1169 OP_6E0 ()
1170 {
1171 if (OP[1] == 0)
1172 {
1173 }
1174 else
1175 {
1176 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1177
1178 State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[0] ]) * SEXT16 (OP[2]);
1179
1180 trace_output (OP_IMM_REG_REG);
1181 }
1182
1183 return 4;
1184 }
1185
1186 /* divh reg1, reg2 */
1187 /* switch reg1 */
1188 int
1189 OP_40 ()
1190 {
1191 /* start-sanitize-v850e */
1192 if (OP[1] == 0)
1193 {
1194 unsigned long adr;
1195
1196 trace_input ("switch", OP_REG, 0);
1197
1198 adr = State.pc + 2 + (State.regs[ OP[0] ] << 1);
1199 State.pc = State.pc + 2 + (SEXT16 (load_mem (adr, 2)) << 1);
1200
1201 trace_output (OP_REG);
1202 }
1203 else
1204 /* end-sanitize-v850e */
1205 {
1206 unsigned int op0, op1, result, ov, s, z;
1207 int temp;
1208
1209 trace_input ("divh", OP_REG_REG, 0);
1210
1211 /* Compute the result. */
1212 temp = SEXT16 (State.regs[ OP[0] ]);
1213 op0 = temp;
1214 op1 = State.regs[OP[1]];
1215
1216 if (op0 == 0xffffffff && op1 == 0x80000000)
1217 {
1218 result = 0x80000000;
1219 ov = 1;
1220 }
1221 else if (op0 != 0)
1222 {
1223 result = op1 / op0;
1224 ov = 0;
1225 }
1226 else
1227 {
1228 result = 0x0;
1229 ov = 1;
1230 }
1231
1232 /* Compute the condition codes. */
1233 z = (result == 0);
1234 s = (result & 0x80000000);
1235
1236 /* Store the result and condition codes. */
1237 State.regs[OP[1]] = result;
1238 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1239 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1240 | (ov ? PSW_OV : 0));
1241 trace_output (OP_REG_REG);
1242 }
1243
1244 return 2;
1245 }
1246
1247 /* cmp reg, reg */
1248 int
1249 OP_1E0 ()
1250 {
1251 unsigned int op0, op1, result, z, s, cy, ov;
1252
1253 trace_input ("cmp", OP_REG_REG_CMP, 0);
1254 /* Compute the result. */
1255 op0 = State.regs[ OP[0] ];
1256 op1 = State.regs[ OP[1] ];
1257 result = op1 - op0;
1258
1259 /* Compute the condition codes. */
1260 z = (result == 0);
1261 s = (result & 0x80000000);
1262 cy = (op1 < op0);
1263 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1264 && (op1 & 0x80000000) != (result & 0x80000000));
1265
1266 /* Set condition codes. */
1267 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1268 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1269 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1270 trace_output (OP_REG_REG_CMP);
1271
1272 return 2;
1273 }
1274
1275 /* cmp sign_extend(imm5), reg */
1276 int
1277 OP_260 ()
1278 {
1279 unsigned int op0, op1, result, z, s, cy, ov;
1280 int temp;
1281
1282 /* Compute the result. */
1283 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1284 temp = SEXT5 (OP[0]);
1285 op0 = temp;
1286 op1 = State.regs[OP[1]];
1287 result = op1 - op0;
1288
1289 /* Compute the condition codes. */
1290 z = (result == 0);
1291 s = (result & 0x80000000);
1292 cy = (op1 < op0);
1293 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1294 && (op1 & 0x80000000) != (result & 0x80000000));
1295
1296 /* Set condition codes. */
1297 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1298 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1299 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1300 trace_output (OP_IMM_REG_CMP);
1301
1302 return 2;
1303 }
1304
1305 /* setf cccc,reg2 */
1306 int
1307 OP_7E0 ()
1308 {
1309 trace_input ("setf", OP_EX1, 0);
1310
1311 State.regs[ OP[1] ] = condition_met (OP[0]);
1312
1313 trace_output (OP_EX1);
1314
1315 return 4;
1316 }
1317
1318 /* zxh reg1 */
1319 /* satadd reg,reg */
1320 int
1321 OP_C0 ()
1322 {
1323 /* start-sanitize-v850e */
1324 if (OP[1] == 0)
1325 {
1326 trace_input ("zxh", OP_REG, 0);
1327
1328 State.regs[ OP[0] ] &= 0xffff;
1329
1330 trace_output (OP_REG);
1331 }
1332 else
1333 /* end-sanitize-v850e */
1334 {
1335 unsigned int op0, op1, result, z, s, cy, ov, sat;
1336
1337 trace_input ("satadd", OP_REG_REG, 0);
1338 /* Compute the result. */
1339 op0 = State.regs[ OP[0] ];
1340 op1 = State.regs[ OP[1] ];
1341 result = op0 + op1;
1342
1343 /* Compute the condition codes. */
1344 z = (result == 0);
1345 s = (result & 0x80000000);
1346 cy = (result < op0 || result < op1);
1347 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1348 && (op0 & 0x80000000) != (result & 0x80000000));
1349 sat = ov;
1350
1351 /* Store the result and condition codes. */
1352 State.regs[OP[1]] = result;
1353 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1354 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1355 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1356 | (sat ? PSW_SAT : 0));
1357
1358 /* Handle saturated results. */
1359 if (sat && s)
1360 State.regs[OP[1]] = 0x80000000;
1361 else if (sat)
1362 State.regs[OP[1]] = 0x7fffffff;
1363 trace_output (OP_REG_REG);
1364 }
1365
1366 return 2;
1367 }
1368
1369 /* satadd sign_extend(imm5), reg */
1370 int
1371 OP_220 ()
1372 {
1373 unsigned int op0, op1, result, z, s, cy, ov, sat;
1374
1375 int temp;
1376
1377 trace_input ("satadd", OP_IMM_REG, 0);
1378
1379 /* Compute the result. */
1380 temp = SEXT5 (OP[0]);
1381 op0 = temp;
1382 op1 = State.regs[OP[1]];
1383 result = op0 + op1;
1384
1385 /* Compute the condition codes. */
1386 z = (result == 0);
1387 s = (result & 0x80000000);
1388 cy = (result < op0 || result < op1);
1389 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1390 && (op0 & 0x80000000) != (result & 0x80000000));
1391 sat = ov;
1392
1393 /* Store the result and condition codes. */
1394 State.regs[OP[1]] = result;
1395 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1396 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1397 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1398 | (sat ? PSW_SAT : 0));
1399
1400 /* Handle saturated results. */
1401 if (sat && s)
1402 State.regs[OP[1]] = 0x80000000;
1403 else if (sat)
1404 State.regs[OP[1]] = 0x7fffffff;
1405 trace_output (OP_IMM_REG);
1406
1407 return 2;
1408 }
1409
1410 /* satsub reg1, reg2 */
1411 /* sxb reg1 */
1412 int
1413 OP_A0 ()
1414 {
1415 /* start-sanitize-v850e */
1416 if (OP[1] == 0)
1417 {
1418 trace_input ("sxb", OP_REG, 0);
1419
1420 State.regs[ OP[0] ] = SEXT8 (State.regs[ OP[0] ]);
1421
1422 trace_output (OP_REG);
1423 }
1424 else
1425 /* end-sanitize-v850e */
1426 {
1427 unsigned int op0, op1, result, z, s, cy, ov, sat;
1428
1429 trace_input ("satsub", OP_REG_REG, 0);
1430
1431 /* Compute the result. */
1432 op0 = State.regs[ OP[0] ];
1433 op1 = State.regs[ OP[1] ];
1434 result = op1 - op0;
1435
1436 /* Compute the condition codes. */
1437 z = (result == 0);
1438 s = (result & 0x80000000);
1439 cy = (op1 < op0);
1440 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1441 && (op1 & 0x80000000) != (result & 0x80000000));
1442 sat = ov;
1443
1444 /* Store the result and condition codes. */
1445 State.regs[OP[1]] = result;
1446 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1447 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1448 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1449 | (sat ? PSW_SAT : 0));
1450
1451 /* Handle saturated results. */
1452 if (sat && s)
1453 State.regs[OP[1]] = 0x80000000;
1454 else if (sat)
1455 State.regs[OP[1]] = 0x7fffffff;
1456 trace_output (OP_REG_REG);
1457 }
1458
1459 return 2;
1460 }
1461
1462 /* satsubi sign_extend(imm16), reg */
1463 int
1464 OP_660 ()
1465 {
1466 unsigned int op0, op1, result, z, s, cy, ov, sat;
1467 int temp;
1468
1469 trace_input ("satsubi", OP_IMM_REG, 0);
1470
1471 /* Compute the result. */
1472 temp = SEXT16 (OP[2]);
1473 op0 = temp;
1474 op1 = State.regs[ OP[0] ];
1475 result = op1 - op0;
1476
1477 /* Compute the condition codes. */
1478 z = (result == 0);
1479 s = (result & 0x80000000);
1480 cy = (op1 < op0);
1481 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1482 && (op1 & 0x80000000) != (result & 0x80000000));
1483 sat = ov;
1484
1485 /* Store the result and condition codes. */
1486 State.regs[OP[1]] = result;
1487 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1488 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1489 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1490 | (sat ? PSW_SAT : 0));
1491
1492 /* Handle saturated results. */
1493 if (sat && s)
1494 State.regs[OP[1]] = 0x80000000;
1495 else if (sat)
1496 State.regs[OP[1]] = 0x7fffffff;
1497 trace_output (OP_IMM_REG);
1498
1499 return 4;
1500 }
1501
1502 /* satsubr reg,reg */
1503 /* zxb reg1 */
1504 int
1505 OP_80 ()
1506 {
1507 /* start-sanitize-v850e */
1508 if (OP[1] == 0)
1509 {
1510 trace_input ("zxb", OP_REG, 0);
1511
1512 State.regs[ OP[0] ] &= 0xff;
1513
1514 trace_output (OP_REG);
1515 }
1516 else
1517 /* end-sanitize-v850e */
1518 {
1519 unsigned int op0, op1, result, z, s, cy, ov, sat;
1520
1521 trace_input ("satsubr", OP_REG_REG, 0);
1522
1523 /* Compute the result. */
1524 op0 = State.regs[ OP[0] ];
1525 op1 = State.regs[ OP[1] ];
1526 result = op0 - op1;
1527
1528 /* Compute the condition codes. */
1529 z = (result == 0);
1530 s = (result & 0x80000000);
1531 cy = (result < op0);
1532 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1533 && (op1 & 0x80000000) != (result & 0x80000000));
1534 sat = ov;
1535
1536 /* Store the result and condition codes. */
1537 State.regs[OP[1]] = result;
1538 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1539 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1540 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1541 | (sat ? PSW_SAT : 0));
1542
1543 /* Handle saturated results. */
1544 if (sat && s)
1545 State.regs[OP[1]] = 0x80000000;
1546 else if (sat)
1547 State.regs[OP[1]] = 0x7fffffff;
1548 trace_output (OP_REG_REG);
1549 }
1550
1551 return 2;
1552 }
1553
1554 /* tst reg,reg */
1555 int
1556 OP_160 ()
1557 {
1558 unsigned int op0, op1, result, z, s;
1559
1560 trace_input ("tst", OP_REG_REG_CMP, 0);
1561
1562 /* Compute the result. */
1563 op0 = State.regs[ OP[0] ];
1564 op1 = State.regs[ OP[1] ];
1565 result = op0 & op1;
1566
1567 /* Compute the condition codes. */
1568 z = (result == 0);
1569 s = (result & 0x80000000);
1570
1571 /* Store the condition codes. */
1572 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1573 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1574 trace_output (OP_REG_REG_CMP);
1575
1576 return 2;
1577 }
1578
1579 /* mov reg, reg */
1580 int
1581 OP_0 ()
1582 {
1583 trace_input ("mov", OP_REG_REG_MOVE, 0);
1584
1585 State.regs[ OP[1] ] = State.regs[ OP[0] ];
1586
1587 trace_output (OP_REG_REG_MOVE);
1588
1589 return 2;
1590 }
1591
1592 /* mov sign_extend(imm5), reg */
1593 /* callt imm6 */
1594 int
1595 OP_200 ()
1596 {
1597 /* start-sanitize-v850e */
1598 if (OP[1] == 0)
1599 {
1600 unsigned long adr;
1601
1602 trace_input ("callt", OP_LOAD16, 1);
1603
1604 CTPC = PC + 2;
1605 CTPSW = PSW;
1606
1607 adr = CTBP + ((OP[3] & 0x3f) << 1);
1608
1609 PC = CTBP + load_mem (adr, 1);
1610
1611 trace_output (OP_LOAD16);
1612
1613 return 0;
1614 }
1615 else
1616 /* end-sanitize-v850e */
1617 {
1618 int value = SEXT5 (OP[0]);
1619
1620 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1621
1622 State.regs[ OP[1] ] = value;
1623
1624 trace_output (OP_IMM_REG_MOVE);
1625
1626 return 2;
1627 }
1628 }
1629
1630 /* mov imm32, reg1 */
1631 /* movea sign_extend(imm16), reg, reg */
1632 int
1633 OP_620 ()
1634 {
1635 /* start-sanitize-v850e */
1636 if (OP[1] == 0)
1637 {
1638 trace_input ("mov", OP_IMM32_REG, 4);
1639
1640 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
1641
1642 trace_output (OP_IMM32_REG);
1643
1644 return 6;
1645 }
1646 else
1647 /* end-sanitize-v850e */
1648 {
1649 trace_input ("movea", OP_IMM_REG_REG, 0);
1650
1651 State.regs[ OP[1] ] = State.regs[ OP[0] ] + SEXT16 (OP[2]);
1652
1653 trace_output (OP_IMM_REG_REG);
1654
1655 return 4;
1656 }
1657 }
1658
1659 /* dispose imm5, list12 [, reg1] */
1660 /* movhi imm16, reg, reg */
1661 int
1662 OP_640 ()
1663 {
1664 /* start-sanitize-v850e */
1665
1666 if (OP[1] == 0)
1667 {
1668 int i;
1669
1670 trace_input ("dispose", OP_PUSHPOP1, 0);
1671
1672 SP += (OP[3] & 0x3e) << 1;
1673
1674 /* Load the registers with lower number registers being retrieved from higher addresses. */
1675 for (i = 12; i--;)
1676 if ((OP[3] & (1 << type1_regs[ i ])))
1677 {
1678 State.regs[ 20 + i ] = load_mem (SP, 4);
1679 SP += 4;
1680 }
1681
1682 if ((OP[3] & 0x1f0000) != 0)
1683 {
1684 PC = State.regs[ (OP[3] >> 16) & 0x1f];
1685 return 0;
1686 }
1687
1688 trace_output (OP_PUSHPOP1);
1689 }
1690 else
1691 /* end-sanitize-v850e */
1692 {
1693 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1694
1695 State.regs[ OP[1] ] = State.regs[ OP[0] ] + OP[2] << 16;
1696
1697 trace_output (OP_UIMM_REG_REG);
1698 }
1699
1700 return 4;
1701 }
1702
1703 /* sar zero_extend(imm5),reg1 */
1704 int
1705 OP_2A0 ()
1706 {
1707 unsigned int op0, op1, result, z, s, cy;
1708
1709 trace_input ("sar", OP_IMM_REG, 0);
1710 op0 = OP[0];
1711 op1 = State.regs[ OP[1] ];
1712 result = (signed)op1 >> op0;
1713
1714 /* Compute the condition codes. */
1715 z = (result == 0);
1716 s = (result & 0x80000000);
1717 cy = (op1 & (1 << (op0 - 1)));
1718
1719 /* Store the result and condition codes. */
1720 State.regs[ OP[1] ] = result;
1721 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1722 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1723 | (cy ? PSW_CY : 0));
1724 trace_output (OP_IMM_REG);
1725
1726 return 2;
1727 }
1728
1729 /* sar reg1, reg2 */
1730 int
1731 OP_A007E0 ()
1732 {
1733 unsigned int op0, op1, result, z, s, cy;
1734
1735 trace_input ("sar", OP_REG_REG, 0);
1736
1737 op0 = State.regs[ OP[0] ] & 0x1f;
1738 op1 = State.regs[ OP[1] ];
1739 result = (signed)op1 >> op0;
1740
1741 /* Compute the condition codes. */
1742 z = (result == 0);
1743 s = (result & 0x80000000);
1744 cy = (op1 & (1 << (op0 - 1)));
1745
1746 /* Store the result and condition codes. */
1747 State.regs[OP[1]] = result;
1748 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1749 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1750 | (cy ? PSW_CY : 0));
1751 trace_output (OP_REG_REG);
1752
1753 return 4;
1754 }
1755
1756 /* shl zero_extend(imm5),reg1 */
1757 int
1758 OP_2C0 ()
1759 {
1760 unsigned int op0, op1, result, z, s, cy;
1761
1762 trace_input ("shl", OP_IMM_REG, 0);
1763 op0 = OP[0];
1764 op1 = State.regs[ OP[1] ];
1765 result = op1 << op0;
1766
1767 /* Compute the condition codes. */
1768 z = (result == 0);
1769 s = (result & 0x80000000);
1770 cy = (op1 & (1 << (32 - op0)));
1771
1772 /* Store the result and condition codes. */
1773 State.regs[OP[1]] = result;
1774 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1775 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1776 | (cy ? PSW_CY : 0));
1777 trace_output (OP_IMM_REG);
1778
1779 return 2;
1780 }
1781
1782 /* shl reg1, reg2 */
1783 int
1784 OP_C007E0 ()
1785 {
1786 unsigned int op0, op1, result, z, s, cy;
1787
1788 trace_input ("shl", OP_REG_REG, 0);
1789 op0 = State.regs[ OP[0] ] & 0x1f;
1790 op1 = State.regs[ OP[1] ];
1791 result = op1 << op0;
1792
1793 /* Compute the condition codes. */
1794 z = (result == 0);
1795 s = (result & 0x80000000);
1796 cy = (op1 & (1 << (32 - op0)));
1797
1798 /* Store the result and condition codes. */
1799 State.regs[OP[1]] = result;
1800 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1801 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1802 | (cy ? PSW_CY : 0));
1803 trace_output (OP_REG_REG);
1804
1805 return 4;
1806 }
1807
1808 /* shr zero_extend(imm5),reg1 */
1809 int
1810 OP_280 ()
1811 {
1812 unsigned int op0, op1, result, z, s, cy;
1813
1814 trace_input ("shr", OP_IMM_REG, 0);
1815 op0 = OP[0];
1816 op1 = State.regs[ OP[1] ];
1817 result = op1 >> op0;
1818
1819 /* Compute the condition codes. */
1820 z = (result == 0);
1821 s = (result & 0x80000000);
1822 cy = (op1 & (1 << (op0 - 1)));
1823
1824 /* Store the result and condition codes. */
1825 State.regs[OP[1]] = result;
1826 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1827 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1828 | (cy ? PSW_CY : 0));
1829 trace_output (OP_IMM_REG);
1830
1831 return 2;
1832 }
1833
1834 /* shr reg1, reg2 */
1835 int
1836 OP_8007E0 ()
1837 {
1838 unsigned int op0, op1, result, z, s, cy;
1839
1840 trace_input ("shr", OP_REG_REG, 0);
1841 op0 = State.regs[ OP[0] ] & 0x1f;
1842 op1 = State.regs[ OP[1] ];
1843 result = op1 >> op0;
1844
1845 /* Compute the condition codes. */
1846 z = (result == 0);
1847 s = (result & 0x80000000);
1848 cy = (op1 & (1 << (op0 - 1)));
1849
1850 /* Store the result and condition codes. */
1851 State.regs[OP[1]] = result;
1852 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1853 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1854 | (cy ? PSW_CY : 0));
1855 trace_output (OP_REG_REG);
1856
1857 return 4;
1858 }
1859
1860 /* or reg, reg */
1861 int
1862 OP_100 ()
1863 {
1864 unsigned int op0, op1, result, z, s;
1865
1866 trace_input ("or", OP_REG_REG, 0);
1867
1868 /* Compute the result. */
1869 op0 = State.regs[ OP[0] ];
1870 op1 = State.regs[ OP[1] ];
1871 result = op0 | op1;
1872
1873 /* Compute the condition codes. */
1874 z = (result == 0);
1875 s = (result & 0x80000000);
1876
1877 /* Store the result and condition codes. */
1878 State.regs[OP[1]] = result;
1879 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1880 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1881 trace_output (OP_REG_REG);
1882
1883 return 2;
1884 }
1885
1886 /* ori zero_extend(imm16), reg, reg */
1887 int
1888 OP_680 ()
1889 {
1890 unsigned int op0, op1, result, z, s;
1891
1892 trace_input ("ori", OP_UIMM_REG_REG, 0);
1893 op0 = OP[2];
1894 op1 = State.regs[ OP[0] ];
1895 result = op0 | op1;
1896
1897 /* Compute the condition codes. */
1898 z = (result == 0);
1899 s = (result & 0x80000000);
1900
1901 /* Store the result and condition codes. */
1902 State.regs[OP[1]] = result;
1903 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1904 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1905 trace_output (OP_UIMM_REG_REG);
1906
1907 return 4;
1908 }
1909
1910 /* and reg, reg */
1911 int
1912 OP_140 ()
1913 {
1914 unsigned int op0, op1, result, z, s;
1915
1916 trace_input ("and", OP_REG_REG, 0);
1917
1918 /* Compute the result. */
1919 op0 = State.regs[ OP[0] ];
1920 op1 = State.regs[ OP[1] ];
1921 result = op0 & op1;
1922
1923 /* Compute the condition codes. */
1924 z = (result == 0);
1925 s = (result & 0x80000000);
1926
1927 /* Store the result and condition codes. */
1928 State.regs[OP[1]] = result;
1929 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1930 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1931 trace_output (OP_REG_REG);
1932
1933 return 2;
1934 }
1935
1936 /* andi zero_extend(imm16), reg, reg */
1937 int
1938 OP_6C0 ()
1939 {
1940 unsigned int result, z;
1941
1942 trace_input ("andi", OP_UIMM_REG_REG, 0);
1943
1944 result = OP[2] & State.regs[ OP[0] ];
1945
1946 /* Compute the condition codes. */
1947 z = (result == 0);
1948
1949 /* Store the result and condition codes. */
1950 State.regs[ OP[1] ] = result;
1951
1952 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1953 PSW |= (z ? PSW_Z : 0);
1954
1955 trace_output (OP_UIMM_REG_REG);
1956
1957 return 4;
1958 }
1959
1960 /* xor reg, reg */
1961 int
1962 OP_120 ()
1963 {
1964 unsigned int op0, op1, result, z, s;
1965
1966 trace_input ("xor", OP_REG_REG, 0);
1967
1968 /* Compute the result. */
1969 op0 = State.regs[ OP[0] ];
1970 op1 = State.regs[ OP[1] ];
1971 result = op0 ^ op1;
1972
1973 /* Compute the condition codes. */
1974 z = (result == 0);
1975 s = (result & 0x80000000);
1976
1977 /* Store the result and condition codes. */
1978 State.regs[OP[1]] = result;
1979 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1980 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1981 trace_output (OP_REG_REG);
1982
1983 return 2;
1984 }
1985
1986 /* xori zero_extend(imm16), reg, reg */
1987 int
1988 OP_6A0 ()
1989 {
1990 unsigned int op0, op1, result, z, s;
1991
1992 trace_input ("xori", OP_UIMM_REG_REG, 0);
1993 op0 = OP[2];
1994 op1 = State.regs[ OP[0] ];
1995 result = op0 ^ op1;
1996
1997 /* Compute the condition codes. */
1998 z = (result == 0);
1999 s = (result & 0x80000000);
2000
2001 /* Store the result and condition codes. */
2002 State.regs[OP[1]] = result;
2003 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2004 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2005 trace_output (OP_UIMM_REG_REG);
2006
2007 return 4;
2008 }
2009
2010 /* not reg1, reg2 */
2011 int
2012 OP_20 ()
2013 {
2014 unsigned int op0, result, z, s;
2015
2016 trace_input ("not", OP_REG_REG_MOVE, 0);
2017 /* Compute the result. */
2018 op0 = State.regs[ OP[0] ];
2019 result = ~op0;
2020
2021 /* Compute the condition codes. */
2022 z = (result == 0);
2023 s = (result & 0x80000000);
2024
2025 /* Store the result and condition codes. */
2026 State.regs[OP[1]] = result;
2027 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2028 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2029 trace_output (OP_REG_REG_MOVE);
2030
2031 return 2;
2032 }
2033
2034 /* set1 */
2035 int
2036 OP_7C0 ()
2037 {
2038 unsigned int op0, op1, op2;
2039 int temp;
2040
2041 trace_input ("set1", OP_BIT, 0);
2042 op0 = State.regs[ OP[0] ];
2043 op1 = OP[1] & 0x7;
2044 temp = SEXT16 (OP[2]);
2045 op2 = temp;
2046 temp = load_mem (op0 + op2, 1);
2047 PSW &= ~PSW_Z;
2048 if ((temp & (1 << op1)) == 0)
2049 PSW |= PSW_Z;
2050 temp |= (1 << op1);
2051 store_mem (op0 + op2, 1, temp);
2052 trace_output (OP_BIT);
2053
2054 return 4;
2055 }
2056
2057 /* not1 */
2058 int
2059 OP_47C0 ()
2060 {
2061 unsigned int op0, op1, op2;
2062 int temp;
2063
2064 trace_input ("not1", OP_BIT, 0);
2065 op0 = State.regs[ OP[0] ];
2066 op1 = OP[1] & 0x7;
2067 temp = SEXT16 (OP[2]);
2068 op2 = temp;
2069 temp = load_mem (op0 + op2, 1);
2070 PSW &= ~PSW_Z;
2071 if ((temp & (1 << op1)) == 0)
2072 PSW |= PSW_Z;
2073 temp ^= (1 << op1);
2074 store_mem (op0 + op2, 1, temp);
2075 trace_output (OP_BIT);
2076
2077 return 4;
2078 }
2079
2080 /* clr1 */
2081 int
2082 OP_87C0 ()
2083 {
2084 unsigned int op0, op1, op2;
2085 int temp;
2086
2087 trace_input ("clr1", OP_BIT, 0);
2088 op0 = State.regs[ OP[0] ];
2089 op1 = OP[1] & 0x7;
2090 temp = SEXT16 (OP[2]);
2091 op2 = temp;
2092 temp = load_mem (op0 + op2, 1);
2093 PSW &= ~PSW_Z;
2094 if ((temp & (1 << op1)) == 0)
2095 PSW |= PSW_Z;
2096 temp &= ~(1 << op1);
2097 store_mem (op0 + op2, 1, temp);
2098 trace_output (OP_BIT);
2099
2100 return 4;
2101 }
2102
2103 /* tst1 */
2104 int
2105 OP_C7C0 ()
2106 {
2107 unsigned int op0, op1, op2;
2108 int temp;
2109
2110 trace_input ("tst1", OP_BIT, 0);
2111 op0 = State.regs[ OP[0] ];
2112 op1 = OP[1] & 0x7;
2113 temp = SEXT16 (OP[2]);
2114 op2 = temp;
2115 temp = load_mem (op0 + op2, 1);
2116 PSW &= ~PSW_Z;
2117 if ((temp & (1 << op1)) == 0)
2118 PSW |= PSW_Z;
2119 trace_output (OP_BIT);
2120
2121 return 4;
2122 }
2123
2124 /* breakpoint */
2125 int
2126 OP_FFFF ()
2127 {
2128 State.exception = SIGTRAP;
2129 return -4;
2130 }
2131
2132 /* di */
2133 int
2134 OP_16007E0 ()
2135 {
2136 trace_input ("di", OP_NONE, 0);
2137 PSW |= PSW_ID;
2138 trace_output (OP_NONE);
2139
2140 return 4;
2141 }
2142
2143 /* ei */
2144 int
2145 OP_16087E0 ()
2146 {
2147 trace_input ("ei", OP_NONE, 0);
2148 PSW &= ~PSW_ID;
2149 trace_output (OP_NONE);
2150
2151 return 4;
2152 }
2153
2154 /* halt */
2155 int
2156 OP_12007E0 ()
2157 {
2158 trace_input ("halt", OP_NONE, 0);
2159 /* FIXME this should put processor into a mode where NMI still handled */
2160 State.exception = SIGQUIT;
2161 trace_output (OP_NONE);
2162
2163 return 4;
2164 }
2165
2166 /* reti */
2167 int
2168 OP_14007E0 ()
2169 {
2170 trace_input ("reti", OP_NONE, 0);
2171 trace_output (OP_NONE);
2172
2173 /* Restore for NMI if only NP on, otherwise is interrupt or exception. */
2174 if ((PSW & (PSW_NP | PSW_EP)) == PSW_NP)
2175 {
2176 PC = FEPC - 4;
2177 PSW = FEPSW;
2178 }
2179 else
2180 {
2181 PC = EIPC - 4;
2182 PSW = EIPSW;
2183 }
2184
2185 return 0;
2186 }
2187
2188 /* trap */
2189 int
2190 OP_10007E0 ()
2191 {
2192 trace_input ("trap", OP_TRAP, 0);
2193 trace_output (OP_TRAP);
2194
2195 /* Trap 31 is used for simulating OS I/O functions */
2196
2197 if (OP[0] == 31)
2198 {
2199 int save_errno = errno;
2200 errno = 0;
2201
2202 /* Registers passed to trap 0 */
2203
2204 #define FUNC State.regs[6] /* function number, return value */
2205 #define PARM1 State.regs[7] /* optional parm 1 */
2206 #define PARM2 State.regs[8] /* optional parm 2 */
2207 #define PARM3 State.regs[9] /* optional parm 3 */
2208
2209 /* Registers set by trap 0 */
2210
2211 #define RETVAL State.regs[10] /* return value */
2212 #define RETERR State.regs[11] /* return error code */
2213
2214 /* Turn a pointer in a register into a pointer into real memory. */
2215
2216 #define MEMPTR(x) (map (x))
2217
2218 switch (FUNC)
2219 {
2220
2221 #if !defined(__GO32__) && !defined(_WIN32)
2222 #ifdef SYS_fork
2223 case SYS_fork:
2224 RETVAL = fork ();
2225 break;
2226 #endif
2227 #endif
2228
2229 #if !defined(__GO32__) && !defined(_WIN32)
2230 #ifdef SYS_execv
2231 case SYS_execve:
2232 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2233 (char **)MEMPTR (PARM3));
2234 break;
2235 #endif
2236 #endif
2237
2238 #if !defined(__GO32__) && !defined(_WIN32)
2239 #ifdef SYS_execv
2240 case SYS_execv:
2241 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2242 break;
2243 #endif
2244 #endif
2245
2246 #if 0
2247 #ifdef SYS_pipe
2248 case SYS_pipe:
2249 {
2250 reg_t buf;
2251 int host_fd[2];
2252
2253 buf = PARM1;
2254 RETVAL = pipe (host_fd);
2255 SW (buf, host_fd[0]);
2256 buf += sizeof(uint16);
2257 SW (buf, host_fd[1]);
2258 }
2259 break;
2260 #endif
2261 #endif
2262
2263 #if 0
2264 #ifdef SYS_wait
2265 case SYS_wait:
2266 {
2267 int status;
2268
2269 RETVAL = wait (&status);
2270 SW (PARM1, status);
2271 }
2272 break;
2273 #endif
2274 #endif
2275
2276 #ifdef SYS_read
2277 case SYS_read:
2278 RETVAL = v850_callback->read (v850_callback, PARM1, MEMPTR (PARM2),
2279 PARM3);
2280 break;
2281 #endif
2282
2283 #ifdef SYS_write
2284 case SYS_write:
2285 if (PARM1 == 1)
2286 RETVAL = (int)v850_callback->write_stdout (v850_callback,
2287 MEMPTR (PARM2), PARM3);
2288 else
2289 RETVAL = (int)v850_callback->write (v850_callback, PARM1,
2290 MEMPTR (PARM2), PARM3);
2291 break;
2292 #endif
2293
2294 #ifdef SYS_lseek
2295 case SYS_lseek:
2296 RETVAL = v850_callback->lseek (v850_callback, PARM1, PARM2, PARM3);
2297 break;
2298 #endif
2299
2300 #ifdef SYS_close
2301 case SYS_close:
2302 RETVAL = v850_callback->close (v850_callback, PARM1);
2303 break;
2304 #endif
2305
2306 #ifdef SYS_open
2307 case SYS_open:
2308 RETVAL = v850_callback->open (v850_callback, MEMPTR (PARM1), PARM2);
2309 break;
2310 #endif
2311
2312 #ifdef SYS_exit
2313 case SYS_exit:
2314 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
2315 State.exception = PARM1 & 0xffff; /* get signal encoded by kill */
2316 else if (PARM1 == 0xdead)
2317 State.exception = SIGABRT; /* old libraries */
2318 else
2319 State.exception = SIG_V850_EXIT; /* PARM1 has exit status encoded */
2320 break;
2321 #endif
2322
2323 #if !defined(__GO32__) && !defined(_WIN32)
2324 #ifdef SYS_stat
2325 case SYS_stat: /* added at hmsi */
2326 /* stat system call */
2327 {
2328 struct stat host_stat;
2329 reg_t buf;
2330
2331 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2332
2333 buf = PARM2;
2334
2335 /* Just wild-assed guesses. */
2336 store_mem (buf, 2, host_stat.st_dev);
2337 store_mem (buf + 2, 2, host_stat.st_ino);
2338 store_mem (buf + 4, 4, host_stat.st_mode);
2339 store_mem (buf + 8, 2, host_stat.st_nlink);
2340 store_mem (buf + 10, 2, host_stat.st_uid);
2341 store_mem (buf + 12, 2, host_stat.st_gid);
2342 store_mem (buf + 14, 2, host_stat.st_rdev);
2343 store_mem (buf + 16, 4, host_stat.st_size);
2344 store_mem (buf + 20, 4, host_stat.st_atime);
2345 store_mem (buf + 28, 4, host_stat.st_mtime);
2346 store_mem (buf + 36, 4, host_stat.st_ctime);
2347 }
2348 break;
2349 #endif
2350 #endif
2351
2352 #if !defined(__GO32__) && !defined(_WIN32)
2353 #ifdef SYS_chown
2354 case SYS_chown:
2355 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2356 break;
2357 #endif
2358 #endif
2359
2360 #ifdef SYS_chmod
2361 #if HAVE_CHMOD
2362 case SYS_chmod:
2363 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2364 break;
2365 #endif
2366 #endif
2367
2368 #ifdef SYS_time
2369 #if HAVE_TIME
2370 case SYS_time:
2371 {
2372 time_t now;
2373 RETVAL = time (&now);
2374 store_mem (PARM1, 4, now);
2375 }
2376 break;
2377 #endif
2378 #endif
2379
2380 #if !defined(__GO32__) && !defined(_WIN32)
2381 #ifdef SYS_times
2382 case SYS_times:
2383 {
2384 struct tms tms;
2385 RETVAL = times (&tms);
2386 store_mem (PARM1, 4, tms.tms_utime);
2387 store_mem (PARM1 + 4, 4, tms.tms_stime);
2388 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2389 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2390 break;
2391 }
2392 #endif
2393 #endif
2394
2395 #ifdef SYS_gettimeofday
2396 #if !defined(__GO32__) && !defined(_WIN32)
2397 case SYS_gettimeofday:
2398 {
2399 struct timeval t;
2400 struct timezone tz;
2401 RETVAL = gettimeofday (&t, &tz);
2402 store_mem (PARM1, 4, t.tv_sec);
2403 store_mem (PARM1 + 4, 4, t.tv_usec);
2404 store_mem (PARM2, 4, tz.tz_minuteswest);
2405 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2406 break;
2407 }
2408 #endif
2409 #endif
2410
2411 #if !defined(__GO32__) && !defined(_WIN32)
2412 #ifdef SYS_utime
2413 case SYS_utime:
2414 /* Cast the second argument to void *, to avoid type mismatch
2415 if a prototype is present. */
2416 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2417 break;
2418 #endif
2419 #endif
2420
2421 default:
2422 abort ();
2423 }
2424 RETERR = errno;
2425 errno = save_errno;
2426
2427 return 4;
2428 }
2429 else
2430 { /* Trap 0 -> 30 */
2431 EIPC = PC + 4;
2432 EIPSW = PSW;
2433 /* Mask out EICC */
2434 ECR &= 0xffff0000;
2435 ECR |= 0x40 + OP[0];
2436 /* Flag that we are now doing exception processing. */
2437 PSW |= PSW_EP | PSW_ID;
2438 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
2439
2440 return 0;
2441 }
2442 }
2443
2444 /* ldsr, reg,reg */
2445 int
2446 OP_2007E0 ()
2447 {
2448 trace_input ("ldsr", OP_LDSR, 0);
2449
2450 State.sregs[ OP[1] ] = State.regs[ OP[0] ];
2451
2452 trace_output (OP_LDSR);
2453
2454 return 4;
2455 }
2456
2457 /* stsr */
2458 int
2459 OP_4007E0 ()
2460 {
2461 unsigned int op0;
2462
2463 trace_input ("stsr", OP_STSR, 0);
2464
2465 State.regs[ OP[1] ] = State.sregs[ OP[0] ];
2466
2467 trace_output (OP_STSR);
2468
2469 return 4;
2470 }
2471
2472 /* tst1 reg2, [reg1] */
2473 int
2474 OP_E607E0 (void)
2475 {
2476 int temp;
2477
2478 trace_input ("tst1", OP_BIT_LOAD, 1);
2479
2480 temp = load_mem (State.regs[ OP[0] ], 1);
2481
2482 PSW &= ~PSW_Z;
2483 if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
2484 PSW |= PSW_Z;
2485
2486 trace_output (OP_BIT_LOAD);
2487
2488 return 4;
2489 }
2490
2491 /* mulu reg1, reg2, reg3 */
2492 int
2493 OP_22207E0 (void)
2494 {
2495 trace_input ("mulu", OP_REG_REG_REG, 0);
2496
2497 Multiply64 (false, State.regs[ OP[0] ]);
2498
2499 trace_output (OP_REG_REG_REG);
2500
2501 return 4;
2502 }
2503
2504 /* start-sanitize-v850e */
2505
2506 #define BIT_CHANGE_OP( name, binop ) \
2507 unsigned int bit; \
2508 unsigned int temp; \
2509 \
2510 trace_input (name, OP_BIT_CHANGE, 0); \
2511 \
2512 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
2513 temp = load_mem (State.regs[ OP[0] ], 1); \
2514 \
2515 PSW &= ~PSW_Z; \
2516 if ((temp & bit) == 0) \
2517 PSW |= PSW_Z; \
2518 temp binop bit; \
2519 \
2520 store_mem (State.regs[ OP[0] ], 1, temp); \
2521 \
2522 trace_output (OP_BIT_CHANGE); \
2523 \
2524 return 4;
2525
2526 /* clr1 reg2, [reg1] */
2527 int
2528 OP_E407E0 (void)
2529 {
2530 BIT_CHANGE_OP ("clr1", &= ~ );
2531 }
2532
2533 /* not1 reg2, [reg1] */
2534 int
2535 OP_E207E0 (void)
2536 {
2537 BIT_CHANGE_OP ("not1", ^= );
2538 }
2539
2540 /* set1 */
2541 int
2542 OP_E007E0 (void)
2543 {
2544 BIT_CHANGE_OP ("set1", |= );
2545 }
2546
2547 /* sasf */
2548 int
2549 OP_20007E0 (void)
2550 {
2551 trace_input ("sasf", OP_EX1, 0);
2552
2553 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2554
2555 trace_output (OP_EX1);
2556
2557 return 4;
2558 }
2559 /* end-sanitize-v850e */
2560
2561 /* start-sanitize-v850eq */
2562 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2563 static void
2564 divun
2565 (
2566 unsigned int N,
2567 unsigned long int als,
2568 unsigned long int sfi,
2569 unsigned long int * quotient_ptr,
2570 unsigned long int * remainder_ptr,
2571 boolean * overflow_ptr
2572 )
2573 {
2574 unsigned long ald = sfi >> N - 1;
2575 unsigned long alo = als;
2576 unsigned int Q = 1;
2577 unsigned int C;
2578 unsigned int S = 0;
2579 unsigned int i;
2580 unsigned int R1 = 1;
2581 unsigned int OV;
2582 unsigned int DBZ = (als == 0) ? 1 : 0;
2583 unsigned long alt = Q ? ~als : als;
2584
2585 /* 1st Loop */
2586 alo = ald + alt + Q;
2587 C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
2588 C = C ^ Q;
2589 Q = ~(C ^ S) & 1;
2590 R1 = (alo == 0) ? 0 : (R1 & Q);
2591 if ((S ^ (alo>>31)) && !C)
2592 {
2593 DBZ = 1;
2594 }
2595 S = alo >> 31;
2596 sfi = (sfi << (32-N+1)) | Q;
2597 ald = (alo << 1) | (sfi >> 31);
2598
2599 /* 2nd - N-1th Loop */
2600 for (i = 2; i < N; i++)
2601 {
2602 alt = Q ? ~als : als;
2603 alo = ald + alt + Q;
2604 C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
2605 C = C ^ Q;
2606 Q = ~(C ^ S) & 1;
2607 R1 = (alo == 0) ? 0 : (R1 & Q);
2608 if ((S ^ (alo>>31)) && !C && !DBZ)
2609 {
2610 DBZ = 1;
2611 }
2612 S = alo >> 31;
2613 sfi = (sfi << 1) | Q;
2614 ald = (alo << 1) | (sfi >> 31);
2615 }
2616
2617 /* Nth Loop */
2618 alt = Q ? ~als : als;
2619 alo = ald + alt + Q;
2620 C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
2621 C = C ^ Q;
2622 Q = ~(C ^ S) & 1;
2623 R1 = (alo == 0) ? 0 : (R1 & Q);
2624 if ((S ^ (alo>>31)) && !C)
2625 {
2626 DBZ = 1;
2627 }
2628
2629 * quotient_ptr = (sfi << 1) | Q;
2630 * remainder_ptr = Q ? alo : (alo + als);
2631 * overflow_ptr = DBZ | R1;
2632 }
2633
2634 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2635 static void
2636 divn
2637 (
2638 unsigned int N,
2639 unsigned long int als,
2640 unsigned long int sfi,
2641 signed long int * quotient_ptr,
2642 signed long int * remainder_ptr,
2643 boolean * overflow_ptr
2644 )
2645 {
2646 unsigned long ald = (signed long) sfi >> (N - 1);
2647 unsigned long alo = als;
2648 unsigned int SS = als >> 31;
2649 unsigned int SD = sfi >> 31;
2650 unsigned int R1 = 1;
2651 unsigned int OV;
2652 unsigned int DBZ = als == 0 ? 1 : 0;
2653 unsigned int Q = ~(SS ^ SD) & 1;
2654 unsigned int C;
2655 unsigned int S;
2656 unsigned int i;
2657 unsigned long alt = Q ? ~als : als;
2658
2659
2660 /* 1st Loop */
2661
2662 alo = ald + alt + Q;
2663 C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
2664 Q = C ^ SS;
2665 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2666 S = alo >> 31;
2667 sfi = (sfi << (32-N+1)) | Q;
2668 ald = (alo << 1) | (sfi >> 31);
2669 if ((alo >> 31) ^ (ald >> 31))
2670 {
2671 DBZ = 1;
2672 }
2673
2674 /* 2nd - N-1th Loop */
2675
2676 for (i = 2; i < N; i++)
2677 {
2678 alt = Q ? ~als : als;
2679 alo = ald + alt + Q;
2680 C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
2681 Q = C ^ SS;
2682 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2683 S = alo >> 31;
2684 sfi = (sfi << 1) | Q;
2685 ald = (alo << 1) | (sfi >> 31);
2686 if ((alo >> 31) ^ (ald >> 31))
2687 {
2688 DBZ = 1;
2689 }
2690 }
2691
2692 /* Nth Loop */
2693 alt = Q ? ~als : als;
2694 alo = ald + alt + Q;
2695 C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
2696 Q = C ^ SS;
2697 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2698 sfi = (sfi << (32-N+1));
2699 ald = alo;
2700
2701 /* End */
2702 if (alo != 0)
2703 {
2704 alt = Q ? ~als : als;
2705 alo = ald + alt + Q;
2706 }
2707 R1 = R1 & ((~alo >> 31) ^ SD);
2708 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2709 if (N != 32)
2710 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2711 else
2712 ald = sfi = sfi | Q;
2713
2714 OV = DBZ | ((alo == 0) ? 0 : R1);
2715
2716 * remainder_ptr = alo;
2717
2718 /* Adj */
2719 if ((alo != 0) && ((SS ^ SD) ^ R1) || (alo == 0) && (SS ^ R1))
2720 alo = ald + 1;
2721 else
2722 alo = ald;
2723
2724 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2725
2726 * quotient_ptr = alo;
2727 * overflow_ptr = OV;
2728 }
2729
2730 /* sdivun imm5, reg1, reg2, reg3 */
2731 int
2732 OP_1C207E0 (void)
2733 {
2734 unsigned long int quotient;
2735 unsigned long int remainder;
2736 unsigned long int divide_by;
2737 unsigned long int divide_this;
2738 boolean overflow = false;
2739 unsigned int imm5;
2740
2741 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2742
2743 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2744
2745 divide_by = State.regs[ OP[0] ];
2746 divide_this = State.regs[ OP[1] ] << imm5;
2747
2748 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2749
2750 State.regs[ OP[1] ] = quotient;
2751 State.regs[ OP[2] >> 11 ] = remainder;
2752
2753 /* Set condition codes. */
2754 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2755
2756 if (overflow) PSW |= PSW_OV;
2757 if (quotient == 0) PSW |= PSW_Z;
2758 if (quotient & 0x80000000) PSW |= PSW_S;
2759
2760 trace_output (OP_IMM_REG_REG_REG);
2761
2762 return 4;
2763 }
2764
2765 /* sdivn imm5, reg1, reg2, reg3 */
2766 int
2767 OP_1C007E0 (void)
2768 {
2769 signed long int quotient;
2770 signed long int remainder;
2771 signed long int divide_by;
2772 signed long int divide_this;
2773 boolean overflow = false;
2774 unsigned int imm5;
2775
2776 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2777
2778 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2779
2780 divide_by = State.regs[ OP[0] ];
2781 divide_this = State.regs[ OP[1] ] << imm5;
2782
2783 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2784
2785 State.regs[ OP[1] ] = quotient;
2786 State.regs[ OP[2] >> 11 ] = remainder;
2787
2788 /* Set condition codes. */
2789 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2790
2791 if (overflow) PSW |= PSW_OV;
2792 if (quotient == 0) PSW |= PSW_Z;
2793 if (quotient < 0) PSW |= PSW_S;
2794
2795 trace_output (OP_IMM_REG_REG_REG);
2796
2797 return 4;
2798 }
2799
2800 /* sdivhun imm5, reg1, reg2, reg3 */
2801 int
2802 OP_18207E0 (void)
2803 {
2804 unsigned long int quotient;
2805 unsigned long int remainder;
2806 unsigned long int divide_by;
2807 unsigned long int divide_this;
2808 boolean overflow = false;
2809 unsigned int imm5;
2810
2811 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2812
2813 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2814
2815 divide_by = State.regs[ OP[0] ] & 0xffff;
2816 divide_this = State.regs[ OP[1] ] << imm5;
2817
2818 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2819
2820 State.regs[ OP[1] ] = quotient;
2821 State.regs[ OP[2] >> 11 ] = remainder;
2822
2823 /* Set condition codes. */
2824 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2825
2826 if (overflow) PSW |= PSW_OV;
2827 if (quotient == 0) PSW |= PSW_Z;
2828 if (quotient & 0x80000000) PSW |= PSW_S;
2829
2830 trace_output (OP_IMM_REG_REG_REG);
2831
2832 return 4;
2833 }
2834
2835 /* sdivhn imm5, reg1, reg2, reg3 */
2836 int
2837 OP_18007E0 (void)
2838 {
2839 signed long int quotient;
2840 signed long int remainder;
2841 signed long int divide_by;
2842 signed long int divide_this;
2843 boolean overflow = false;
2844 unsigned int imm5;
2845
2846 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2847
2848 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2849
2850 divide_by = SEXT16 (State.regs[ OP[0] ]);
2851 divide_this = State.regs[ OP[1] ] << imm5;
2852
2853 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2854
2855 State.regs[ OP[1] ] = quotient;
2856 State.regs[ OP[2] >> 11 ] = remainder;
2857
2858 /* Set condition codes. */
2859 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2860
2861 if (overflow) PSW |= PSW_OV;
2862 if (quotient == 0) PSW |= PSW_Z;
2863 if (quotient < 0) PSW |= PSW_S;
2864
2865 trace_output (OP_IMM_REG_REG_REG);
2866
2867 return 4;
2868 }
2869 /* end-sanitize-v850eq */
2870
2871 /* start-sanitize-v850e */
2872 /* divu reg1, reg2, reg3 */
2873 int
2874 OP_2C207E0 (void)
2875 {
2876 unsigned long int quotient;
2877 unsigned long int remainder;
2878 unsigned long int divide_by;
2879 unsigned long int divide_this;
2880 boolean overflow = false;
2881
2882 if ((OP[3] & 0x3c0000) == 0)
2883 {
2884 trace_input ("divu", OP_REG_REG_REG, 0);
2885
2886 /* Compute the result. */
2887
2888 divide_by = State.regs[ OP[0] ];
2889 divide_this = State.regs[ OP[1] ];
2890
2891 if (divide_by == 0)
2892 {
2893 overflow = true;
2894 divide_by = 1;
2895 }
2896
2897 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2898 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2899
2900 /* Set condition codes. */
2901 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2902
2903 if (overflow) PSW |= PSW_OV;
2904 if (quotient == 0) PSW |= PSW_Z;
2905 if (quotient & 0x80000000) PSW |= PSW_S;
2906
2907 trace_output (OP_REG_REG_REG);
2908 }
2909 /* start-sanitize-v850eq */
2910 /* divun imm5, reg1, reg2, reg3 */
2911 else
2912 {
2913 unsigned int imm5;
2914
2915 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
2916
2917 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2918
2919 divide_by = State.regs[ OP[0] ];
2920 divide_this = State.regs[ OP[1] ];
2921
2922 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2923
2924 State.regs[ OP[1] ] = quotient;
2925 State.regs[ OP[2] >> 11 ] = remainder;
2926
2927 /* Set condition codes. */
2928 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2929
2930 if (overflow) PSW |= PSW_OV;
2931 if (quotient == 0) PSW |= PSW_Z;
2932 if (quotient & 0x80000000) PSW |= PSW_S;
2933
2934 trace_output (OP_IMM_REG_REG_REG);
2935 }
2936 /* end-sanitize-v850eq */
2937
2938 return 4;
2939 }
2940
2941 /* div reg1, reg2, reg3 */
2942 int
2943 OP_2C007E0 (void)
2944 {
2945 signed long int quotient;
2946 signed long int remainder;
2947 signed long int divide_by;
2948 signed long int divide_this;
2949 boolean overflow = false;
2950
2951 if ((OP[3] & 0x3c0000) == 0)
2952 {
2953 trace_input ("div", OP_REG_REG_REG, 0);
2954
2955 /* Compute the result. */
2956
2957 divide_by = State.regs[ OP[0] ];
2958 divide_this = State.regs[ OP[1] ];
2959
2960 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2961 {
2962 overflow = true;
2963 divide_by = 1;
2964 }
2965
2966 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2967 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2968
2969 /* Set condition codes. */
2970 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2971
2972 if (overflow) PSW |= PSW_OV;
2973 if (quotient == 0) PSW |= PSW_Z;
2974 if (quotient < 0) PSW |= PSW_S;
2975
2976 trace_output (OP_REG_REG_REG);
2977 }
2978 /* start-sanitize-v850eq */
2979 /* divn imm5, reg1, reg2, reg3 */
2980 else
2981 {
2982 unsigned int imm5;
2983
2984 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
2985
2986 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2987
2988 divide_by = State.regs[ OP[0] ];
2989 divide_this = State.regs[ OP[1] ];
2990
2991 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2992
2993 State.regs[ OP[1] ] = quotient;
2994 State.regs[ OP[2] >> 11 ] = remainder;
2995
2996 /* Set condition codes. */
2997 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2998
2999 if (overflow) PSW |= PSW_OV;
3000 if (quotient == 0) PSW |= PSW_Z;
3001 if (quotient < 0) PSW |= PSW_S;
3002
3003 trace_output (OP_IMM_REG_REG_REG);
3004 }
3005 /* end-sanitize-v850eq */
3006
3007 return 4;
3008 }
3009
3010 /* divhu reg1, reg2, reg3 */
3011 int
3012 OP_28207E0 (void)
3013 {
3014 unsigned long int quotient;
3015 unsigned long int remainder;
3016 unsigned long int divide_by;
3017 unsigned long int divide_this;
3018 boolean overflow = false;
3019
3020 if ((OP[3] & 0x3c0000) == 0)
3021 {
3022 trace_input ("divhu", OP_REG_REG_REG, 0);
3023
3024 /* Compute the result. */
3025
3026 divide_by = State.regs[ OP[0] ] & 0xffff;
3027 divide_this = State.regs[ OP[1] ];
3028
3029 if (divide_by == 0)
3030 {
3031 overflow = true;
3032 divide_by = 1;
3033 }
3034
3035 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3036 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3037
3038 /* Set condition codes. */
3039 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3040
3041 if (overflow) PSW |= PSW_OV;
3042 if (quotient == 0) PSW |= PSW_Z;
3043 if (quotient & 0x80000000) PSW |= PSW_S;
3044
3045 trace_output (OP_REG_REG_REG);
3046 }
3047 /* start-sanitize-v850eq */
3048 /* divhun imm5, reg1, reg2, reg3 */
3049 else
3050 {
3051 unsigned int imm5;
3052
3053 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
3054
3055 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3056
3057 divide_by = State.regs[ OP[0] ] & 0xffff;
3058 divide_this = State.regs[ OP[1] ];
3059
3060 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3061
3062 State.regs[ OP[1] ] = quotient;
3063 State.regs[ OP[2] >> 11 ] = remainder;
3064
3065 /* Set condition codes. */
3066 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3067
3068 if (overflow) PSW |= PSW_OV;
3069 if (quotient == 0) PSW |= PSW_Z;
3070 if (quotient & 0x80000000) PSW |= PSW_S;
3071
3072 trace_output (OP_IMM_REG_REG_REG);
3073 }
3074 /* end-sanitize-v850eq */
3075
3076 return 4;
3077 }
3078
3079 /* divh reg1, reg2, reg3 */
3080 int
3081 OP_28007E0 (void)
3082 {
3083 signed long int quotient;
3084 signed long int remainder;
3085 signed long int divide_by;
3086 signed long int divide_this;
3087 boolean overflow = false;
3088
3089 if ((OP[3] & 0x3c0000) == 0)
3090 {
3091 trace_input ("divh", OP_REG_REG_REG, 0);
3092
3093 /* Compute the result. */
3094
3095 divide_by = State.regs[ OP[0] ];
3096 divide_this = SEXT16 (State.regs[ OP[1] ]);
3097
3098 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3099 {
3100 overflow = true;
3101 divide_by = 1;
3102 }
3103
3104 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3105 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3106
3107 /* Set condition codes. */
3108 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3109
3110 if (overflow) PSW |= PSW_OV;
3111 if (quotient == 0) PSW |= PSW_Z;
3112 if (quotient < 0) PSW |= PSW_S;
3113
3114 trace_output (OP_REG_REG_REG);
3115 }
3116 /* start-sanitize-v850eq */
3117 /* divhn imm5, reg1, reg2, reg3 */
3118 else
3119 {
3120 unsigned int imm5;
3121
3122 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
3123
3124 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3125
3126 divide_by = SEXT16 (State.regs[ OP[0] ]);
3127 divide_this = State.regs[ OP[1] ];
3128
3129 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3130
3131 State.regs[ OP[1] ] = quotient;
3132 State.regs[ OP[2] >> 11 ] = remainder;
3133
3134 /* Set condition codes. */
3135 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3136
3137 if (overflow) PSW |= PSW_OV;
3138 if (quotient == 0) PSW |= PSW_Z;
3139 if (quotient < 0) PSW |= PSW_S;
3140
3141 trace_output (OP_IMM_REG_REG_REG);
3142 }
3143 /* end-sanitize-v850eq */
3144
3145 return 4;
3146 }
3147
3148 /* mulu imm9, reg2, reg3 */
3149 int
3150 OP_24207E0 (void)
3151 {
3152 trace_input ("mulu", OP_IMM_REG_REG, 0);
3153
3154 Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
3155
3156 trace_output (OP_IMM_REG_REG);
3157
3158 return 4;
3159 }
3160
3161 /* mul imm9, reg2, reg3 */
3162 int
3163 OP_24007E0 (void)
3164 {
3165 trace_input ("mul", OP_IMM_REG_REG, 0);
3166
3167 Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
3168
3169 trace_output (OP_IMM_REG_REG);
3170
3171 return 4;
3172 }
3173
3174 /* cmov imm5, reg2, reg3 */
3175 int
3176 OP_30007E0 (void)
3177 {
3178 trace_input ("cmov", OP_IMM_REG_REG, 0);
3179
3180 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? SEXT5( OP[0] ) : State.regs[ OP[1] ];
3181
3182 trace_output (OP_IMM_REG_REG);
3183
3184 return 4;
3185
3186 }
3187
3188 /* ctret */
3189 int
3190 OP_14407E0 (void)
3191 {
3192 trace_input ("ctret", OP_NONE, 0);
3193
3194 PC = CTPC;
3195 PSW = CTPSW;
3196
3197 trace_output (OP_NONE);
3198
3199 return 0;
3200 }
3201
3202 /* hsw */
3203 int
3204 OP_34407E0 (void)
3205 {
3206 unsigned long value;
3207
3208 trace_input ("hsw", OP_REG_REG3, 0);
3209
3210 value = State.regs[ OP[ 1 ] ];
3211 value >>= 16;
3212 value |= (State.regs[ OP[ 1 ] ] << 16);
3213
3214 State.regs[ OP[2] >> 11 ] = value;
3215
3216 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3217
3218 if (value == 0) PSW |= PSW_Z;
3219 if (value & 0x80000000) PSW |= PSW_S;
3220 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
3221
3222 trace_output (OP_REG_REG3);
3223
3224 return 4;
3225 }
3226
3227 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
3228
3229 /* bsw */
3230 int
3231 OP_34007E0 (void)
3232 {
3233 unsigned long value;
3234
3235 trace_input ("bsw", OP_REG_REG3, 0);
3236
3237 value = State.regs[ OP[ 1 ] ];
3238 value >>= 24;
3239 value |= (State.regs[ OP[ 1 ] ] << 24);
3240 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0x00ff0000);
3241 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x0000ff00);
3242
3243 State.regs[ OP[2] >> 11 ] = value;
3244
3245 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3246
3247 if (value == 0) PSW |= PSW_Z;
3248 if (value & 0x80000000) PSW |= PSW_S;
3249 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
3250
3251 trace_output (OP_REG_REG3);
3252
3253 return 4;
3254 }
3255
3256 /* bsh */
3257 int
3258 OP_34207E0 (void)
3259 {
3260 unsigned long value;
3261
3262 trace_input ("bsh", OP_REG_REG3, 0);
3263
3264 value = State.regs[ OP[ 1 ] ];
3265 value >>= 8;
3266 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0xff00ff00);
3267 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x000000ff);
3268
3269 State.regs[ OP[2] >> 11 ] = value;
3270
3271 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3272
3273 if (value == 0) PSW |= PSW_Z;
3274 if (value & 0x80000000) PSW |= PSW_S;
3275 if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
3276
3277 trace_output (OP_REG_REG3);
3278
3279 return 4;
3280 }
3281
3282 /* pushml list18 */
3283 /* ld.hu */
3284 int
3285 OP_107E0 (void)
3286 {
3287 if (OP[ 1 ] == 0)
3288 {
3289 int i;
3290
3291 trace_input ("pushml", OP_PUSHPOP3, 0);
3292
3293 /* Store the registers with lower number registers being placed at higher addresses. */
3294 for (i = 0; i < 15; i++)
3295 if ((OP[3] & (1 << type3_regs[ i ])))
3296 {
3297 SP -= 4;
3298 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
3299 }
3300
3301 if (OP[3] & (1 << 3))
3302 {
3303 SP -= 4;
3304
3305 store_mem (SP & ~ 3, 4, PSW);
3306 }
3307
3308 if (OP[3] & (1 << 19))
3309 {
3310 SP -= 8;
3311
3312 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3313 {
3314 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3315 store_mem ( SP & ~ 3, 4, FEPSW);
3316 }
3317 else
3318 {
3319 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3320 store_mem ( SP & ~ 3, 4, EIPSW);
3321 }
3322 }
3323
3324 trace_output (OP_PUSHPOP2);
3325 }
3326 else
3327 {
3328 int adr;
3329
3330 trace_input ("ld.hu", OP_LOAD32, 2);
3331
3332 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
3333 adr &= ~0x1;
3334
3335 State.regs[ OP[1] ] = load_mem (adr, 2);
3336
3337 trace_output (OP_LOAD32);
3338 }
3339
3340 return 4;
3341 }
3342
3343 /* prepare list12, imm5 */
3344 /* ld.bu */
3345 int
3346 OP_10780 (void)
3347 {
3348 if (OP[ 1 ] == 0)
3349 {
3350 int i;
3351
3352 trace_input ("prepare", OP_PUSHPOP1, 0);
3353
3354 /* Store the registers with lower number registers being placed at higher addresses. */
3355 for (i = 0; i < 12; i++)
3356 if ((OP[3] & (1 << type1_regs[ i ])))
3357 {
3358 SP -= 4;
3359 store_mem (SP, 4, State.regs[ 20 + i ]);
3360 }
3361
3362 SP -= (OP[3] & 0x3e) << 1;
3363
3364 trace_output (OP_PUSHPOP1);
3365 }
3366 else
3367 {
3368 int adr;
3369
3370 trace_input ("ld.bu", OP_LOAD32, 1);
3371
3372 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1) | ((OP[3] >> 5) & 1);
3373
3374 State.regs[ OP[1] ] = load_mem (adr, 1);
3375
3376 trace_output (OP_LOAD32);
3377 }
3378
3379 return 4;
3380 }
3381
3382 /* prepare list12, imm5, imm32 */
3383 int
3384 OP_1B0780 (void)
3385 {
3386 int i;
3387
3388 trace_input ("prepare", OP_PUSHPOP1, 0);
3389
3390 /* Store the registers with lower number registers being placed at higher addresses. */
3391 for (i = 0; i < 12; i++)
3392 if ((OP[3] & (1 << type1_regs[ i ])))
3393 {
3394 SP -= 4;
3395 store_mem (SP, 4, State.regs[ 20 + i ]);
3396 }
3397
3398 SP -= (OP[3] & 0x3e) << 1;
3399
3400 EP = load_mem (PC + 4, 4);
3401
3402 trace_output (OP_PUSHPOP1);
3403
3404 return 8;
3405 }
3406
3407 /* prepare list12, imm5, imm16-32 */
3408 int
3409 OP_130780 (void)
3410 {
3411 int i;
3412
3413 trace_input ("prepare", OP_PUSHPOP1, 0);
3414
3415 /* Store the registers with lower number registers being placed at higher addresses. */
3416 for (i = 0; i < 12; i++)
3417 if ((OP[3] & (1 << type1_regs[ i ])))
3418 {
3419 SP -= 4;
3420 store_mem (SP, 4, State.regs[ 20 + i ]);
3421 }
3422
3423 SP -= (OP[3] & 0x3e) << 1;
3424
3425 EP = load_mem (PC + 4, 2) << 16;
3426
3427 trace_output (OP_PUSHPOP1);
3428
3429 return 6;
3430 }
3431
3432 /* prepare list12, imm5, imm16 */
3433 int
3434 OP_B0780 (void)
3435 {
3436 int i;
3437
3438 trace_input ("prepare", OP_PUSHPOP1, 0);
3439
3440 /* Store the registers with lower number registers being placed at higher addresses. */
3441 for (i = 0; i < 12; i++)
3442 if ((OP[3] & (1 << type1_regs[ i ])))
3443 {
3444 SP -= 4;
3445 store_mem (SP, 4, State.regs[ 20 + i ]);
3446 }
3447
3448 SP -= (OP[3] & 0x3e) << 1;
3449
3450 EP = SEXT16 (load_mem (PC + 4, 2));
3451
3452 trace_output (OP_PUSHPOP1);
3453
3454 return 6;
3455 }
3456
3457 /* prepare list12, imm5, sp */
3458 int
3459 OP_30780 (void)
3460 {
3461 int i;
3462
3463 trace_input ("prepare", OP_PUSHPOP1, 0);
3464
3465 /* Store the registers with lower number registers being placed at higher addresses. */
3466 for (i = 0; i < 12; i++)
3467 if ((OP[3] & (1 << type1_regs[ i ])))
3468 {
3469 SP -= 4;
3470 store_mem (SP, 4, State.regs[ 20 + i ]);
3471 }
3472
3473 SP -= (OP[3] & 0x3e) << 1;
3474
3475 EP = SP;
3476
3477 trace_output (OP_PUSHPOP1);
3478
3479 return 4;
3480 }
3481
3482 /* sld.hu */
3483 int
3484 OP_70 (void)
3485 {
3486 unsigned long result;
3487
3488 result = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
3489
3490 /* start-sanitize-v850eq */
3491 #ifdef ARCH_v850eq
3492 trace_input ("sld.h", OP_LOAD16, 2);
3493
3494 State.regs[ OP[1] ] = SEXT16 (result);
3495 #else
3496 /* end-sanitize-v850eq */
3497 trace_input ("sld.hu", OP_LOAD16, 2);
3498
3499 State.regs[ OP[1] ] = result;
3500 /* start-sanitize-v850eq */
3501 #endif
3502 /* end-sanitize-v850eq */
3503
3504 trace_output (OP_LOAD16);
3505
3506 return 2;
3507 }
3508
3509 /* cmov reg1, reg2, reg3 */
3510 int
3511 OP_32007E0 (void)
3512 {
3513 trace_input ("cmov", OP_REG_REG_REG, 0);
3514
3515 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
3516
3517 trace_output (OP_REG_REG_REG);
3518
3519 return 4;
3520 }
3521
3522 /* mul reg1, reg2, reg3 */
3523 int
3524 OP_22007E0 (void)
3525 {
3526 trace_input ("mul", OP_REG_REG_REG, 0);
3527
3528 Multiply64 (true, State.regs[ OP[0] ]);
3529
3530 trace_output (OP_REG_REG_REG);
3531
3532 return 4;
3533 }
3534
3535 /* end-sanitize-v850e */
3536 /* start-sanitize-v850eq */
3537
3538 /* popmh list18 */
3539 int
3540 OP_307F0 (void)
3541 {
3542 int i;
3543
3544 trace_input ("popmh", OP_PUSHPOP2, 0);
3545
3546 if (OP[3] & (1 << 19))
3547 {
3548 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3549 {
3550 FEPSW = load_mem ( SP & ~ 3, 4);
3551 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3552 }
3553 else
3554 {
3555 EIPSW = load_mem ( SP & ~ 3, 4);
3556 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3557 }
3558
3559 SP += 8;
3560 }
3561
3562 /* Load the registers with lower number registers being retrieved from higher addresses. */
3563 for (i = 16; i--;)
3564 if ((OP[3] & (1 << type2_regs[ i ])))
3565 {
3566 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
3567 SP += 4;
3568 }
3569
3570 trace_output (OP_PUSHPOP2);
3571
3572 return 4;
3573 }
3574
3575 /* popml lsit18 */
3576 int
3577 OP_107F0 (void)
3578 {
3579 int i;
3580
3581 trace_input ("popml", OP_PUSHPOP3, 0);
3582
3583 if (OP[3] & (1 << 19))
3584 {
3585 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3586 {
3587 FEPSW = load_mem ( SP & ~ 3, 4);
3588 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3589 }
3590 else
3591 {
3592 EIPSW = load_mem ( SP & ~ 3, 4);
3593 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3594 }
3595
3596 SP += 8;
3597 }
3598
3599 if (OP[3] & (1 << 3))
3600 {
3601 PSW = load_mem (SP & ~ 3, 4);
3602 SP += 4;
3603 }
3604
3605 /* Load the registers with lower number registers being retrieved from higher addresses. */
3606 for (i = 15; i--;)
3607 if ((OP[3] & (1 << type3_regs[ i ])))
3608 {
3609 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
3610 SP += 4;
3611 }
3612
3613 trace_output (OP_PUSHPOP2);
3614 }
3615
3616 /* pushmh list18 */
3617 int
3618 OP_307E0 (void)
3619 {
3620 int i;
3621
3622 trace_input ("pushmh", OP_PUSHPOP2, 0);
3623
3624 /* Store the registers with lower number registers being placed at higher addresses. */
3625 for (i = 0; i < 16; i++)
3626 if ((OP[3] & (1 << type2_regs[ i ])))
3627 {
3628 SP -= 4;
3629 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
3630 }
3631
3632 if (OP[3] & (1 << 19))
3633 {
3634 SP -= 8;
3635
3636 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3637 {
3638 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3639 store_mem ( SP & ~ 3, 4, FEPSW);
3640 }
3641 else
3642 {
3643 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3644 store_mem ( SP & ~ 3, 4, EIPSW);
3645 }
3646 }
3647
3648 trace_output (OP_PUSHPOP2);
3649
3650 return 4;
3651 }
3652
3653 /* end-sanitize-v850eq */