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Print line # and function name or filename if they exist for each PC.
[binutils-gdb.git] / sim / v850 / simops.c
1 #include <signal.h>
2 #include "v850_sim.h"
3 #include "simops.h"
4 #include "sys/syscall.h"
5 #include "bfd.h"
6
7 enum op_types {
8 OP_UNKNOWN,
9 OP_NONE,
10 OP_TRAP,
11 OP_REG,
12 OP_REG_REG,
13 OP_REG_REG_CMP,
14 OP_REG_REG_MOVE,
15 OP_IMM_REG,
16 OP_IMM_REG_CMP,
17 OP_IMM_REG_MOVE,
18 OP_COND_BR,
19 OP_LOAD16,
20 OP_STORE16,
21 OP_LOAD32,
22 OP_STORE32,
23 OP_JUMP,
24 OP_IMM_REG_REG,
25 OP_UIMM_REG_REG,
26 OP_BIT,
27 OP_EX1,
28 OP_EX2,
29 OP_LDSR,
30 OP_STSR
31 };
32
33 #ifdef DEBUG
34 static void trace_input PARAMS ((char *name, enum op_types type, int size));
35 static void trace_output PARAMS ((enum op_types result));
36 static int init_text_p = 0;
37 static asection *text;
38 static bfd_vma text_start;
39 static bfd_vma text_end;
40 extern bfd *sim_bfd;
41
42 #ifndef SIZE_INSTRUCTION
43 #define SIZE_INSTRUCTION 6
44 #endif
45
46 #ifndef SIZE_OPERANDS
47 #define SIZE_OPERANDS 16
48 #endif
49
50 #ifndef SIZE_VALUES
51 #define SIZE_VALUES 11
52 #endif
53
54 #ifndef SIZE_LOCATION
55 #define SIZE_LOCATION 40
56 #endif
57
58 static void
59 trace_input (name, type, size)
60 char *name;
61 enum op_types type;
62 int size;
63 {
64 char buf[1024];
65 char *p;
66 uint32 values[3];
67 int num_values, i;
68 char *cond;
69 asection *s;
70 const char *filename;
71 const char *functionname;
72 unsigned int linenumber;
73
74 if ((v850_debug & DEBUG_TRACE) == 0)
75 return;
76
77 buf[0] = '\0';
78 if (!init_text_p)
79 {
80 init_text_p = 1;
81 for (s = sim_bfd->sections; s; s = s->next)
82 if (strcmp (bfd_get_section_name (sim_bfd, s), ".text") == 0)
83 {
84 text = s;
85 text_start = bfd_get_section_vma (sim_bfd, s);
86 text_end = text_start + bfd_section_size (sim_bfd, s);
87 break;
88 }
89 }
90
91 if (text && PC >= text_start && PC < text_end)
92 {
93 filename = (const char *)0;
94 functionname = (const char *)0;
95 linenumber = 0;
96 if (bfd_find_nearest_line (sim_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
97 &filename, &functionname, &linenumber))
98 {
99 p = buf;
100 if (linenumber)
101 {
102 sprintf (p, "Line %5d ", linenumber);
103 p += strlen (p);
104 }
105
106 if (functionname)
107 {
108 sprintf (p, "Func %s ", functionname);
109 p += strlen (p);
110 }
111 else if (filename)
112 {
113 char *q = (char *) strrchr (filename, '/');
114 sprintf (p, "File %s ", (q) ? q+1 : filename);
115 p += strlen (p);
116 }
117
118 if (*p == ' ')
119 *p = '\0';
120 }
121 }
122
123 (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
124 (unsigned)PC,
125 SIZE_LOCATION, SIZE_LOCATION, buf,
126 SIZE_INSTRUCTION, name);
127
128 switch (type)
129 {
130 default:
131 case OP_UNKNOWN:
132 case OP_NONE:
133 strcpy (buf, "unknown");
134 break;
135
136 case OP_TRAP:
137 sprintf (buf, "%d", OP[0]);
138 break;
139
140 case OP_REG:
141 sprintf (buf, "r%d", OP[0]);
142 break;
143
144 case OP_REG_REG:
145 case OP_REG_REG_CMP:
146 case OP_REG_REG_MOVE:
147 sprintf (buf, "r%d,r%d", OP[0], OP[1]);
148 break;
149
150 case OP_IMM_REG:
151 case OP_IMM_REG_CMP:
152 case OP_IMM_REG_MOVE:
153 sprintf (buf, "%d,r%d", OP[1], OP[0]);
154 break;
155
156 case OP_COND_BR:
157 sprintf (buf, "%d", SEXT9 (OP[0]));
158 break;
159
160 case OP_LOAD16:
161 sprintf (buf, "%d[r30],r%d", SEXT7 (OP[1]) * size, OP[0]);
162 break;
163
164 case OP_STORE16:
165 sprintf (buf, "r%d,%d[r30]", OP[0], SEXT7 (OP[1]) * size);
166 break;
167
168 case OP_LOAD32:
169 sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]), OP[0], OP[1]);
170 break;
171
172 case OP_STORE32:
173 sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2]), OP[0]);
174 break;
175
176 case OP_JUMP:
177 sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
178 break;
179
180 case OP_IMM_REG_REG:
181 sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
182 break;
183
184 case OP_UIMM_REG_REG:
185 sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
186 break;
187
188 case OP_BIT:
189 sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
190 break;
191
192 case OP_EX1:
193 switch (OP[0] & 0xf)
194 {
195 default: cond = "?"; break;
196 case 0x0: cond = "v"; break;
197 case 0x1: cond = "c"; break;
198 case 0x2: cond = "z"; break;
199 case 0x3: cond = "nh"; break;
200 case 0x4: cond = "s"; break;
201 case 0x5: cond = "t"; break;
202 case 0x6: cond = "lt"; break;
203 case 0x7: cond = "le"; break;
204 case 0x8: cond = "nv"; break;
205 case 0x9: cond = "nc"; break;
206 case 0xa: cond = "nz"; break;
207 case 0xb: cond = "h"; break;
208 case 0xc: cond = "ns"; break;
209 case 0xd: cond = "sa"; break;
210 case 0xe: cond = "ge"; break;
211 case 0xf: cond = "gt"; break;
212 }
213
214 sprintf (buf, "%s,r%d", cond, OP[1]);
215 break;
216
217 case OP_EX2:
218 strcpy (buf, "EX2");
219 break;
220
221 case OP_LDSR:
222 case OP_STSR:
223 sprintf (buf, "r%d,s%d", OP[0], OP[1]);
224 break;
225 }
226
227 if ((v850_debug & DEBUG_VALUES) == 0)
228 {
229 (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
230 }
231 else
232 {
233 (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
234 switch (type)
235 {
236 default:
237 case OP_UNKNOWN:
238 case OP_NONE:
239 case OP_TRAP:
240 num_values = 0;
241 break;
242
243 case OP_REG:
244 case OP_REG_REG_MOVE:
245 values[0] = State.regs[OP[0]];
246 num_values = 1;
247 break;
248
249 case OP_REG_REG:
250 case OP_REG_REG_CMP:
251 values[0] = State.regs[OP[1]];
252 values[1] = State.regs[OP[0]];
253 num_values = 2;
254 break;
255
256 case OP_IMM_REG:
257 case OP_IMM_REG_CMP:
258 values[0] = SEXT5 (OP[0]);
259 values[1] = OP[1];
260 num_values = 2;
261 break;
262
263 case OP_IMM_REG_MOVE:
264 values[0] = SEXT5 (OP[0]);
265 num_values = 1;
266 break;
267
268 case OP_COND_BR:
269 values[0] = State.pc;
270 values[1] = SEXT9 (OP[0]);
271 values[2] = State.sregs[5];
272 num_values = 3;
273 break;
274
275 case OP_LOAD16:
276 values[0] = SEXT7 (OP[1]) * size;
277 values[1] = State.regs[30];
278 num_values = 2;
279 break;
280
281 case OP_STORE16:
282 values[0] = State.regs[OP[0]];
283 values[1] = SEXT7 (OP[1]) * size;
284 values[2] = State.regs[30];
285 num_values = 3;
286 break;
287
288 case OP_LOAD32:
289 values[0] = SEXT16 (OP[2]);
290 values[1] = State.regs[OP[0]];
291 num_values = 2;
292 break;
293
294 case OP_STORE32:
295 values[0] = State.regs[OP[1]];
296 values[1] = SEXT16 (OP[2]);
297 values[2] = State.regs[OP[0]];
298 num_values = 3;
299 break;
300
301 case OP_JUMP:
302 values[0] = SEXT22 (OP[0]);
303 values[1] = State.pc;
304 num_values = 2;
305 break;
306
307 case OP_IMM_REG_REG:
308 values[0] = SEXT16 (OP[0]) << size;
309 values[1] = State.regs[OP[1]];
310 num_values = 2;
311 break;
312
313 case OP_UIMM_REG_REG:
314 values[0] = (OP[0] & 0xffff) << size;
315 values[1] = State.regs[OP[1]];
316 num_values = 2;
317 break;
318
319 case OP_BIT:
320 num_values = 0;
321 break;
322
323 case OP_EX1:
324 values[0] = State.sregs[5];
325 num_values = 1;
326 break;
327
328 case OP_EX2:
329 num_values = 0;
330 break;
331
332 case OP_LDSR:
333 values[0] = State.regs[OP[0]];
334 num_values = 1;
335 break;
336
337 case OP_STSR:
338 values[0] = State.sregs[OP[1]];
339 num_values = 1;
340 }
341
342 for (i = 0; i < num_values; i++)
343 (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
344
345 while (i++ < 3)
346 (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
347 }
348 }
349
350 static void
351 trace_output (result)
352 enum op_types result;
353 {
354 if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
355 {
356 switch (result)
357 {
358 default:
359 case OP_UNKNOWN:
360 case OP_NONE:
361 case OP_TRAP:
362 case OP_REG:
363 case OP_REG_REG_CMP:
364 case OP_IMM_REG_CMP:
365 case OP_COND_BR:
366 case OP_STORE16:
367 case OP_STORE32:
368 case OP_BIT:
369 case OP_EX2:
370 break;
371
372 case OP_LOAD16:
373 case OP_STSR:
374 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
375 (unsigned long)State.regs[OP[0]]);
376 break;
377
378 case OP_REG_REG:
379 case OP_REG_REG_MOVE:
380 case OP_IMM_REG:
381 case OP_IMM_REG_MOVE:
382 case OP_LOAD32:
383 case OP_EX1:
384 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
385 (unsigned long)State.regs[OP[1]]);
386 break;
387
388 case OP_IMM_REG_REG:
389 case OP_UIMM_REG_REG:
390 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
391 (unsigned long)State.regs[OP[2]]);
392 break;
393
394 case OP_JUMP:
395 if (OP[1] != 0)
396 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
397 (unsigned long)State.regs[OP[1]]);
398 break;
399
400 case OP_LDSR:
401 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
402 (unsigned long)State.sregs[OP[1]]);
403 break;
404 }
405
406 (*v850_callback->printf_filtered) (v850_callback, "\n");
407 }
408 }
409
410 #else
411 #define trace_input(NAME, IN1, IN2, IN3)
412 #define trace_output(RESULT)
413 #endif
414
415 \f
416 /* sld.b */
417 void
418 OP_300 ()
419 {
420 unsigned int op2;
421 int result, temp;
422
423 trace_input ("sld.b", OP_LOAD16, 1);
424 temp = OP[1];
425 temp = SEXT7 (temp);
426 op2 = temp;
427 result = get_byte (State.mem + State.regs[30] + op2);
428 State.regs[OP[0]] = SEXT8 (result);
429 trace_output (OP_LOAD16);
430 }
431
432 /* sld.h */
433 void
434 OP_400 ()
435 {
436 unsigned int op2;
437 int result, temp;
438
439 trace_input ("sld.h", OP_LOAD16, 2);
440 temp = OP[1];
441 temp = SEXT7 (temp);
442 op2 = temp << 1;
443 result = get_half (State.mem + State.regs[30] + op2);
444 State.regs[OP[0]] = SEXT16 (result);
445 trace_output (OP_LOAD16);
446 }
447
448 /* sld.w */
449 void
450 OP_500 ()
451 {
452 unsigned int op2;
453 int result, temp;
454
455 trace_input ("sld.w", OP_LOAD16, 4);
456 temp = OP[1];
457 temp = SEXT7 (temp);
458 op2 = temp << 2;
459 result = get_word (State.mem + State.regs[30] + op2);
460 State.regs[OP[0]] = result;
461 trace_output (OP_LOAD16);
462 }
463
464 /* sst.b */
465 void
466 OP_380 ()
467 {
468 unsigned int op0, op1;
469 int temp;
470
471 trace_input ("sst.b", OP_STORE16, 1);
472 op0 = State.regs[OP[0]];
473 temp = OP[1];
474 temp = SEXT7 (temp);
475 op1 = temp;
476 put_byte (State.mem + State.regs[30] + op1, op0);
477 trace_output (OP_STORE16);
478 }
479
480 /* sst.h */
481 void
482 OP_480 ()
483 {
484 unsigned int op0, op1;
485 int temp;
486
487 trace_input ("sst.h", OP_STORE16, 2);
488 op0 = State.regs[OP[0]];
489 temp = OP[1];
490 temp = SEXT7 (temp);
491 op1 = temp << 1;
492 put_half (State.mem + State.regs[30] + op1, op0);
493 trace_output (OP_STORE16);
494 }
495
496 /* sst.w */
497 void
498 OP_501 ()
499 {
500 unsigned int op0, op1;
501 int temp;
502
503 trace_input ("sst.w", OP_STORE16, 4);
504 op0 = State.regs[OP[0]];
505 temp = OP[1];
506 temp = SEXT7 (temp);
507 op1 = temp << 2;
508 put_word (State.mem + State.regs[30] + op1, op0);
509 trace_output (OP_STORE16);
510 }
511
512 /* ld.b */
513 void
514 OP_700 ()
515 {
516 unsigned int op0, op2;
517 int result, temp;
518
519 trace_input ("ld.b", OP_LOAD32, 1);
520 op0 = State.regs[OP[0]];
521 temp = SEXT16 (OP[2]);
522 op2 = temp;
523 result = get_byte (State.mem + op0 + op2);
524 State.regs[OP[1]] = SEXT8 (result);
525 trace_output (OP_LOAD32);
526 }
527
528 /* ld.h */
529 void
530 OP_720 ()
531 {
532 unsigned int op0, op2;
533 int result, temp;
534
535 trace_input ("ld.h", OP_LOAD32, 2);
536 op0 = State.regs[OP[0]];
537 temp = SEXT16 (OP[2]);
538 temp &= ~0x1;
539 op2 = temp;
540 result = get_half (State.mem + op0 + op2);
541 State.regs[OP[1]] = SEXT16 (result);
542 trace_output (OP_LOAD32);
543 }
544
545 /* ld.w */
546 void
547 OP_10720 ()
548 {
549 unsigned int op0, op2;
550 int result, temp;
551
552 trace_input ("ld.w", OP_LOAD32, 4);
553 op0 = State.regs[OP[0]];
554 temp = SEXT16 (OP[2]);
555 temp &= ~0x1;
556 op2 = temp;
557 result = get_word (State.mem + op0 + op2);
558 State.regs[OP[1]] = result;
559 trace_output (OP_LOAD32);
560 }
561
562 /* st.b */
563 void
564 OP_740 ()
565 {
566 unsigned int op0, op1, op2;
567 int temp;
568
569 trace_input ("st.b", OP_STORE32, 1);
570 op0 = State.regs[OP[0]];
571 op1 = State.regs[OP[1]];
572 temp = SEXT16 (OP[2]);
573 op2 = temp;
574 put_byte (State.mem + op0 + op2, op1);
575 trace_output (OP_STORE32);
576 }
577
578 /* st.h */
579 void
580 OP_760 ()
581 {
582 unsigned int op0, op1, op2;
583 int temp;
584
585 trace_input ("st.h", OP_STORE32, 2);
586 op0 = State.regs[OP[0]];
587 op1 = State.regs[OP[1]];
588 temp = SEXT16 (OP[2] & ~0x1);
589 op2 = temp;
590 put_half (State.mem + op0 + op2, op1);
591 trace_output (OP_STORE32);
592 }
593
594 /* st.w */
595 void
596 OP_10760 ()
597 {
598 unsigned int op0, op1, op2;
599 int temp;
600
601 trace_input ("st.w", OP_STORE32, 4);
602 op0 = State.regs[OP[0]];
603 op1 = State.regs[OP[1]];
604 temp = SEXT16 (OP[2] & ~0x1);
605 op2 = temp;
606 put_word (State.mem + op0 + op2, op1);
607 trace_output (OP_STORE32);
608 }
609
610 /* bv disp9 */
611 void
612 OP_580 ()
613 {
614 unsigned int psw;
615 int op0;
616
617 trace_input ("bv", OP_COND_BR, 0);
618 op0 = SEXT9 (OP[0]);
619 psw = State.sregs[5];
620
621 if ((psw & PSW_OV) != 0)
622 State.pc += op0;
623 else
624 State.pc += 2;
625 trace_output (OP_COND_BR);
626 }
627
628 /* bl disp9 */
629 void
630 OP_581 ()
631 {
632 unsigned int psw;
633 int op0;
634
635 trace_input ("bl", OP_COND_BR, 0);
636 op0 = SEXT9 (OP[0]);
637 psw = State.sregs[5];
638
639 if ((psw & PSW_CY) != 0)
640 State.pc += op0;
641 else
642 State.pc += 2;
643 trace_output (OP_COND_BR);
644 }
645
646 /* be disp9 */
647 void
648 OP_582 ()
649 {
650 unsigned int psw;
651 int op0;
652
653 trace_input ("be", OP_COND_BR, 0);
654 op0 = SEXT9 (OP[0]);
655 psw = State.sregs[5];
656
657 if ((psw & PSW_Z) != 0)
658 State.pc += op0;
659 else
660 State.pc += 2;
661 trace_output (OP_COND_BR);
662 }
663
664 /* bnh disp 9*/
665 void
666 OP_583 ()
667 {
668 unsigned int psw;
669 int op0;
670
671 trace_input ("bnh", OP_COND_BR, 0);
672 op0 = SEXT9 (OP[0]);
673 psw = State.sregs[5];
674
675 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
676 State.pc += op0;
677 else
678 State.pc += 2;
679 trace_output (OP_COND_BR);
680 }
681
682 /* bn disp9 */
683 void
684 OP_584 ()
685 {
686 unsigned int psw;
687 int op0;
688
689 trace_input ("bn", OP_COND_BR, 0);
690 op0 = SEXT9 (OP[0]);
691 psw = State.sregs[5];
692
693 if ((psw & PSW_S) != 0)
694 State.pc += op0;
695 else
696 State.pc += 2;
697 trace_output (OP_COND_BR);
698 }
699
700 /* br disp9 */
701 void
702 OP_585 ()
703 {
704 unsigned int psw;
705 int op0;
706
707 trace_input ("br", OP_COND_BR, 0);
708 op0 = SEXT9 (OP[0]);
709 State.pc += op0;
710 trace_output (OP_COND_BR);
711 }
712
713 /* blt disp9 */
714 void
715 OP_586 ()
716 {
717 unsigned int psw;
718 int op0;
719
720 trace_input ("blt", OP_COND_BR, 0);
721 op0 = SEXT9 (OP[0]);
722 psw = State.sregs[5];
723
724 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
725 State.pc += op0;
726 else
727 State.pc += 2;
728 trace_output (OP_COND_BR);
729 }
730
731 /* ble disp9 */
732 void
733 OP_587 ()
734 {
735 unsigned int psw;
736 int op0;
737
738 trace_input ("ble", OP_COND_BR, 0);
739 op0 = SEXT9 (OP[0]);
740 psw = State.sregs[5];
741
742 if ((((psw & PSW_Z) != 0)
743 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
744 State.pc += op0;
745 else
746 State.pc += 2;
747 trace_output (OP_COND_BR);
748 }
749
750 /* bnv disp9 */
751 void
752 OP_588 ()
753 {
754 unsigned int psw;
755 int op0;
756
757 trace_input ("bnv", OP_COND_BR, 0);
758 op0 = SEXT9 (OP[0]);
759 psw = State.sregs[5];
760
761 if ((psw & PSW_OV) == 0)
762 State.pc += op0;
763 else
764 State.pc += 2;
765 trace_output (OP_COND_BR);
766 }
767
768 /* bnl disp9 */
769 void
770 OP_589 ()
771 {
772 unsigned int psw;
773 int op0;
774
775 trace_input ("bnl", OP_COND_BR, 0);
776 op0 = SEXT9 (OP[0]);
777 psw = State.sregs[5];
778
779 if ((psw & PSW_CY) == 0)
780 State.pc += op0;
781 else
782 State.pc += 2;
783 trace_output (OP_COND_BR);
784 }
785
786 /* bne disp9 */
787 void
788 OP_58A ()
789 {
790 unsigned int psw;
791 int op0;
792
793 trace_input ("bne", OP_COND_BR, 0);
794 op0 = SEXT9 (OP[0]);
795 psw = State.sregs[5];
796
797 if ((psw & PSW_Z) == 0)
798 State.pc += op0;
799 else
800 State.pc += 2;
801 trace_output (OP_COND_BR);
802 }
803
804 /* bh disp9 */
805 void
806 OP_58B ()
807 {
808 unsigned int psw;
809 int op0;
810
811 trace_input ("bh", OP_COND_BR, 0);
812 op0 = SEXT9 (OP[0]);
813 psw = State.sregs[5];
814
815 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
816 State.pc += op0;
817 else
818 State.pc += 2;
819 trace_output (OP_COND_BR);
820 }
821
822 /* bp disp9 */
823 void
824 OP_58C ()
825 {
826 unsigned int psw;
827 int op0;
828
829 trace_input ("bp", OP_COND_BR, 0);
830 op0 = SEXT9 (OP[0]);
831 psw = State.sregs[5];
832
833 if ((psw & PSW_S) == 0)
834 State.pc += op0;
835 else
836 State.pc += 2;
837 trace_output (OP_COND_BR);
838 }
839
840 /* bsa disp9 */
841 void
842 OP_58D ()
843 {
844 unsigned int psw;
845 int op0;
846
847 trace_input ("bsa", OP_COND_BR, 0);
848 op0 = SEXT9 (OP[0]);
849 psw = State.sregs[5];
850
851 if ((psw & PSW_SAT) != 0)
852 State.pc += op0;
853 else
854 State.pc += 2;
855 trace_output (OP_COND_BR);
856 }
857
858 /* bge disp9 */
859 void
860 OP_58E ()
861 {
862 unsigned int psw;
863 int op0;
864
865 trace_input ("bge", OP_COND_BR, 0);
866 op0 = SEXT9 (OP[0]);
867 psw = State.sregs[5];
868
869 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
870 State.pc += op0;
871 else
872 State.pc += 2;
873 trace_output (OP_COND_BR);
874 }
875
876 /* bgt disp9 */
877 void
878 OP_58F ()
879 {
880 unsigned int psw;
881 int op0;
882
883 trace_input ("bgt", OP_COND_BR, 0);
884 op0 = SEXT9 (OP[0]);
885 psw = State.sregs[5];
886
887 if ((((psw & PSW_Z) != 0)
888 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
889 State.pc += op0;
890 else
891 State.pc += 2;
892 trace_output (OP_COND_BR);
893 }
894
895 /* jmp [reg1] */
896 void
897 OP_60 ()
898 {
899 /* interp.c will bump this by +2, so correct for it here. */
900 trace_input ("jmp", OP_REG, 0);
901 State.pc = State.regs[OP[0]] - 2;
902 trace_output (OP_REG);
903 }
904
905 /* jarl disp22, reg */
906 void
907 OP_780 ()
908 {
909 unsigned int op0, opc;
910 int temp;
911
912 trace_input ("jarl", OP_JUMP, 0);
913 temp = SEXT22 (OP[0]);
914 op0 = temp;
915 opc = State.pc;
916
917 State.pc += temp;
918
919 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
920 if (OP[1] != 0)
921 State.regs[OP[1]] = opc + 4;
922 trace_output (OP_JUMP);
923 }
924
925 /* add reg, reg */
926 void
927 OP_1C0 ()
928 {
929 unsigned int op0, op1, result, z, s, cy, ov;
930
931 trace_input ("add", OP_REG_REG, 0);
932 /* Compute the result. */
933 op0 = State.regs[OP[0]];
934 op1 = State.regs[OP[1]];
935 result = op0 + op1;
936
937 /* Compute the condition codes. */
938 z = (result == 0);
939 s = (result & 0x80000000);
940 cy = (result < op0 || result < op1);
941 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
942 && (op0 & 0x80000000) != (result & 0x80000000));
943
944 /* Store the result and condition codes. */
945 State.regs[OP[1]] = result;
946 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
947 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
948 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
949 trace_output (OP_REG_REG);
950 }
951
952 /* add sign_extend(imm5), reg */
953 void
954 OP_240 ()
955 {
956 unsigned int op0, op1, result, z, s, cy, ov;
957 int temp;
958
959 trace_input ("add", OP_IMM_REG, 0);
960
961 /* Compute the result. */
962 temp = SEXT5 (OP[0]);
963 op0 = temp;
964 op1 = State.regs[OP[1]];
965 result = op0 + op1;
966
967 /* Compute the condition codes. */
968 z = (result == 0);
969 s = (result & 0x80000000);
970 cy = (result < op0 || result < op1);
971 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
972 && (op0 & 0x80000000) != (result & 0x80000000));
973
974 /* Store the result and condition codes. */
975 State.regs[OP[1]] = result;
976 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
977 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
978 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
979 trace_output (OP_IMM_REG);
980 }
981
982 /* addi sign_extend(imm16), reg, reg */
983 void
984 OP_600 ()
985 {
986 unsigned int op0, op1, result, z, s, cy, ov;
987 int temp;
988
989 trace_input ("addi", OP_IMM_REG_REG, 0);
990
991 /* Compute the result. */
992 temp = SEXT16 (OP[0]);
993 op0 = temp;
994 op1 = State.regs[OP[1]];
995 result = op0 + op1;
996
997 /* Compute the condition codes. */
998 z = (result == 0);
999 s = (result & 0x80000000);
1000 cy = (result < op0 || result < op1);
1001 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1002 && (op0 & 0x80000000) != (result & 0x80000000));
1003
1004 /* Store the result and condition codes. */
1005 State.regs[OP[2]] = result;
1006 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1007 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1008 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1009 trace_output (OP_IMM_REG_REG);
1010 }
1011
1012 /* sub reg1, reg2 */
1013 void
1014 OP_1A0 ()
1015 {
1016 unsigned int op0, op1, result, z, s, cy, ov;
1017
1018 trace_input ("sub", OP_REG_REG, 0);
1019 /* Compute the result. */
1020 op0 = State.regs[OP[0]];
1021 op1 = State.regs[OP[1]];
1022 result = op1 - op0;
1023
1024 /* Compute the condition codes. */
1025 z = (result == 0);
1026 s = (result & 0x80000000);
1027 cy = (op1 < op0);
1028 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1029 && (op1 & 0x80000000) != (result & 0x80000000));
1030
1031 /* Store the result and condition codes. */
1032 State.regs[OP[1]] = result;
1033 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1034 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1035 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1036 trace_output (OP_REG_REG);
1037 }
1038
1039 /* subr reg1, reg2 */
1040 void
1041 OP_180 ()
1042 {
1043 unsigned int op0, op1, result, z, s, cy, ov;
1044
1045 trace_input ("subr", OP_REG_REG, 0);
1046 /* Compute the result. */
1047 op0 = State.regs[OP[0]];
1048 op1 = State.regs[OP[1]];
1049 result = op0 - op1;
1050
1051 /* Compute the condition codes. */
1052 z = (result == 0);
1053 s = (result & 0x80000000);
1054 cy = (op0 < op1);
1055 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1056 && (op0 & 0x80000000) != (result & 0x80000000));
1057
1058 /* Store the result and condition codes. */
1059 State.regs[OP[1]] = result;
1060 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1061 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1062 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1063 trace_output (OP_REG_REG);
1064 }
1065
1066 /* mulh reg1, reg2 */
1067 void
1068 OP_E0 ()
1069 {
1070 trace_input ("mulh", OP_REG_REG, 0);
1071 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
1072 * (State.regs[OP[0]] & 0xffff));
1073 trace_output (OP_REG_REG);
1074 }
1075
1076 /* mulh sign_extend(imm5), reg2
1077
1078 Condition codes */
1079 void
1080 OP_2E0 ()
1081 {
1082 int value = SEXT5 (OP[0]);
1083
1084 trace_input ("mulh", OP_IMM_REG, 0);
1085 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
1086 trace_output (OP_IMM_REG);
1087 }
1088
1089 /* mulhi imm16, reg1, reg2 */
1090 void
1091 OP_6E0 ()
1092 {
1093 int value = OP[0] & 0xffff;
1094
1095 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1096 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
1097 trace_output (OP_IMM_REG_REG);
1098 }
1099
1100 /* divh reg1, reg2 */
1101 void
1102 OP_40 ()
1103 {
1104 unsigned int op0, op1, result, ov, s, z;
1105 int temp;
1106
1107 trace_input ("divh", OP_REG_REG, 0);
1108
1109 /* Compute the result. */
1110 temp = SEXT16 (State.regs[OP[0]]);
1111 op0 = temp;
1112 op1 = State.regs[OP[1]];
1113
1114 if (op0 == 0xffffffff && op1 == 0x80000000)
1115 {
1116 result = 0x80000000;
1117 ov = 1;
1118 }
1119 else if (op0 != 0)
1120 {
1121 result = op1 / op0;
1122 ov = 0;
1123 }
1124 else
1125 {
1126 result = 0x0;
1127 ov = 1;
1128 }
1129
1130 /* Compute the condition codes. */
1131 z = (result == 0);
1132 s = (result & 0x80000000);
1133
1134 /* Store the result and condition codes. */
1135 State.regs[OP[1]] = result;
1136 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1137 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1138 | (ov ? PSW_OV : 0));
1139 trace_output (OP_REG_REG);
1140 }
1141
1142 /* cmp reg, reg */
1143 void
1144 OP_1E0 ()
1145 {
1146 unsigned int op0, op1, result, z, s, cy, ov;
1147
1148 trace_input ("cmp", OP_REG_REG_CMP, 0);
1149 /* Compute the result. */
1150 op0 = State.regs[OP[0]];
1151 op1 = State.regs[OP[1]];
1152 result = op1 - op0;
1153
1154 /* Compute the condition codes. */
1155 z = (result == 0);
1156 s = (result & 0x80000000);
1157 cy = (op1 < op0);
1158 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1159 && (op1 & 0x80000000) != (result & 0x80000000));
1160
1161 /* Set condition codes. */
1162 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1163 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1164 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1165 trace_output (OP_REG_REG_CMP);
1166 }
1167
1168 /* cmp sign_extend(imm5), reg */
1169 void
1170 OP_260 ()
1171 {
1172 unsigned int op0, op1, result, z, s, cy, ov;
1173 int temp;
1174
1175 /* Compute the result. */
1176 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1177 temp = SEXT5 (OP[0]);
1178 op0 = temp;
1179 op1 = State.regs[OP[1]];
1180 result = op1 - op0;
1181
1182 /* Compute the condition codes. */
1183 z = (result == 0);
1184 s = (result & 0x80000000);
1185 cy = (op1 < op0);
1186 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1187 && (op1 & 0x80000000) != (result & 0x80000000));
1188
1189 /* Set condition codes. */
1190 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1191 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1192 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1193 trace_output (OP_IMM_REG_CMP);
1194 }
1195
1196 /* setf cccc,reg2 */
1197 void
1198 OP_7E0 ()
1199 {
1200 /* Hack alert. We turn off a bit in op0 since we really only
1201 wanted 4 bits. */
1202 unsigned int op0, psw, result = 0;
1203
1204 trace_input ("setf", OP_EX1, 0);
1205 op0 = OP[0] & 0xf;
1206 psw = State.sregs[5];
1207
1208 switch (op0)
1209 {
1210 case 0x0:
1211 result = ((psw & PSW_OV) != 0);
1212 break;
1213 case 0x1:
1214 result = ((psw & PSW_CY) != 0);
1215 break;
1216 case 0x2:
1217 result = ((psw & PSW_Z) != 0);
1218 break;
1219 case 0x3:
1220 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
1221 break;
1222 case 0x4:
1223 result = ((psw & PSW_S) != 0);
1224 break;
1225 case 0x5:
1226 result = 1;
1227 break;
1228 case 0x6:
1229 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
1230 break;
1231 case 0x7:
1232 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
1233 || ((psw & PSW_Z) != 0)) != 0);
1234 break;
1235 case 0x8:
1236 result = ((psw & PSW_OV) == 0);
1237 break;
1238 case 0x9:
1239 result = ((psw & PSW_CY) == 0);
1240 break;
1241 case 0xa:
1242 result = ((psw & PSW_Z) == 0);
1243 break;
1244 case 0xb:
1245 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
1246 break;
1247 case 0xc:
1248 result = ((psw & PSW_S) == 0);
1249 break;
1250 case 0xd:
1251 result = ((psw & PSW_SAT) != 0);
1252 break;
1253 case 0xe:
1254 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
1255 break;
1256 case 0xf:
1257 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
1258 || ((psw & PSW_Z) != 0)) == 0);
1259 break;
1260 }
1261
1262 State.regs[OP[1]] = result;
1263 trace_output (OP_EX1);
1264 }
1265
1266 /* satadd reg,reg */
1267 void
1268 OP_C0 ()
1269 {
1270 unsigned int op0, op1, result, z, s, cy, ov, sat;
1271
1272 trace_input ("satadd", OP_REG_REG, 0);
1273 /* Compute the result. */
1274 op0 = State.regs[OP[0]];
1275 op1 = State.regs[OP[1]];
1276 result = op0 + op1;
1277
1278 /* Compute the condition codes. */
1279 z = (result == 0);
1280 s = (result & 0x80000000);
1281 cy = (result < op0 || result < op1);
1282 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1283 && (op0 & 0x80000000) != (result & 0x80000000));
1284 sat = ov;
1285
1286 /* Store the result and condition codes. */
1287 State.regs[OP[1]] = result;
1288 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1289 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1290 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1291 | (sat ? PSW_SAT : 0));
1292
1293 /* Handle saturated results. */
1294 if (sat && s)
1295 State.regs[OP[1]] = 0x80000000;
1296 else if (sat)
1297 State.regs[OP[1]] = 0x7fffffff;
1298 trace_output (OP_REG_REG);
1299 }
1300
1301 /* satadd sign_extend(imm5), reg */
1302 void
1303 OP_220 ()
1304 {
1305 unsigned int op0, op1, result, z, s, cy, ov, sat;
1306
1307 int temp;
1308
1309 trace_input ("satadd", OP_IMM_REG, 0);
1310
1311 /* Compute the result. */
1312 temp = SEXT5 (OP[0]);
1313 op0 = temp;
1314 op1 = State.regs[OP[1]];
1315 result = op0 + op1;
1316
1317 /* Compute the condition codes. */
1318 z = (result == 0);
1319 s = (result & 0x80000000);
1320 cy = (result < op0 || result < op1);
1321 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1322 && (op0 & 0x80000000) != (result & 0x80000000));
1323 sat = ov;
1324
1325 /* Store the result and condition codes. */
1326 State.regs[OP[1]] = result;
1327 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1328 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1329 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1330 | (sat ? PSW_SAT : 0));
1331
1332 /* Handle saturated results. */
1333 if (sat && s)
1334 State.regs[OP[1]] = 0x80000000;
1335 else if (sat)
1336 State.regs[OP[1]] = 0x7fffffff;
1337 trace_output (OP_IMM_REG);
1338 }
1339
1340 /* satsub reg1, reg2 */
1341 void
1342 OP_A0 ()
1343 {
1344 unsigned int op0, op1, result, z, s, cy, ov, sat;
1345
1346 trace_input ("satsub", OP_REG_REG, 0);
1347
1348 /* Compute the result. */
1349 op0 = State.regs[OP[0]];
1350 op1 = State.regs[OP[1]];
1351 result = op1 - op0;
1352
1353 /* Compute the condition codes. */
1354 z = (result == 0);
1355 s = (result & 0x80000000);
1356 cy = (op1 < op0);
1357 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1358 && (op1 & 0x80000000) != (result & 0x80000000));
1359 sat = ov;
1360
1361 /* Store the result and condition codes. */
1362 State.regs[OP[1]] = result;
1363 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1364 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1365 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1366 | (sat ? PSW_SAT : 0));
1367
1368 /* Handle saturated results. */
1369 if (sat && s)
1370 State.regs[OP[1]] = 0x80000000;
1371 else if (sat)
1372 State.regs[OP[1]] = 0x7fffffff;
1373 trace_output (OP_REG_REG);
1374 }
1375
1376 /* satsubi sign_extend(imm16), reg */
1377 void
1378 OP_660 ()
1379 {
1380 unsigned int op0, op1, result, z, s, cy, ov, sat;
1381 int temp;
1382
1383 trace_input ("satsubi", OP_IMM_REG, 0);
1384
1385 /* Compute the result. */
1386 temp = SEXT16 (OP[0]);
1387 op0 = temp;
1388 op1 = State.regs[OP[1]];
1389 result = op1 - op0;
1390
1391 /* Compute the condition codes. */
1392 z = (result == 0);
1393 s = (result & 0x80000000);
1394 cy = (op1 < op0);
1395 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1396 && (op1 & 0x80000000) != (result & 0x80000000));
1397 sat = ov;
1398
1399 /* Store the result and condition codes. */
1400 State.regs[OP[1]] = result;
1401 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1402 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1403 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1404 | (sat ? PSW_SAT : 0));
1405
1406 /* Handle saturated results. */
1407 if (sat && s)
1408 State.regs[OP[1]] = 0x80000000;
1409 else if (sat)
1410 State.regs[OP[1]] = 0x7fffffff;
1411 trace_output (OP_IMM_REG);
1412 }
1413
1414 /* satsubr reg,reg */
1415 void
1416 OP_80 ()
1417 {
1418 unsigned int op0, op1, result, z, s, cy, ov, sat;
1419
1420 trace_input ("satsubr", OP_REG_REG, 0);
1421
1422 /* Compute the result. */
1423 op0 = State.regs[OP[0]];
1424 op1 = State.regs[OP[1]];
1425 result = op0 - op1;
1426
1427 /* Compute the condition codes. */
1428 z = (result == 0);
1429 s = (result & 0x80000000);
1430 cy = (result < op0);
1431 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1432 && (op1 & 0x80000000) != (result & 0x80000000));
1433 sat = ov;
1434
1435 /* Store the result and condition codes. */
1436 State.regs[OP[1]] = result;
1437 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1438 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1439 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1440 | (sat ? PSW_SAT : 0));
1441
1442 /* Handle saturated results. */
1443 if (sat && s)
1444 State.regs[OP[1]] = 0x80000000;
1445 else if (sat)
1446 State.regs[OP[1]] = 0x7fffffff;
1447 trace_output (OP_REG_REG);
1448 }
1449
1450 /* tst reg,reg */
1451 void
1452 OP_160 ()
1453 {
1454 unsigned int op0, op1, result, z, s;
1455
1456 trace_input ("tst", OP_REG_REG_CMP, 0);
1457
1458 /* Compute the result. */
1459 op0 = State.regs[OP[0]];
1460 op1 = State.regs[OP[1]];
1461 result = op0 & op1;
1462
1463 /* Compute the condition codes. */
1464 z = (result == 0);
1465 s = (result & 0x80000000);
1466
1467 /* Store the condition codes. */
1468 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1469 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1470 trace_output (OP_REG_REG_CMP);
1471 }
1472
1473 /* mov reg, reg */
1474 void
1475 OP_0 ()
1476 {
1477 trace_input ("mov", OP_REG_REG_MOVE, 0);
1478 State.regs[OP[1]] = State.regs[OP[0]];
1479 trace_output (OP_REG_REG_MOVE);
1480 }
1481
1482 /* mov sign_extend(imm5), reg */
1483 void
1484 OP_200 ()
1485 {
1486 int value = SEXT5 (OP[0]);
1487
1488 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1489 State.regs[OP[1]] = value;
1490 trace_output (OP_IMM_REG_MOVE);
1491 }
1492
1493 /* movea sign_extend(imm16), reg, reg */
1494
1495 void
1496 OP_620 ()
1497 {
1498 int value = SEXT16 (OP[0]);
1499
1500 trace_input ("movea", OP_IMM_REG_REG, 0);
1501 State.regs[OP[2]] = State.regs[OP[1]] + value;
1502 trace_output (OP_IMM_REG_REG);
1503 }
1504
1505 /* movhi imm16, reg, reg */
1506 void
1507 OP_640 ()
1508 {
1509 uint32 value = (OP[0] & 0xffff) << 16;
1510
1511 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1512 State.regs[OP[2]] = State.regs[OP[1]] + value;
1513 trace_output (OP_UIMM_REG_REG);
1514 }
1515
1516 /* sar zero_extend(imm5),reg1 */
1517 void
1518 OP_2A0 ()
1519 {
1520 unsigned int op0, op1, result, z, s, cy;
1521
1522 trace_input ("sar", OP_IMM_REG, 0);
1523 op0 = OP[0] & 0x1f;
1524 op1 = State.regs[OP[1]];
1525 result = (signed)op1 >> op0;
1526
1527 /* Compute the condition codes. */
1528 z = (result == 0);
1529 s = (result & 0x80000000);
1530 cy = (op1 & (1 << (op0 - 1)));
1531
1532 /* Store the result and condition codes. */
1533 State.regs[OP[1]] = result;
1534 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1535 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1536 | (cy ? PSW_CY : 0));
1537 trace_output (OP_IMM_REG);
1538 }
1539
1540 /* sar reg1, reg2 */
1541 void
1542 OP_A007E0 ()
1543 {
1544 unsigned int op0, op1, result, z, s, cy;
1545
1546 trace_input ("sar", OP_REG_REG, 0);
1547 op0 = State.regs[OP[0]] & 0x1f;
1548 op1 = State.regs[OP[1]];
1549 result = (signed)op1 >> op0;
1550
1551 /* Compute the condition codes. */
1552 z = (result == 0);
1553 s = (result & 0x80000000);
1554 cy = (op1 & (1 << (op0 - 1)));
1555
1556 /* Store the result and condition codes. */
1557 State.regs[OP[1]] = result;
1558 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1559 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1560 | (cy ? PSW_CY : 0));
1561 trace_output (OP_REG_REG);
1562 }
1563
1564 /* shl zero_extend(imm5),reg1 */
1565 void
1566 OP_2C0 ()
1567 {
1568 unsigned int op0, op1, result, z, s, cy;
1569
1570 trace_input ("shl", OP_IMM_REG, 0);
1571 op0 = OP[0] & 0x1f;
1572 op1 = State.regs[OP[1]];
1573 result = op1 << op0;
1574
1575 /* Compute the condition codes. */
1576 z = (result == 0);
1577 s = (result & 0x80000000);
1578 cy = (op1 & (1 << (32 - op0)));
1579
1580 /* Store the result and condition codes. */
1581 State.regs[OP[1]] = result;
1582 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1583 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1584 | (cy ? PSW_CY : 0));
1585 trace_output (OP_IMM_REG);
1586 }
1587
1588 /* shl reg1, reg2 */
1589 void
1590 OP_C007E0 ()
1591 {
1592 unsigned int op0, op1, result, z, s, cy;
1593
1594 trace_input ("shl", OP_REG_REG, 0);
1595 op0 = State.regs[OP[0]] & 0x1f;
1596 op1 = State.regs[OP[1]];
1597 result = op1 << op0;
1598
1599 /* Compute the condition codes. */
1600 z = (result == 0);
1601 s = (result & 0x80000000);
1602 cy = (op1 & (1 << (32 - op0)));
1603
1604 /* Store the result and condition codes. */
1605 State.regs[OP[1]] = result;
1606 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1607 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1608 | (cy ? PSW_CY : 0));
1609 trace_output (OP_REG_REG);
1610 }
1611
1612 /* shr zero_extend(imm5),reg1 */
1613 void
1614 OP_280 ()
1615 {
1616 unsigned int op0, op1, result, z, s, cy;
1617
1618 trace_input ("shr", OP_IMM_REG, 0);
1619 op0 = OP[0] & 0x1f;
1620 op1 = State.regs[OP[1]];
1621 result = op1 >> op0;
1622
1623 /* Compute the condition codes. */
1624 z = (result == 0);
1625 s = (result & 0x80000000);
1626 cy = (op1 & (1 << (op0 - 1)));
1627
1628 /* Store the result and condition codes. */
1629 State.regs[OP[1]] = result;
1630 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1631 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1632 | (cy ? PSW_CY : 0));
1633 trace_output (OP_IMM_REG);
1634 }
1635
1636 /* shr reg1, reg2 */
1637 void
1638 OP_8007E0 ()
1639 {
1640 unsigned int op0, op1, result, z, s, cy;
1641
1642 trace_input ("shr", OP_REG_REG, 0);
1643 op0 = State.regs[OP[0]] & 0x1f;
1644 op1 = State.regs[OP[1]];
1645 result = op1 >> op0;
1646
1647 /* Compute the condition codes. */
1648 z = (result == 0);
1649 s = (result & 0x80000000);
1650 cy = (op1 & (1 << (op0 - 1)));
1651
1652 /* Store the result and condition codes. */
1653 State.regs[OP[1]] = result;
1654 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1655 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1656 | (cy ? PSW_CY : 0));
1657 trace_output (OP_REG_REG);
1658 }
1659
1660 /* or reg, reg */
1661 void
1662 OP_100 ()
1663 {
1664 unsigned int op0, op1, result, z, s;
1665
1666 trace_input ("or", OP_REG_REG, 0);
1667
1668 /* Compute the result. */
1669 op0 = State.regs[OP[0]];
1670 op1 = State.regs[OP[1]];
1671 result = op0 | op1;
1672
1673 /* Compute the condition codes. */
1674 z = (result == 0);
1675 s = (result & 0x80000000);
1676
1677 /* Store the result and condition codes. */
1678 State.regs[OP[1]] = result;
1679 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1680 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1681 trace_output (OP_REG_REG);
1682 }
1683
1684 /* ori zero_extend(imm16), reg, reg */
1685 void
1686 OP_680 ()
1687 {
1688 unsigned int op0, op1, result, z, s;
1689
1690 trace_input ("ori", OP_UIMM_REG_REG, 0);
1691 op0 = OP[0] & 0xffff;
1692 op1 = State.regs[OP[1]];
1693 result = op0 | op1;
1694
1695 /* Compute the condition codes. */
1696 z = (result == 0);
1697 s = (result & 0x80000000);
1698
1699 /* Store the result and condition codes. */
1700 State.regs[OP[2]] = result;
1701 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1702 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1703 trace_output (OP_UIMM_REG_REG);
1704 }
1705
1706 /* and reg, reg */
1707 void
1708 OP_140 ()
1709 {
1710 unsigned int op0, op1, result, z, s;
1711
1712 trace_input ("and", OP_REG_REG, 0);
1713
1714 /* Compute the result. */
1715 op0 = State.regs[OP[0]];
1716 op1 = State.regs[OP[1]];
1717 result = op0 & op1;
1718
1719 /* Compute the condition codes. */
1720 z = (result == 0);
1721 s = (result & 0x80000000);
1722
1723 /* Store the result and condition codes. */
1724 State.regs[OP[1]] = result;
1725 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1726 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1727 trace_output (OP_REG_REG);
1728 }
1729
1730 /* andi zero_extend(imm16), reg, reg */
1731 void
1732 OP_6C0 ()
1733 {
1734 unsigned int op0, op1, result, z;
1735
1736 trace_input ("andi", OP_UIMM_REG_REG, 0);
1737 op0 = OP[0] & 0xffff;
1738 op1 = State.regs[OP[1]];
1739 result = op0 & op1;
1740
1741 /* Compute the condition codes. */
1742 z = (result == 0);
1743
1744 /* Store the result and condition codes. */
1745 State.regs[OP[2]] = result;
1746 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1747 State.sregs[5] |= (z ? PSW_Z : 0);
1748 trace_output (OP_UIMM_REG_REG);
1749 }
1750
1751 /* xor reg, reg */
1752 void
1753 OP_120 ()
1754 {
1755 unsigned int op0, op1, result, z, s;
1756
1757 trace_input ("xor", OP_REG_REG, 0);
1758
1759 /* Compute the result. */
1760 op0 = State.regs[OP[0]];
1761 op1 = State.regs[OP[1]];
1762 result = op0 ^ op1;
1763
1764 /* Compute the condition codes. */
1765 z = (result == 0);
1766 s = (result & 0x80000000);
1767
1768 /* Store the result and condition codes. */
1769 State.regs[OP[1]] = result;
1770 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1771 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1772 trace_output (OP_REG_REG);
1773 }
1774
1775 /* xori zero_extend(imm16), reg, reg */
1776 void
1777 OP_6A0 ()
1778 {
1779 unsigned int op0, op1, result, z, s;
1780
1781 trace_input ("xori", OP_UIMM_REG_REG, 0);
1782 op0 = OP[0] & 0xffff;
1783 op1 = State.regs[OP[1]];
1784 result = op0 ^ op1;
1785
1786 /* Compute the condition codes. */
1787 z = (result == 0);
1788 s = (result & 0x80000000);
1789
1790 /* Store the result and condition codes. */
1791 State.regs[OP[2]] = result;
1792 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1793 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1794 trace_output (OP_UIMM_REG_REG);
1795 }
1796
1797 /* not reg1, reg2 */
1798 void
1799 OP_20 ()
1800 {
1801 unsigned int op0, result, z, s;
1802
1803 trace_input ("not", OP_REG_REG_MOVE, 0);
1804 /* Compute the result. */
1805 op0 = State.regs[OP[0]];
1806 result = ~op0;
1807
1808 /* Compute the condition codes. */
1809 z = (result == 0);
1810 s = (result & 0x80000000);
1811
1812 /* Store the result and condition codes. */
1813 State.regs[OP[1]] = result;
1814 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1815 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1816 trace_output (OP_REG_REG_MOVE);
1817 }
1818
1819 /* set1 */
1820 void
1821 OP_7C0 ()
1822 {
1823 unsigned int op0, op1, op2;
1824 int temp;
1825
1826 trace_input ("set1", OP_BIT, 0);
1827 op0 = State.regs[OP[0]];
1828 op1 = OP[1] & 0x7;
1829 temp = SEXT16 (OP[2]);
1830 op2 = temp;
1831 temp = get_byte (State.mem + op0 + op2);
1832 State.sregs[5] &= ~PSW_Z;
1833 if ((temp & (1 << op1)) == 0)
1834 State.sregs[5] |= PSW_Z;
1835 temp |= (1 << op1);
1836 put_byte (State.mem + op0 + op2, temp);
1837 trace_output (OP_BIT);
1838 }
1839
1840 /* not1 */
1841 void
1842 OP_47C0 ()
1843 {
1844 unsigned int op0, op1, op2;
1845 int temp;
1846
1847 trace_input ("not1", OP_BIT, 0);
1848 op0 = State.regs[OP[0]];
1849 op1 = OP[1] & 0x7;
1850 temp = SEXT16 (OP[2]);
1851 op2 = temp;
1852 temp = get_byte (State.mem + op0 + op2);
1853 State.sregs[5] &= ~PSW_Z;
1854 if ((temp & (1 << op1)) == 0)
1855 State.sregs[5] |= PSW_Z;
1856 temp ^= (1 << op1);
1857 put_byte (State.mem + op0 + op2, temp);
1858 trace_output (OP_BIT);
1859 }
1860
1861 /* clr1 */
1862 void
1863 OP_87C0 ()
1864 {
1865 unsigned int op0, op1, op2;
1866 int temp;
1867
1868 trace_input ("clr1", OP_BIT, 0);
1869 op0 = State.regs[OP[0]];
1870 op1 = OP[1] & 0x7;
1871 temp = SEXT16 (OP[2]);
1872 op2 = temp;
1873 temp = get_byte (State.mem + op0 + op2);
1874 State.sregs[5] &= ~PSW_Z;
1875 if ((temp & (1 << op1)) == 0)
1876 State.sregs[5] |= PSW_Z;
1877 temp &= ~(1 << op1);
1878 put_byte (State.mem + op0 + op2, temp);
1879 trace_output (OP_BIT);
1880 }
1881
1882 /* tst1 */
1883 void
1884 OP_C7C0 ()
1885 {
1886 unsigned int op0, op1, op2;
1887 int temp;
1888
1889 trace_input ("tst1", OP_BIT, 0);
1890 op0 = State.regs[OP[0]];
1891 op1 = OP[1] & 0x7;
1892 temp = SEXT16 (OP[2]);
1893 op2 = temp;
1894 temp = get_byte (State.mem + op0 + op2);
1895 State.sregs[5] &= ~PSW_Z;
1896 if ((temp & (1 << op1)) == 0)
1897 State.sregs[5] |= PSW_Z;
1898 trace_output (OP_BIT);
1899 }
1900
1901 /* di */
1902 void
1903 OP_16007E0 ()
1904 {
1905 trace_input ("di", OP_NONE, 0);
1906 State.sregs[5] |= PSW_ID;
1907 trace_output (OP_NONE);
1908 }
1909
1910 /* ei */
1911 void
1912 OP_16087E0 ()
1913 {
1914 trace_input ("ei", OP_NONE, 0);
1915 State.sregs[5] &= ~PSW_ID;
1916 trace_output (OP_NONE);
1917 }
1918
1919 /* halt, not supported */
1920 void
1921 OP_12007E0 ()
1922 {
1923 trace_input ("halt", OP_NONE, 0);
1924 State.exception = SIGQUIT;
1925 trace_output (OP_NONE);
1926 }
1927
1928 /* reti, not supported */
1929 void
1930 OP_14007E0 ()
1931 {
1932 trace_input ("reti", OP_NONE, 0);
1933 trace_output (OP_NONE);
1934 abort ();
1935 }
1936
1937 /* trap, not supportd */
1938 void
1939 OP_10007E0 ()
1940 {
1941 extern int errno;
1942
1943 trace_input ("trap", OP_TRAP, 0);
1944 trace_output (OP_TRAP);
1945
1946 /* Trap 0 is used for simulating low-level I/O */
1947
1948 if (OP[0] == 0)
1949 {
1950 int save_errno = errno;
1951 errno = 0;
1952
1953 /* Registers passed to trap 0 */
1954
1955 #define FUNC State.regs[6] /* function number, return value */
1956 #define PARM1 State.regs[7] /* optional parm 1 */
1957 #define PARM2 State.regs[8] /* optional parm 2 */
1958 #define PARM3 State.regs[9] /* optional parm 3 */
1959
1960 /* Registers set by trap 0 */
1961
1962 #define RETVAL State.regs[10] /* return value */
1963 #define RETERR State.regs[11] /* return error code */
1964
1965 /* Turn a pointer in a register into a pointer into real memory. */
1966
1967 #define MEMPTR(x) ((char *)((x) + State.mem))
1968
1969
1970 switch (FUNC)
1971 {
1972 #if !defined(__GO32__) && !defined(_WIN32)
1973 case SYS_fork:
1974 RETVAL = fork ();
1975 break;
1976 case SYS_execve:
1977 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
1978 (char **)MEMPTR (PARM3));
1979 break;
1980 case SYS_execv:
1981 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
1982 break;
1983 #if 0
1984 case SYS_pipe:
1985 {
1986 reg_t buf;
1987 int host_fd[2];
1988
1989 buf = PARM1;
1990 RETVAL = pipe (host_fd);
1991 SW (buf, host_fd[0]);
1992 buf += sizeof(uint16);
1993 SW (buf, host_fd[1]);
1994 }
1995 break;
1996
1997 case SYS_wait:
1998 {
1999 int status;
2000
2001 RETVAL = wait (&status);
2002 SW (PARM1, status);
2003 }
2004 break;
2005 #endif
2006 #endif
2007
2008 case SYS_read:
2009 RETVAL = v850_callback->read (v850_callback, PARM1, MEMPTR (PARM2),
2010 PARM3);
2011 break;
2012 case SYS_write:
2013 if (PARM1 == 1)
2014 RETVAL = (int)v850_callback->write_stdout (v850_callback,
2015 MEMPTR (PARM2), PARM3);
2016 else
2017 RETVAL = (int)v850_callback->write (v850_callback, PARM1,
2018 MEMPTR (PARM2), PARM3);
2019 break;
2020 case SYS_lseek:
2021 RETVAL = v850_callback->lseek (v850_callback, PARM1, PARM2, PARM3);
2022 break;
2023 case SYS_close:
2024 RETVAL = v850_callback->close (v850_callback, PARM1);
2025 break;
2026 case SYS_open:
2027 RETVAL = v850_callback->open (v850_callback, MEMPTR (PARM1), PARM2);
2028 break;
2029 case SYS_exit:
2030 /* EXIT - caller can look in PARM1 to work out the
2031 reason */
2032 if (PARM1 == 0xdead || PARM1 == 0x1)
2033 State.exception = SIGABRT;
2034 else
2035 State.exception = SIGQUIT;
2036 break;
2037
2038 #if 0
2039 case SYS_stat: /* added at hmsi */
2040 /* stat system call */
2041 {
2042 struct stat host_stat;
2043 reg_t buf;
2044
2045 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2046
2047 buf = PARM2;
2048
2049 /* The hard-coded offsets and sizes were determined by using
2050 * the D10V compiler on a test program that used struct stat.
2051 */
2052 SW (buf, host_stat.st_dev);
2053 SW (buf+2, host_stat.st_ino);
2054 SW (buf+4, host_stat.st_mode);
2055 SW (buf+6, host_stat.st_nlink);
2056 SW (buf+8, host_stat.st_uid);
2057 SW (buf+10, host_stat.st_gid);
2058 SW (buf+12, host_stat.st_rdev);
2059 SLW (buf+16, host_stat.st_size);
2060 SLW (buf+20, host_stat.st_atime);
2061 SLW (buf+28, host_stat.st_mtime);
2062 SLW (buf+36, host_stat.st_ctime);
2063 }
2064 #endif
2065 break;
2066
2067 case SYS_chown:
2068 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2069 break;
2070 case SYS_chmod:
2071 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2072 break;
2073 case SYS_utime:
2074 /* Cast the second argument to void *, to avoid type mismatch
2075 if a prototype is present. */
2076 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2077 break;
2078 default:
2079 abort ();
2080 }
2081 RETERR = errno;
2082 errno = save_errno;
2083 }
2084 else if (OP[0] == 1 )
2085 {
2086 char *fstr = State.regs[2] + State.mem;
2087 puts (fstr);
2088 }
2089 }
2090
2091 /* ldsr, reg,reg */
2092 void
2093 OP_2007E0 ()
2094 {
2095 unsigned int op0;
2096
2097 trace_input ("ldsr", OP_LDSR, 0);
2098 op0 = State.regs[OP[0]];
2099 State.sregs[OP[1]] = op0;
2100 trace_output (OP_LDSR);
2101 }
2102
2103 /* stsr, not supported */
2104 void
2105 OP_4007E0 ()
2106 {
2107 unsigned int op0;
2108
2109 trace_input ("stsr", OP_STSR, 0);
2110 op0 = State.sregs[OP[1]];
2111 State.regs[OP[0]] = op0;
2112 trace_output (OP_STSR);
2113 }