sim/v850/simops.c

   1 #include <signal.h>
   2 #include "v850_sim.h"
   3 #include "simops.h"
   4
   5 /* sld.b */
   6 void
   7 OP_300 ()
   8 {
   9   unsigned int op0, op1, op2;
  10   int result, temp;
  11
  12   temp = OP[1];
  13   temp = (temp << 25) >> 25;
  14   op2 = temp;
  15   result = get_byte (State.mem + State.regs[30] + op2);
  16   result = (result << 24) >> 24;
  17   State.regs[OP[0]] = result;
  18 }
  19
  20 /* sld.h */
  21 void
  22 OP_400 ()
  23 {
  24   unsigned int op0, op1, op2;
  25   int result, temp;
  26
  27   temp = OP[1];
  28   temp = (temp << 25) >> 25;
  29   op2 = temp << 1;
  30   result = get_half (State.mem + State.regs[30] + op2);
  31   result = (result << 16) >> 16;
  32   State.regs[OP[0]] = result;
  33 }
  34
  35 /* sld.w */
  36 void
  37 OP_500 ()
  38 {
  39   unsigned int op0, op1, op2;
  40   int result, temp;
  41
  42   temp = OP[1];
  43   temp = (temp << 25) >> 25;
  44   op2 = temp << 2;
  45   result = get_word (State.mem + State.regs[30] + op2);
  46   State.regs[OP[0]] = result;
  47 }
  48
  49 /* sst.b */
  50 void
  51 OP_380 ()
  52 {
  53   unsigned int op0, op1, op2;
  54   int result, temp;
  55
  56   op0 = State.regs[OP[0]];
  57   temp = OP[1];
  58   temp = (temp << 25) >> 25;
  59   op1 = temp;
  60   put_byte (State.mem + State.regs[30] + op1, op0);
  61 }
  62
  63 /* sst.h */
  64 void
  65 OP_480 ()
  66 {
  67   unsigned int op0, op1, op2;
  68   int result, temp;
  69
  70   op0 = State.regs[OP[0]];
  71   temp = OP[1];
  72   temp = (temp << 25) >> 25;
  73   op1 = temp << 1;
  74   put_half (State.mem + State.regs[30] + op1, op0);
  75 }
  76
  77 /* sst.w */
  78 void
  79 OP_501 ()
  80 {
  81   unsigned int op0, op1, op2;
  82   int result, temp;
  83
  84   op0 = State.regs[OP[0]];
  85   temp = OP[1];
  86   temp = (temp << 25) >> 25;
  87   op1 = temp << 2;
  88   put_word (State.mem + State.regs[30] + op1, op0);
  89 }
  90
  91 /* ld.b */
  92 void
  93 OP_700 ()
  94 {
  95   unsigned int op0, op1, op2;
  96   int result, temp;
  97
  98   op0 = State.regs[OP[0]];
  99   temp = OP[2];
 100   temp = (temp << 16) >> 16;
 101   op2 = temp;
 102   result = get_byte (State.mem + op0 + op2);
 103   result = (result << 24) >> 24;
 104   State.regs[OP[1]] = result;
 105 }
 106
 107 /* ld.h */
 108 void
 109 OP_720 ()
 110 {
 111   unsigned int op0, op1, op2;
 112   int result, temp;
 113
 114   op0 = State.regs[OP[0]];
 115   temp = OP[2];
 116   temp = (temp << 16) >> 16;
 117   temp &= ~0x1;
 118   op2 = temp;
 119   result = get_half (State.mem + op0 + op2);
 120   result = (result << 16) >> 16;
 121   State.regs[OP[1]] = result;
 122 }
 123
 124 /* ld.w */
 125 void
 126 OP_10720 ()
 127 {
 128   unsigned int op0, op1, op2;
 129   int result, temp;
 130
 131   op0 = State.regs[OP[0]];
 132   temp = OP[2];
 133   temp = (temp << 16) >> 16;
 134   temp &= ~0x1;
 135   op2 = temp;
 136   result = get_word (State.mem + op0 + op2);
 137   State.regs[OP[1]] = result;
 138 }
 139
 140 /* st.b */
 141 void
 142 OP_740 ()
 143 {
 144   unsigned int op0, op1, op2;
 145   int result, temp;
 146
 147   op0 = State.regs[OP[0]];
 148   op1 = State.regs[OP[1]];
 149   temp = OP[2];
 150   temp = (temp << 16) >> 16;
 151   op2 = temp;
 152   put_byte (State.mem + op0 + op2, op1);
 153 }
 154
 155 /* st.h */
 156 void
 157 OP_760 ()
 158 {
 159   unsigned int op0, op1, op2;
 160   int result, temp;
 161
 162   op0 = State.regs[OP[0]];
 163   op1 = State.regs[OP[1]];
 164   temp = OP[2];
 165   temp &= ~0x1;
 166   temp = (temp << 16) >> 16;
 167   op2 = temp;
 168   put_half (State.mem + op0 + op2, op1);
 169 }
 170
 171 /* st.w */
 172 void
 173 OP_10760 ()
 174 {
 175   unsigned int op0, op1, op2;
 176   int result, temp;
 177
 178   op0 = State.regs[OP[0]];
 179   op1 = State.regs[OP[1]];
 180   temp = OP[2];
 181   temp &= ~0x1;
 182   temp = (temp << 16) >> 16;
 183   op2 = temp;
 184   put_word (State.mem + op0 + op2, op1);
 185 }
 186
 187 /* bv disp9 */
 188 void
 189 OP_580 ()
 190 {
 191   unsigned int op0, psw;
 192   int temp;
 193
 194   temp = (State.regs[OP[0]] << 23) >> 23;
 195   op0 = temp;
 196   psw = State.sregs[5];
 197
 198   if ((psw & PSW_OV) != 0)
 199     State.pc += op0;
 200   else
 201     State.pc += 2;
 202 }
 203
 204 /* bl disp9 */
 205 void
 206 OP_581 ()
 207 {
 208   unsigned int op0, psw;
 209   int temp;
 210
 211   temp = (State.regs[OP[0]] << 23) >> 23;
 212   op0 = temp;
 213   psw = State.sregs[5];
 214
 215   if ((psw & PSW_CY) != 0)
 216     State.pc += op0;
 217   else
 218     State.pc += 2;
 219 }
 220
 221 /* be disp9 */
 222 void
 223 OP_582 ()
 224 {
 225   unsigned int op0, psw;
 226   int temp;
 227
 228   temp = (State.regs[OP[0]] << 23) >> 23;
 229   op0 = temp;
 230   psw = State.sregs[5];
 231
 232   if ((psw & PSW_Z) != 0)
 233     State.pc += op0;
 234   else
 235     State.pc += 2;
 236 }
 237
 238 /* bnh disp 9*/
 239 void
 240 OP_583 ()
 241 {
 242   unsigned int op0, psw;
 243   int temp;
 244
 245   temp = (State.regs[OP[0]] << 23) >> 23;
 246   op0 = temp;
 247   psw = State.sregs[5];
 248
 249   if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
 250     State.pc += op0;
 251   else
 252     State.pc += 2;
 253 }
 254
 255 /* bn disp9 */
 256 void
 257 OP_584 ()
 258 {
 259   unsigned int op0, psw;
 260   int temp;
 261
 262   temp = (State.regs[OP[0]] << 23) >> 23;
 263   op0 = temp;
 264   psw = State.sregs[5];
 265
 266   if ((psw & PSW_S) != 0)
 267     State.pc += op0;
 268   else
 269     State.pc += 2;
 270 }
 271
 272 /* br disp9 */
 273 void
 274 OP_585 ()
 275 {
 276   unsigned int op0;
 277   int temp;
 278
 279   temp = (State.regs[OP[0]] << 23) >> 23;
 280   op0 = temp;
 281   State.pc += op0;
 282 }
 283
 284 /* blt disp9 */
 285 void
 286 OP_586 ()
 287 {
 288   unsigned int op0, psw;
 289   int temp;
 290
 291   temp = (State.regs[OP[0]] << 23) >> 23;
 292   op0 = temp;
 293   psw = State.sregs[5];
 294
 295   if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
 296     State.pc += op0;
 297   else
 298     State.pc += 2;
 299 }
 300
 301 /* ble disp9 */
 302 void
 303 OP_587 ()
 304 {
 305   unsigned int op0, psw;
 306   int temp;
 307
 308   temp = (State.regs[OP[0]] << 23) >> 23;
 309   op0 = temp;
 310   psw = State.sregs[5];
 311
 312   if ((((psw & PSW_Z) != 0)
 313        || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
 314     State.pc += op0;
 315   else
 316     State.pc += 2;
 317 }
 318
 319 /* bnv disp9 */
 320 void
 321 OP_588 ()
 322 {
 323   unsigned int op0, psw;
 324   int temp;
 325
 326   temp = (State.regs[OP[0]] << 23) >> 23;
 327   op0 = temp;
 328   psw = State.sregs[5];
 329
 330   if ((psw & PSW_OV) == 0)
 331     State.pc += op0;
 332   else
 333     State.pc += 2;
 334 }
 335
 336 /* bnl disp9 */
 337 void
 338 OP_589 ()
 339 {
 340   unsigned int op0, psw;
 341   int temp;
 342
 343   temp = (State.regs[OP[0]] << 23) >> 23;
 344   op0 = temp;
 345   psw = State.sregs[5];
 346
 347   if ((psw & PSW_CY) == 0)
 348     State.pc += op0;
 349   else
 350     State.pc += 2;
 351 }
 352
 353 /* bne disp9 */
 354 void
 355 OP_58A ()
 356 {
 357   unsigned int op0, psw;
 358   int temp;
 359
 360   temp = (State.regs[OP[0]] << 23) >> 23;
 361   op0 = temp;
 362   psw = State.sregs[5];
 363
 364   if ((psw & PSW_Z) == 0)
 365     State.pc += op0;
 366   else
 367     State.pc += 2;
 368 }
 369
 370 /* bh disp9 */
 371 void
 372 OP_58B ()
 373 {
 374   unsigned int op0, psw;
 375   int temp;
 376
 377   temp = (State.regs[OP[0]] << 23) >> 23;
 378   op0 = temp;
 379   psw = State.sregs[5];
 380
 381   if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
 382     State.pc += op0;
 383   else
 384     State.pc += 2;
 385 }
 386
 387 /* bp disp9 */
 388 void
 389 OP_58C ()
 390 {
 391   unsigned int op0, psw;
 392   int temp;
 393
 394   temp = (State.regs[OP[0]] << 23) >> 23;
 395   op0 = temp;
 396   psw = State.sregs[5];
 397
 398   if ((psw & PSW_S) == 0)
 399     State.pc += op0;
 400   else
 401     State.pc += 2;
 402 }
 403
 404 /* bsa disp9 */
 405 void
 406 OP_58D ()
 407 {
 408   unsigned int op0, psw;
 409   int temp;
 410
 411   temp = (State.regs[OP[0]] << 23) >> 23;
 412   op0 = temp;
 413   psw = State.sregs[5];
 414
 415   if ((psw & PSW_SAT) != 0)
 416     State.pc += op0;
 417   else
 418     State.pc += 2;
 419 }
 420
 421 /* bge disp9 */
 422 void
 423 OP_58E ()
 424 {
 425   unsigned int op0, psw;
 426   int temp;
 427
 428   temp = (State.regs[OP[0]] << 23) >> 23;
 429   op0 = temp;
 430   psw = State.sregs[5];
 431
 432   if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
 433     State.pc += op0;
 434   else
 435     State.pc += 2;
 436 }
 437
 438 /* bgt disp9 */
 439 void
 440 OP_58F ()
 441 {
 442   unsigned int op0, psw;
 443   int temp;
 444
 445   temp = (State.regs[OP[0]] << 23) >> 23;
 446   op0 = temp;
 447   psw = State.sregs[5];
 448
 449   if ((((psw & PSW_Z) != 0)
 450        || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
 451     State.pc += op0;
 452   else
 453     State.pc += 2;
 454 }
 455
 456 /* jmp [reg1] */
 457 void
 458 OP_60 ()
 459 {
 460   /* interp.c will bump this by +2, so correct for it here.  */
 461   State.pc = State.regs[OP[0]] - 2;
 462 }
 463
 464 /* jarl disp22, reg */
 465 void
 466 OP_780 ()
 467 {
 468   unsigned int op0, opc;
 469   int temp;
 470
 471   temp = OP[0];
 472   temp = (temp << 10) >> 10;
 473   op0 = temp;
 474   opc = State.pc;
 475
 476   State.pc += temp;
 477
 478   /* Gross.  jarl X,r0 is really jr and doesn't save its result.  */
 479   if (OP[1] != 0)
 480     State.regs[OP[1]] = opc + 4;
 481 }
 482
 483 /* add reg, reg */
 484 void
 485 OP_1C0 ()
 486 {
 487   unsigned int op0, op1, result, z, s, cy, ov;
 488
 489   /* Compute the result.  */
 490   op0 = State.regs[OP[0]];
 491   op1 = State.regs[OP[1]];
 492   result = op0 + op1;
 493
 494   /* Compute the condition codes.  */
 495   z = (result == 0);
 496   s = (result & 0x80000000);
 497   cy = (result < op0 || result < op1);
 498   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 499         && (op0 & 0x80000000) != (result & 0x80000000));
 500
 501   /* Store the result and condition codes.  */
 502   State.regs[OP[1]] = result;
 503   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 504   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 505                      | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 506 }
 507
 508 /* add sign_extend(imm5), reg */
 509 void
 510 OP_240 ()
 511 {
 512   unsigned int op0, op1, result, z, s, cy, ov;
 513   int temp;
 514
 515   /* Compute the result.  */
 516   temp = (OP[0] & 0x1f);
 517   temp = (temp << 27) >> 27;
 518   op0 = temp;
 519   op1 = State.regs[OP[1]];
 520   result = op0 + op1;
 521
 522   /* Compute the condition codes.  */
 523   z = (result == 0);
 524   s = (result & 0x80000000);
 525   cy = (result < op0 || result < op1);
 526   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 527         && (op0 & 0x80000000) != (result & 0x80000000));
 528
 529   /* Store the result and condition codes.  */
 530   State.regs[OP[1]] = result;
 531   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 532   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 533                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 534 }
 535
 536 /* addi sign_extend(imm16), reg, reg */
 537 void
 538 OP_600 ()
 539 {
 540   unsigned int op0, op1, result, z, s, cy, ov;
 541   int temp;
 542
 543   /* Compute the result.  */
 544   temp = (OP[0] & 0xffff);
 545   temp = (temp << 16) >> 16;
 546   op0 = temp;
 547   op1 = State.regs[OP[1]];
 548   result = op0 + op1;
 549
 550   /* Compute the condition codes.  */
 551   z = (result == 0);
 552   s = (result & 0x80000000);
 553   cy = (result < op0 || result < op1);
 554   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 555         && (op0 & 0x80000000) != (result & 0x80000000));
 556
 557   /* Store the result and condition codes.  */
 558   State.regs[OP[2]] = result;
 559   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 560   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 561                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 562 }
 563
 564 /* sub reg1, reg2 */
 565 void
 566 OP_1A0 ()
 567 {
 568   unsigned int op0, op1, result, z, s, cy, ov;
 569
 570   /* Compute the result.  */
 571   op0 = State.regs[OP[0]];
 572   op1 = State.regs[OP[1]];
 573   result = op1 - op0;
 574
 575   /* Compute the condition codes.  */
 576   z = (result == 0);
 577   s = (result & 0x80000000);
 578   cy = (result < -op0);
 579   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 580         && (op1 & 0x80000000) != (result & 0x80000000));
 581
 582   /* Store the result and condition codes.  */
 583   State.regs[OP[1]] = result;
 584   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 585   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 586                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 587 }
 588
 589 /* subr reg1, reg2 */
 590 void
 591 OP_180 ()
 592 {
 593   unsigned int op0, op1, result, z, s, cy, ov;
 594
 595   /* Compute the result.  */
 596   op0 = State.regs[OP[0]];
 597   op1 = State.regs[OP[1]];
 598   result = op0 - op1;
 599
 600   /* Compute the condition codes.  */
 601   z = (result == 0);
 602   s = (result & 0x80000000);
 603   cy = (result < -op1);
 604   ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
 605         && (op0 & 0x80000000) != (result & 0x80000000));
 606
 607   /* Store the result and condition codes.  */
 608   State.regs[OP[1]] = result;
 609   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 610   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 611                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 612 }
 613
 614 /* mulh reg1, reg2 */
 615 void
 616 OP_E0 ()
 617 {
 618   State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
 619                        * (State.regs[OP[0]] & 0xffff));
 620 }
 621
 622 /* mulh sign_extend(imm5), reg2
 623
 624    Condition codes */
 625 void
 626 OP_2E0 ()
 627 {
 628   int value = OP[0];
 629
 630   value = (value << 27) >> 27;
 631
 632   State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
 633 }
 634
 635 /* mulhi imm16, reg1, reg2 */
 636 void
 637 OP_6E0 ()
 638 {
 639   int value = OP[0];
 640
 641   value = value & 0xffff;
 642
 643   State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
 644 }
 645
 646 /* divh reg1, reg2 */
 647 void
 648 OP_40 ()
 649 {
 650   unsigned int op0, op1, result, z, s, cy, ov;
 651   int temp;
 652
 653   /* Compute the result.  */
 654   temp = State.regs[OP[0]] & 0xffff;
 655   temp = (temp << 16) >> 16;
 656   op0 = temp;
 657   op1 = State.regs[OP[1]];
 658
 659   if (op0 == 0xffffffff && op1 == 0x80000000)
 660     {
 661       result = 0x80000000;
 662       ov = 1;
 663     }
 664   else if (op0 != 0)
 665     {
 666       result = op1 / op0;
 667       ov = 0;
 668     }
 669   else
 670     ov = 1;
 671
 672   /* Compute the condition codes.  */
 673   z = (result == 0);
 674   s = (result & 0x80000000);
 675
 676   /* Store the result and condition codes.  */
 677   State.regs[OP[1]] = result;
 678   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
 679   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 680                 | (ov ? PSW_OV : 0));
 681 }
 682
 683 /* cmp reg, reg */
 684 void
 685 OP_1E0 ()
 686 {
 687   unsigned int op0, op1, result, z, s, cy, ov;
 688
 689   /* Compute the result.  */
 690   op0 = State.regs[OP[0]];
 691   op1 = State.regs[OP[1]];
 692   result = op1 - op0;
 693
 694   /* Compute the condition codes.  */
 695   z = (result == 0);
 696   s = (result & 0x80000000);
 697   cy = (result < -op0);
 698   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 699         && (op1 & 0x80000000) != (result & 0x80000000));
 700
 701   /* Set condition codes.  */
 702   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 703   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 704                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 705 }
 706
 707 /* cmp sign_extend(imm5), reg */
 708 void
 709 OP_260 ()
 710 {
 711   unsigned int op0, op1, result, z, s, cy, ov;
 712   int temp;
 713
 714   /* Compute the result.  */
 715   temp = OP[0];
 716   temp = (temp << 27) >> 27;
 717   op0 = temp;
 718   op1 = State.regs[OP[1]];
 719   result = op1 - op0;
 720
 721   /* Compute the condition codes.  */
 722   z = (result == 0);
 723   s = (result & 0x80000000);
 724   cy = (result < -op0);
 725   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 726         && (op1 & 0x80000000) != (result & 0x80000000));
 727
 728   /* Set condition codes.  */
 729   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 730   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 731                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 732 }
 733
 734 /* setf cccc,reg2 */
 735 void
 736 OP_7E0 ()
 737 {
 738   /* Hack alert.  We turn off a bit in op0 since we really only
 739      wanted 4 bits.  */
 740   unsigned int op0, psw, result;
 741
 742   op0 = OP[0] & 0xf;
 743   psw = State.sregs[5];
 744
 745   switch (op0)
 746     {
 747       case 0x0:
 748         result = ((psw & PSW_OV) != 0);
 749         break;
 750       case 0x1:
 751         result = ((psw & PSW_CY) != 0);
 752         break;
 753       case 0x2:
 754         result = ((psw & PSW_Z) != 0);
 755         break;
 756       case 0x3:
 757         result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
 758         break;
 759       case 0x4:
 760         result = ((psw & PSW_S) != 0);
 761         break;
 762       case 0x5:
 763         result = 1;
 764         break;
 765       case 0x6:
 766         result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
 767         break;
 768       case 0x7:
 769         result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
 770                   || ((psw & PSW_Z) != 0)) != 0);
 771         break;
 772       case 0x8:
 773         result = ((psw & PSW_OV) == 0);
 774         break;
 775       case 0x9:
 776         result = ((psw & PSW_CY) == 0);
 777         break;
 778       case 0xa:
 779         result = ((psw & PSW_Z) == 0);
 780         break;
 781       case 0xb:
 782         result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
 783         break;
 784       case 0xc:
 785         result = ((psw & PSW_S) == 0);
 786         break;
 787       case 0xd:
 788         result = ((psw & PSW_SAT) != 0);
 789         break;
 790       case 0xe:
 791         result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
 792         break;
 793       case 0xf:
 794         result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
 795                   || ((psw & PSW_Z) != 0)) == 0);
 796         break;
 797     }
 798
 799   State.regs[OP[1]] = result;
 800 }
 801
 802 /* satadd reg,reg */
 803 void
 804 OP_C0 ()
 805 {
 806   unsigned int op0, op1, result, z, s, cy, ov, sat;
 807
 808   /* Compute the result.  */
 809   op0 = State.regs[OP[0]];
 810   op1 = State.regs[OP[1]];
 811   result = op0 + op1;
 812
 813   /* Compute the condition codes.  */
 814   z = (result == 0);
 815   s = (result & 0x80000000);
 816   cy = (result < op0 || result < op1);
 817   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 818         && (op0 & 0x80000000) != (result & 0x80000000));
 819   sat = ov;
 820
 821   /* Store the result and condition codes.  */
 822   State.regs[OP[1]] = result;
 823   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 824   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 825                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 826                 | (sat ? PSW_SAT : 0));
 827
 828   /* Handle saturated results.  */
 829   if (sat && s)
 830     State.regs[OP[1]] = 0x80000000;
 831   else if (sat)
 832     State.regs[OP[1]] = 0x7fffffff;
 833 }
 834
 835 /* satadd sign_extend(imm5), reg */
 836 void
 837 OP_220 ()
 838 {
 839   unsigned int op0, op1, result, z, s, cy, ov, sat;
 840
 841   int temp;
 842
 843   /* Compute the result.  */
 844   temp = (OP[0] & 0x1f);
 845   temp = (temp << 27) >> 27;
 846   op0 = temp;
 847   op1 = State.regs[OP[1]];
 848   result = op0 + op1;
 849
 850   /* Compute the condition codes.  */
 851   z = (result == 0);
 852   s = (result & 0x80000000);
 853   cy = (result < op0 || result < op1);
 854   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 855         && (op0 & 0x80000000) != (result & 0x80000000));
 856   sat = ov;
 857
 858   /* Store the result and condition codes.  */
 859   State.regs[OP[1]] = result;
 860   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 861   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 862                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 863                 | (sat ? PSW_SAT : 0));
 864
 865   /* Handle saturated results.  */
 866   if (sat && s)
 867     State.regs[OP[1]] = 0x80000000;
 868   else if (sat)
 869     State.regs[OP[1]] = 0x7fffffff;
 870 }
 871
 872 /* satsub reg1, reg2 */
 873 void
 874 OP_A0 ()
 875 {
 876   unsigned int op0, op1, result, z, s, cy, ov, sat;
 877
 878   /* Compute the result.  */
 879   op0 = State.regs[OP[0]];
 880   op1 = State.regs[OP[1]];
 881   result = op1 - op0;
 882
 883   /* Compute the condition codes.  */
 884   z = (result == 0);
 885   s = (result & 0x80000000);
 886   cy = (result < -op0);
 887   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 888         && (op1 & 0x80000000) != (result & 0x80000000));
 889   sat = ov;
 890
 891   /* Store the result and condition codes.  */
 892   State.regs[OP[1]] = result;
 893   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 894   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 895                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 896                 | (sat ? PSW_SAT : 0));
 897
 898   /* Handle saturated results.  */
 899   if (sat && s)
 900     State.regs[OP[1]] = 0x80000000;
 901   else if (sat)
 902     State.regs[OP[1]] = 0x7fffffff;
 903 }
 904
 905 /* satsubi sign_extend(imm16), reg */
 906 void
 907 OP_660 ()
 908 {
 909   unsigned int op0, op1, result, z, s, cy, ov, sat;
 910   int temp;
 911
 912   /* Compute the result.  */
 913   temp = (OP[0] & 0xffff);
 914   temp = (temp << 16) >> 16;
 915   op0 = temp;
 916   op1 = State.regs[OP[1]];
 917   result = op1 - op0;
 918
 919   /* Compute the condition codes.  */
 920   z = (result == 0);
 921   s = (result & 0x80000000);
 922   cy = (result < -op0);
 923   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 924         && (op1 & 0x80000000) != (result & 0x80000000));
 925   sat = ov;
 926
 927   /* Store the result and condition codes.  */
 928   State.regs[OP[1]] = result;
 929   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 930   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 931                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 932                 | (sat ? PSW_SAT : 0));
 933
 934   /* Handle saturated results.  */
 935   if (sat && s)
 936     State.regs[OP[1]] = 0x80000000;
 937   else if (sat)
 938     State.regs[OP[1]] = 0x7fffffff;
 939 }
 940
 941 void
 942 OP_80 ()
 943 {
 944   unsigned int op0, op1, result, z, s, cy, ov, sat;
 945
 946   /* Compute the result.  */
 947   op0 = State.regs[OP[0]];
 948   op1 = State.regs[OP[1]];
 949   result = op0 - op1;
 950
 951   /* Compute the condition codes.  */
 952   z = (result == 0);
 953   s = (result & 0x80000000);
 954   cy = (result < -op0);
 955   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 956         && (op1 & 0x80000000) != (result & 0x80000000));
 957   sat = ov;
 958
 959   /* Store the result and condition codes.  */
 960   State.regs[OP[1]] = result;
 961   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 962   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 963                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 964                 | (sat ? PSW_SAT : 0));
 965
 966   /* Handle saturated results.  */
 967   if (sat && s)
 968     State.regs[OP[1]] = 0x80000000;
 969   else if (sat)
 970     State.regs[OP[1]] = 0x7fffffff;
 971 }
 972
 973 /* tst reg,reg */
 974 void
 975 OP_160 ()
 976 {
 977   unsigned int op0, op1, result, z, s, cy, ov;
 978
 979   /* Compute the result.  */
 980   op0 = State.regs[OP[0]];
 981   op1 = State.regs[OP[1]];
 982   result = op0 & op1;
 983
 984   /* Compute the condition codes.  */
 985   z = (result == 0);
 986   s = (result & 0x80000000);
 987
 988   /* Store the condition codes.  */
 989   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
 990   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 991 }
 992
 993 /* mov reg, reg */
 994 void
 995 OP_0 ()
 996 {
 997   State.regs[OP[1]] = State.regs[OP[0]];
 998 }
 999
1000 /* mov sign_extend(imm5), reg */
1001 void
1002 OP_200 ()
1003 {
1004   int value = OP[0];
1005
1006   value = (value << 27) >> 27;
1007   State.regs[OP[1]] = value;
1008 }
1009
1010 /* movea sign_extend(imm16), reg, reg  */
1011
1012 void
1013 OP_620 ()
1014 {
1015   int value = OP[0];
1016
1017   value = (value << 16) >> 16;
1018
1019   State.regs[OP[2]] = State.regs[OP[1]] + value;
1020 }
1021
1022 /* movhi imm16, reg, reg */
1023 void
1024 OP_640 ()
1025 {
1026   int value = OP[0];
1027
1028   value = (value & 0xffff) << 16;
1029
1030   State.regs[OP[2]] = State.regs[OP[1]] + value;
1031 }
1032
1033 /* sar zero_extend(imm5),reg1 */
1034 void
1035 OP_2A0 ()
1036 {
1037   unsigned int op0, op1, result, z, s, cy, ov;
1038
1039   op0 = OP[0] & 0x1f;
1040   op1 = State.regs[OP[1]];
1041   result = (signed)op1 >> op0;
1042
1043   /* Compute the condition codes.  */
1044   z = (result == 0);
1045   s = (result & 0x80000000);
1046   cy = (op1 & (1 << (op0 - 1)));
1047
1048   /* Store the result and condition codes.  */
1049   State.regs[OP[1]] = result;
1050   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1051   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1052                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1053 }
1054
1055 /* sar reg1, reg2 */
1056 void
1057 OP_A007E0 ()
1058 {
1059   unsigned int op0, op1, result, z, s, cy, ov;
1060
1061   op0 = State.regs[OP[0]] & 0x1f;
1062   op1 = State.regs[OP[1]];
1063   result = (signed)op1 >> op0;
1064
1065   /* Compute the condition codes.  */
1066   z = (result == 0);
1067   s = (result & 0x80000000);
1068   cy = (op1 & (1 << (op0 - 1)));
1069
1070   /* Store the result and condition codes.  */
1071   State.regs[OP[1]] = result;
1072   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1073   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1074                 | (cy ? PSW_CY : 0));
1075 }
1076
1077 /* shl zero_extend(imm5),reg1 */
1078 void
1079 OP_2C0 ()
1080 {
1081   unsigned int op0, op1, result, z, s, cy, ov;
1082
1083   op0 = OP[0] & 0x1f;
1084   op1 = State.regs[OP[1]];
1085   result = op1 << op0;
1086
1087   /* Compute the condition codes.  */
1088   z = (result == 0);
1089   s = (result & 0x80000000);
1090   cy = (op1 & (1 << (32 - op0)));
1091
1092   /* Store the result and condition codes.  */
1093   State.regs[OP[1]] = result;
1094   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1095   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1096                 | (cy ? PSW_CY : 0));
1097 }
1098
1099 /* shl reg1, reg2 */
1100 void
1101 OP_C007E0 ()
1102 {
1103   unsigned int op0, op1, result, z, s, cy, ov;
1104
1105   op0 = State.regs[OP[0]] & 0x1f;
1106   op1 = State.regs[OP[1]];
1107   result = op1 << op0;
1108
1109   /* Compute the condition codes.  */
1110   z = (result == 0);
1111   s = (result & 0x80000000);
1112   cy = (op1 & (1 << (32 - op0)));
1113
1114   /* Store the result and condition codes.  */
1115   State.regs[OP[1]] = result;
1116   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1117   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1118                 | (cy ? PSW_CY : 0));
1119 }
1120
1121 /* shr zero_extend(imm5),reg1 */
1122 void
1123 OP_280 ()
1124 {
1125   unsigned int op0, op1, result, z, s, cy, ov;
1126
1127   op0 = OP[0] & 0x1f;
1128   op1 = State.regs[OP[1]];
1129   result = op1 >> op0;
1130
1131   /* Compute the condition codes.  */
1132   z = (result == 0);
1133   s = (result & 0x80000000);
1134   cy = (op1 & (1 << (op0 - 1)));
1135
1136   /* Store the result and condition codes.  */
1137   State.regs[OP[1]] = result;
1138   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1139   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1140                 | (cy ? PSW_CY : 0));
1141 }
1142
1143 /* shr reg1, reg2 */
1144 void
1145 OP_8007E0 ()
1146 {
1147   unsigned int op0, op1, result, z, s, cy, ov;
1148
1149   op0 = State.regs[OP[0]] & 0x1f;
1150   op1 = State.regs[OP[1]];
1151   result = op1 >> op0;
1152
1153   /* Compute the condition codes.  */
1154   z = (result == 0);
1155   s = (result & 0x80000000);
1156   cy = (op1 & (1 << (op0 - 1)));
1157
1158   /* Store the result and condition codes.  */
1159   State.regs[OP[1]] = result;
1160   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1161   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1162                 | (cy ? PSW_CY : 0));
1163 }
1164
1165 /* or reg, reg */
1166 void
1167 OP_100 ()
1168 {
1169   unsigned int op0, op1, result, z, s, cy, ov;
1170
1171   /* Compute the result.  */
1172   op0 = State.regs[OP[0]];
1173   op1 = State.regs[OP[1]];
1174   result = op0 | op1;
1175
1176   /* Compute the condition codes.  */
1177   z = (result == 0);
1178   s = (result & 0x80000000);
1179
1180   /* Store the result and condition codes.  */
1181   State.regs[OP[1]] = result;
1182   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1183   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1184 }
1185
1186 /* ori zero_extend(imm16), reg, reg */
1187 void
1188 OP_680 ()
1189 {
1190   unsigned int op0, op1, result, z, s, cy, ov;
1191
1192   op0 = OP[0] & 0xffff;
1193   op1 = State.regs[OP[1]];
1194   result = op0 | op1;
1195
1196   /* Compute the condition codes.  */
1197   z = (result == 0);
1198   s = (result & 0x80000000);
1199
1200   /* Store the result and condition codes.  */
1201   State.regs[OP[2]] = result;
1202   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1203   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1204 }
1205
1206 /* and reg, reg */
1207 void
1208 OP_140 ()
1209 {
1210   unsigned int op0, op1, result, z, s, cy, ov;
1211
1212   /* Compute the result.  */
1213   op0 = State.regs[OP[0]];
1214   op1 = State.regs[OP[1]];
1215   result = op0 & op1;
1216
1217   /* Compute the condition codes.  */
1218   z = (result == 0);
1219   s = (result & 0x80000000);
1220
1221   /* Store the result and condition codes.  */
1222   State.regs[OP[1]] = result;
1223   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1224   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1225 }
1226
1227 /* andi zero_extend(imm16), reg, reg */
1228 void
1229 OP_6C0 ()
1230 {
1231   unsigned int op0, op1, result, z, s, cy, ov;
1232
1233   op0 = OP[0] & 0xffff;
1234   op1 = State.regs[OP[1]];
1235   result = op0 & op1;
1236
1237   /* Compute the condition codes.  */
1238   z = (result == 0);
1239
1240   /* Store the result and condition codes.  */
1241   State.regs[OP[2]] = result;
1242   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1243   State.sregs[5] |= (z ? PSW_Z : 0);
1244 }
1245
1246 /* xor reg, reg */
1247 void
1248 OP_120 ()
1249 {
1250   unsigned int op0, op1, result, z, s, cy, ov;
1251
1252   /* Compute the result.  */
1253   op0 = State.regs[OP[0]];
1254   op1 = State.regs[OP[1]];
1255   result = op0 ^ op1;
1256
1257   /* Compute the condition codes.  */
1258   z = (result == 0);
1259   s = (result & 0x80000000);
1260
1261   /* Store the result and condition codes.  */
1262   State.regs[OP[1]] = result;
1263   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1264   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1265 }
1266
1267 /* xori zero_extend(imm16), reg, reg */
1268 void
1269 OP_6A0 ()
1270 {
1271   unsigned int op0, op1, result, z, s, cy, ov;
1272
1273   op0 = OP[0] & 0xffff;
1274   op1 = State.regs[OP[1]];
1275   result = op0 ^ op1;
1276
1277   /* Compute the condition codes.  */
1278   z = (result == 0);
1279   s = (result & 0x80000000);
1280
1281   /* Store the result and condition codes.  */
1282   State.regs[OP[2]] = result;
1283   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1284   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1285 }
1286
1287 /* not reg1, reg2 */
1288 void
1289 OP_20 ()
1290 {
1291   unsigned int op0, result, z, s, cy, ov;
1292
1293   /* Compute the result.  */
1294   op0 = State.regs[OP[0]];
1295   result = ~op0;
1296
1297   /* Compute the condition codes.  */
1298   z = (result == 0);
1299   s = (result & 0x80000000);
1300
1301   /* Store the result and condition codes.  */
1302   State.regs[OP[1]] = result;
1303   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1304   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1305 }
1306
1307 /* set1 */
1308 void
1309 OP_7C0 ()
1310 {
1311   unsigned int op0, op1, op2;
1312   int result, temp;
1313
1314   op0 = State.regs[OP[0]];
1315   op1 = OP[1] & 0x7;
1316   temp = OP[2];
1317   temp = (temp << 16) >> 16;
1318   op2 = temp;
1319   temp = get_byte (State.mem + op0 + op2);
1320   State.sregs[5] &= ~PSW_Z;
1321   if ((temp & (1 << op1)) == 0)
1322     State.sregs[5] |= PSW_Z;
1323   temp |= ~(1 << op1);
1324   put_byte (State.mem + op0 + op2, temp);
1325 }
1326
1327 /* not1 */
1328 void
1329 OP_47C0 ()
1330 {
1331   unsigned int op0, op1, op2;
1332   int result, temp;
1333
1334   op0 = State.regs[OP[0]];
1335   op1 = OP[1] & 0x7;
1336   temp = OP[2];
1337   temp = (temp << 16) >> 16;
1338   op2 = temp;
1339   temp = get_byte (State.mem + op0 + op2);
1340   State.sregs[5] &= ~PSW_Z;
1341   if ((temp & (1 << op1)) == 0)
1342     State.sregs[5] |= PSW_Z;
1343   temp ^= ~(1 << op1);
1344   put_byte (State.mem + op0 + op2, temp);
1345 }
1346
1347 /* clr1 */
1348 void
1349 OP_87C0 ()
1350 {
1351   unsigned int op0, op1, op2;
1352   int result, temp;
1353
1354   op0 = State.regs[OP[0]];
1355   op1 = OP[1] & 0x7;
1356   temp = OP[2];
1357   temp = (temp << 16) >> 16;
1358   op2 = temp;
1359   temp = get_byte (State.mem + op0 + op2);
1360   State.sregs[5] &= ~PSW_Z;
1361   if ((temp & (1 << op1)) == 0)
1362     State.sregs[5] |= PSW_Z;
1363   temp &= ~(1 << op1);
1364   put_byte (State.mem + op0 + op2, temp);
1365 }
1366
1367 /* tst1 */
1368 void
1369 OP_C7C0 ()
1370 {
1371   unsigned int op0, op1, op2;
1372   int result, temp;
1373
1374   op0 = State.regs[OP[0]];
1375   op1 = OP[1] & 0x7;
1376   temp = OP[2];
1377   temp = (temp << 16) >> 16;
1378   op2 = temp;
1379   temp = get_byte (State.mem + op0 + op2);
1380   State.sregs[5] &= ~PSW_Z;
1381   if ((temp & (1 << op1)) == 0)
1382     State.sregs[5] |= PSW_Z;
1383 }
1384
1385 /* di */
1386 void
1387 OP_16007E0 ()
1388 {
1389   State.sregs[5] |= PSW_ID;
1390 }
1391
1392 /* ei */
1393 void
1394 OP_16087E0 ()
1395 {
1396   State.sregs[5] &= ~PSW_ID;
1397 }
1398
1399 /* halt, not supported */
1400 void
1401 OP_12007E0 ()
1402 {
1403   abort ();
1404 }
1405
1406 /* reti, not supported */
1407 void
1408 OP_14007E0 ()
1409 {
1410   abort ();
1411 }
1412
1413 /* trap, not supportd */
1414 void
1415 OP_10007E0 ()
1416 {
1417   abort ();
1418 }
1419
1420 /* ldsr, reg,reg */
1421 void
1422 OP_2007E0 ()
1423 {
1424   unsigned int op0;
1425
1426   op0 = State.regs[OP[0]];
1427   State.sregs[OP[1]] = op0;
1428 }
1429
1430 /* stsr, not supported */
1431 void
1432 OP_4007E0 ()
1433 {
1434   unsigned int op0;
1435
1436   op0 = State.sregs[OP[1]];
1437   State.regs[OP[0]] = op0;
1438 }
1439