sim/v850/simops.c

   1 #include <signal.h>
   2 #include "v850_sim.h"
   3 #include "simops.h"
   4
   5 void
   6 OP_220 ()
   7 {
   8 }
   9
  10 void
  11 OP_10760 ()
  12 {
  13 }
  14
  15 void
  16 OP_C7C0 ()
  17 {
  18 }
  19
  20 void
  21 OP_760 ()
  22 {
  23 }
  24
  25 /* bv disp9 */
  26 void
  27 OP_580 ()
  28 {
  29   unsigned int op0, psw;
  30   int temp;
  31
  32   temp = (State.regs[OP[0]] << 23) >> 23;
  33   op0 = temp;
  34   psw = State.psw;
  35
  36   if ((psw & PSW_OV) != 0)
  37     State.pc += op0;
  38   else
  39     State.pc += 2;
  40 }
  41
  42 /* bl disp9 */
  43 void
  44 OP_581 ()
  45 {
  46   unsigned int op0, psw;
  47   int temp;
  48
  49   temp = (State.regs[OP[0]] << 23) >> 23;
  50   op0 = temp;
  51   psw = State.psw;
  52
  53   if ((psw & PSW_CY) != 0)
  54     State.pc += op0;
  55   else
  56     State.pc += 2;
  57 }
  58
  59 /* be disp9 */
  60 void
  61 OP_582 ()
  62 {
  63   unsigned int op0, psw;
  64   int temp;
  65
  66   temp = (State.regs[OP[0]] << 23) >> 23;
  67   op0 = temp;
  68   psw = State.psw;
  69
  70   if ((psw & PSW_Z) != 0)
  71     State.pc += op0;
  72   else
  73     State.pc += 2;
  74 }
  75
  76 /* bnh disp 9*/
  77 void
  78 OP_583 ()
  79 {
  80   unsigned int op0, psw;
  81   int temp;
  82
  83   temp = (State.regs[OP[0]] << 23) >> 23;
  84   op0 = temp;
  85   psw = State.psw;
  86
  87   if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
  88     State.pc += op0;
  89   else
  90     State.pc += 2;
  91 }
  92
  93 /* bn disp9 */
  94 void
  95 OP_584 ()
  96 {
  97   unsigned int op0, psw;
  98   int temp;
  99
 100   temp = (State.regs[OP[0]] << 23) >> 23;
 101   op0 = temp;
 102   psw = State.psw;
 103
 104   if ((psw & PSW_S) != 0)
 105     State.pc += op0;
 106   else
 107     State.pc += 2;
 108 }
 109
 110 /* br disp9 */
 111 void
 112 OP_585 ()
 113 {
 114   unsigned int op0;
 115   int temp;
 116
 117   temp = (State.regs[OP[0]] << 23) >> 23;
 118   op0 = temp;
 119   State.pc += op0;
 120 }
 121
 122 /* blt disp9 */
 123 void
 124 OP_586 ()
 125 {
 126   unsigned int op0, psw;
 127   int temp;
 128
 129   temp = (State.regs[OP[0]] << 23) >> 23;
 130   op0 = temp;
 131   psw = State.psw;
 132
 133   if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
 134     State.pc += op0;
 135   else
 136     State.pc += 2;
 137 }
 138
 139 /* ble disp9 */
 140 void
 141 OP_587 ()
 142 {
 143   unsigned int op0, psw;
 144   int temp;
 145
 146   temp = (State.regs[OP[0]] << 23) >> 23;
 147   op0 = temp;
 148   psw = State.psw;
 149
 150   if ((((psw & PSW_Z) != 0)
 151        || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
 152     State.pc += op0;
 153   else
 154     State.pc += 2;
 155 }
 156
 157 /* bnv disp9 */
 158 void
 159 OP_588 ()
 160 {
 161   unsigned int op0, psw;
 162   int temp;
 163
 164   temp = (State.regs[OP[0]] << 23) >> 23;
 165   op0 = temp;
 166   psw = State.psw;
 167
 168   if ((psw & PSW_OV) == 0)
 169     State.pc += op0;
 170   else
 171     State.pc += 2;
 172 }
 173
 174 /* bnl disp9 */
 175 void
 176 OP_589 ()
 177 {
 178   unsigned int op0, psw;
 179   int temp;
 180
 181   temp = (State.regs[OP[0]] << 23) >> 23;
 182   op0 = temp;
 183   psw = State.psw;
 184
 185   if ((psw & PSW_CY) == 0)
 186     State.pc += op0;
 187   else
 188     State.pc += 2;
 189 }
 190
 191 /* bne disp9 */
 192 void
 193 OP_58A ()
 194 {
 195   unsigned int op0, psw;
 196   int temp;
 197
 198   temp = (State.regs[OP[0]] << 23) >> 23;
 199   op0 = temp;
 200   psw = State.psw;
 201
 202   if ((psw & PSW_Z) == 0)
 203     State.pc += op0;
 204   else
 205     State.pc += 2;
 206 }
 207
 208 /* bh disp9 */
 209 void
 210 OP_58B ()
 211 {
 212   unsigned int op0, psw;
 213   int temp;
 214
 215   temp = (State.regs[OP[0]] << 23) >> 23;
 216   op0 = temp;
 217   psw = State.psw;
 218
 219   if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
 220     State.pc += op0;
 221   else
 222     State.pc += 2;
 223 }
 224
 225 /* bp disp9 */
 226 void
 227 OP_58C ()
 228 {
 229   unsigned int op0, psw;
 230   int temp;
 231
 232   temp = (State.regs[OP[0]] << 23) >> 23;
 233   op0 = temp;
 234   psw = State.psw;
 235
 236   if ((psw & PSW_S) == 0)
 237     State.pc += op0;
 238   else
 239     State.pc += 2;
 240 }
 241
 242 /* bsa disp9 */
 243 void
 244 OP_58D ()
 245 {
 246   unsigned int op0, psw;
 247   int temp;
 248
 249   temp = (State.regs[OP[0]] << 23) >> 23;
 250   op0 = temp;
 251   psw = State.psw;
 252
 253   if ((psw & PSW_SAT) != 0)
 254     State.pc += op0;
 255   else
 256     State.pc += 2;
 257 }
 258
 259 /* bge disp9 */
 260 void
 261 OP_58E ()
 262 {
 263   unsigned int op0, psw;
 264   int temp;
 265
 266   temp = (State.regs[OP[0]] << 23) >> 23;
 267   op0 = temp;
 268   psw = State.psw;
 269
 270   if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
 271     State.pc += op0;
 272   else
 273     State.pc += 2;
 274 }
 275
 276 /* bgt disp9 */
 277 void
 278 OP_58F ()
 279 {
 280   unsigned int op0, psw;
 281   int temp;
 282
 283   temp = (State.regs[OP[0]] << 23) >> 23;
 284   op0 = temp;
 285   psw = State.psw;
 286
 287   if ((((psw & PSW_Z) != 0)
 288        || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
 289     State.pc += op0;
 290   else
 291     State.pc += 2;
 292 }
 293
 294 void
 295 OP_660 ()
 296 {
 297 }
 298
 299
 300 /* add reg, reg */
 301 void
 302 OP_1C0 ()
 303 {
 304   unsigned int op0, op1, result, z, s, cy, ov;
 305
 306   /* Compute the result.  */
 307   op0 = State.regs[OP[0]];
 308   op1 = State.regs[OP[1]];
 309   result = op0 + op1;
 310
 311   /* Compute the condition codes.  */
 312   z = (result == 0);
 313   s = (result & 0x80000000);
 314   cy = (result < op0 || result < op1);
 315   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 316         && (op0 & 0x80000000) != (result & 0x80000000));
 317
 318   /* Store the result and condition codes.  */
 319   State.regs[OP[1]] = result;
 320   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 321   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 322                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 323 }
 324
 325 /* add sign_extend(imm5), reg */
 326 void
 327 OP_240 ()
 328 {
 329   unsigned int op0, op1, result, z, s, cy, ov;
 330   int temp;
 331
 332   /* Compute the result.  */
 333   temp = (OP[0] & 0x1f);
 334   temp = (temp << 27) >> 27;
 335   op0 = temp;
 336   op1 = State.regs[OP[1]];
 337   result = op0 + op1;
 338
 339   /* Compute the condition codes.  */
 340   z = (result == 0);
 341   s = (result & 0x80000000);
 342   cy = (result < op0 || result < op1);
 343   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 344         && (op0 & 0x80000000) != (result & 0x80000000));
 345
 346   /* Store the result and condition codes.  */
 347   State.regs[OP[1]] = result;
 348   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 349   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 350                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 351 }
 352
 353 /* addi sign_extend(imm16), reg, reg */
 354 void
 355 OP_600 ()
 356 {
 357   unsigned int op0, op1, result, z, s, cy, ov;
 358   int temp;
 359
 360   /* Compute the result.  */
 361   temp = (OP[0] & 0xffff);
 362   temp = (temp << 16) >> 16;
 363   op0 = temp;
 364   op1 = State.regs[OP[1]];
 365   result = op0 + op1;
 366
 367   /* Compute the condition codes.  */
 368   z = (result == 0);
 369   s = (result & 0x80000000);
 370   cy = (result < op0 || result < op1);
 371   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 372         && (op0 & 0x80000000) != (result & 0x80000000));
 373
 374   /* Store the result and condition codes.  */
 375   State.regs[OP[2]] = result;
 376   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 377   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 378                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 379 }
 380
 381 /* sub reg1, reg2 */
 382 void
 383 OP_1A0 ()
 384 {
 385   unsigned int op0, op1, result, z, s, cy, ov;
 386
 387   /* Compute the result.  */
 388   op0 = State.regs[OP[0]];
 389   op1 = State.regs[OP[1]];
 390   result = op1 - op0;
 391
 392   /* Compute the condition codes.  */
 393   z = (result == 0);
 394   s = (result & 0x80000000);
 395   cy = (result < -op0);
 396   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 397         && (op1 & 0x80000000) != (result & 0x80000000));
 398
 399   /* Store the result and condition codes.  */
 400   State.regs[OP[1]] = result;
 401   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 402   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 403                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 404 }
 405
 406 /* subr reg1, reg2 */
 407 void
 408 OP_180 ()
 409 {
 410   unsigned int op0, op1, result, z, s, cy, ov;
 411
 412   /* Compute the result.  */
 413   op0 = State.regs[OP[0]];
 414   op1 = State.regs[OP[1]];
 415   result = op0 - op1;
 416
 417   /* Compute the condition codes.  */
 418   z = (result == 0);
 419   s = (result & 0x80000000);
 420   cy = (result < -op1);
 421   ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
 422         && (op0 & 0x80000000) != (result & 0x80000000));
 423
 424   /* Store the result and condition codes.  */
 425   State.regs[OP[1]] = result;
 426   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 427   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 428                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 429 }
 430
 431 /* mulh reg1, reg2 */
 432 void
 433 OP_E0 ()
 434 {
 435   State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
 436                        * (State.regs[OP[0]] & 0xffff));
 437 }
 438
 439 /* mulh sign_extend(imm5), reg2
 440
 441    Condition codes */
 442 void
 443 OP_2E0 ()
 444 {
 445   int value = OP[0];
 446
 447   value = (value << 27) >> 27;
 448
 449   State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
 450 }
 451
 452 /* mulhi imm16, reg1, reg2 */
 453 void
 454 OP_6E0 ()
 455 {
 456   int value = OP[0];
 457
 458   value = value & 0xffff;
 459
 460   State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
 461 }
 462
 463 /* divh reg1, reg2 */
 464 void
 465 OP_40 ()
 466 {
 467   unsigned int op0, op1, result, z, s, cy, ov;
 468   int temp;
 469
 470   /* Compute the result.  */
 471   temp = State.regs[OP[0]] & 0xffff;
 472   temp = (temp << 16) >> 16;
 473   op0 = temp;
 474   op1 = State.regs[OP[1]];
 475
 476   if (op0 == 0xffffffff && op1 == 0x80000000)
 477     {
 478       result = 0x80000000;
 479       ov = 1;
 480     }
 481   else if (op0 != 0)
 482     {
 483       result = op1 / op0;
 484       ov = 0;
 485     }
 486   else
 487     ov = 1;
 488
 489   /* Compute the condition codes.  */
 490   z = (result == 0);
 491   s = (result & 0x80000000);
 492
 493   /* Store the result and condition codes.  */
 494   State.regs[OP[1]] = result;
 495   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 496   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 497                 | (ov ? PSW_OV : 0));
 498 }
 499
 500 /* cmp reg, reg */
 501 void
 502 OP_1E0 ()
 503 {
 504   unsigned int op0, op1, result, z, s, cy, ov;
 505
 506   /* Compute the result.  */
 507   op0 = State.regs[OP[0]];
 508   op1 = State.regs[OP[1]];
 509   result = op1 - op0;
 510
 511   /* Compute the condition codes.  */
 512   z = (result == 0);
 513   s = (result & 0x80000000);
 514   cy = (result < -op0);
 515   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 516         && (op1 & 0x80000000) != (result & 0x80000000));
 517
 518   /* Set condition codes.  */
 519   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 520   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 521                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 522 }
 523
 524 /* cmp sign_extend(imm5), reg */
 525 void
 526 OP_260 ()
 527 {
 528   unsigned int op0, op1, result, z, s, cy, ov;
 529   int temp;
 530
 531   /* Compute the result.  */
 532   temp = OP[0];
 533   temp = (temp << 27) >> 27;
 534   op0 = temp;
 535   op1 = State.regs[OP[1]];
 536   result = op1 - op0;
 537
 538   /* Compute the condition codes.  */
 539   z = (result == 0);
 540   s = (result & 0x80000000);
 541   cy = (result < -op0);
 542   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 543         && (op1 & 0x80000000) != (result & 0x80000000));
 544
 545   /* Set condition codes.  */
 546   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 547   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 548                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 549 }
 550
 551 /* setf cccc,reg2 */
 552 void
 553 OP_7E0 ()
 554 {
 555   /* Hack alert.  We turn off a bit in op0 since we really only
 556      wanted 4 bits.  */
 557   unsigned int op0, psw, result;
 558
 559   op0 = OP[0] & 0xf;
 560   psw = State.psw;
 561
 562   switch (op0)
 563     {
 564       case 0x0:
 565         result = ((psw & PSW_OV) != 0);
 566         break;
 567       case 0x1:
 568         result = ((psw & PSW_CY) != 0);
 569         break;
 570       case 0x2:
 571         result = ((psw & PSW_Z) != 0);
 572         break;
 573       case 0x3:
 574         result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
 575         break;
 576       case 0x4:
 577         result = ((psw & PSW_S) != 0);
 578         break;
 579       case 0x5:
 580         result = 1;
 581         break;
 582       case 0x6:
 583         result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
 584         break;
 585       case 0x7:
 586         result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
 587                   || ((psw & PSW_Z) != 0)) != 0);
 588         break;
 589       case 0x8:
 590         result = ((psw & PSW_OV) == 0);
 591         break;
 592       case 0x9:
 593         result = ((psw & PSW_CY) == 0);
 594         break;
 595       case 0xa:
 596         result = ((psw & PSW_Z) == 0);
 597         break;
 598       case 0xb:
 599         result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
 600         break;
 601       case 0xc:
 602         result = ((psw & PSW_S) == 0);
 603         break;
 604       case 0xd:
 605         result = ((psw & PSW_SAT) != 0);
 606         break;
 607       case 0xe:
 608         result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
 609         break;
 610       case 0xf:
 611         result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
 612                   || ((psw & PSW_Z) != 0)) == 0);
 613         break;
 614     }
 615
 616   State.regs[OP[1]] = result;
 617 }
 618
 619 /* tst reg,reg */
 620 void
 621 OP_160 ()
 622 {
 623   unsigned int op0, op1, result, z, s, cy, ov;
 624
 625   /* Compute the result.  */
 626   op0 = State.regs[OP[0]];
 627   op1 = State.regs[OP[1]];
 628   result = op0 & op1;
 629
 630   /* Compute the condition codes.  */
 631   z = (result == 0);
 632   s = (result & 0x80000000);
 633
 634   /* Store the condition codes.  */
 635   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 636   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 637 }
 638
 639 void
 640 OP_10720 ()
 641 {
 642 }
 643
 644 void
 645 OP_780 ()
 646 {
 647 }
 648
 649 void
 650 OP_720 ()
 651 {
 652 }
 653
 654 void
 655 OP_60 ()
 656 {
 657 }
 658
 659 void
 660 OP_87C0 ()
 661 {
 662 }
 663
 664 void
 665 OP_300 ()
 666 {
 667 }
 668
 669 /* mov reg, reg */
 670 void
 671 OP_0 ()
 672 {
 673   State.regs[OP[1]] = State.regs[OP[0]];
 674 }
 675
 676 /* mov sign_extend(imm5), reg */
 677 void
 678 OP_200 ()
 679 {
 680   int value = OP[0];
 681
 682   value = (value << 27) >> 27;
 683   State.regs[OP[1]] = value;
 684 }
 685
 686 /* movea sign_extend(imm16), reg, reg  */
 687
 688 void
 689 OP_620 ()
 690 {
 691   int value = OP[0];
 692
 693   value = (value << 16) >> 16;
 694
 695   State.regs[OP[2]] = State.regs[OP[1]] + value;
 696 }
 697
 698 /* movhi imm16, reg, reg */
 699 void
 700 OP_640 ()
 701 {
 702   int value = OP[0];
 703
 704   value = (value & 0xffff) << 16;
 705
 706   State.regs[OP[2]] = State.regs[OP[1]] + value;
 707 }
 708
 709 void
 710 OP_7C0 ()
 711 {
 712 }
 713
 714 void
 715 OP_1687E0 ()
 716 {
 717 }
 718
 719 void
 720 OP_A0 ()
 721 {
 722 }
 723
 724 void
 725 OP_740 ()
 726 {
 727 }
 728
 729 void
 730 OP_80 ()
 731 {
 732 }
 733
 734 /* sar zero_extend(imm5),reg1 */
 735 void
 736 OP_2A0 ()
 737 {
 738   unsigned int op0, op1, result, z, s, cy, ov;
 739
 740   op0 = OP[0] & 0x1f;
 741   op1 = State.regs[OP[1]];
 742   result = (signed)op1 >> op0;
 743
 744   /* Compute the condition codes.  */
 745   z = (result == 0);
 746   s = (result & 0x80000000);
 747   cy = (op1 & (1 << (op0 - 1)));
 748
 749   /* Store the result and condition codes.  */
 750   State.regs[OP[1]] = result;
 751   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 752   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 753                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 754 }
 755
 756 /* sar reg1, reg2 */
 757 void
 758 OP_A007E0 ()
 759 {
 760   unsigned int op0, op1, result, z, s, cy, ov;
 761
 762   op0 = State.regs[OP[0]] & 0x1f;
 763   op1 = State.regs[OP[1]];
 764   result = (signed)op1 >> op0;
 765
 766   /* Compute the condition codes.  */
 767   z = (result == 0);
 768   s = (result & 0x80000000);
 769   cy = (op1 & (1 << (op0 - 1)));
 770
 771   /* Store the result and condition codes.  */
 772   State.regs[OP[1]] = result;
 773   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 774   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 775                 | (cy ? PSW_CY : 0));
 776 }
 777
 778 /* shl zero_extend(imm5),reg1 */
 779 void
 780 OP_2C0 ()
 781 {
 782   unsigned int op0, op1, result, z, s, cy, ov;
 783
 784   op0 = OP[0] & 0x1f;
 785   op1 = State.regs[OP[1]];
 786   result = op1 << op0;
 787
 788   /* Compute the condition codes.  */
 789   z = (result == 0);
 790   s = (result & 0x80000000);
 791   cy = (op1 & (1 << (32 - op0)));
 792
 793   /* Store the result and condition codes.  */
 794   State.regs[OP[1]] = result;
 795   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 796   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 797                 | (cy ? PSW_CY : 0));
 798 }
 799
 800 /* shl reg1, reg2 */
 801 void
 802 OP_C007E0 ()
 803 {
 804   unsigned int op0, op1, result, z, s, cy, ov;
 805
 806   op0 = State.regs[OP[0]] & 0x1f;
 807   op1 = State.regs[OP[1]];
 808   result = op1 << op0;
 809
 810   /* Compute the condition codes.  */
 811   z = (result == 0);
 812   s = (result & 0x80000000);
 813   cy = (op1 & (1 << (32 - op0)));
 814
 815   /* Store the result and condition codes.  */
 816   State.regs[OP[1]] = result;
 817   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 818   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 819                 | (cy ? PSW_CY : 0));
 820 }
 821
 822 /* shr zero_extend(imm5),reg1 */
 823 void
 824 OP_280 ()
 825 {
 826   unsigned int op0, op1, result, z, s, cy, ov;
 827
 828   op0 = OP[0] & 0x1f;
 829   op1 = State.regs[OP[1]];
 830   result = op1 >> op0;
 831
 832   /* Compute the condition codes.  */
 833   z = (result == 0);
 834   s = (result & 0x80000000);
 835   cy = (op1 & (1 << (op0 - 1)));
 836
 837   /* Store the result and condition codes.  */
 838   State.regs[OP[1]] = result;
 839   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 840   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 841                 | (cy ? PSW_CY : 0));
 842 }
 843
 844 /* shr reg1, reg2 */
 845 void
 846 OP_8007E0 ()
 847 {
 848   unsigned int op0, op1, result, z, s, cy, ov;
 849
 850   op0 = State.regs[OP[0]] & 0x1f;
 851   op1 = State.regs[OP[1]];
 852   result = op1 >> op0;
 853
 854   /* Compute the condition codes.  */
 855   z = (result == 0);
 856   s = (result & 0x80000000);
 857   cy = (op1 & (1 << (op0 - 1)));
 858
 859   /* Store the result and condition codes.  */
 860   State.regs[OP[1]] = result;
 861   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 862   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 863                 | (cy ? PSW_CY : 0));
 864 }
 865
 866 void
 867 OP_500 ()
 868 {
 869 }
 870
 871 void
 872 OP_47C0 ()
 873 {
 874 }
 875
 876 /* or reg, reg */
 877 void
 878 OP_100 ()
 879 {
 880   unsigned int op0, op1, result, z, s, cy, ov;
 881
 882   /* Compute the result.  */
 883   op0 = State.regs[OP[0]];
 884   op1 = State.regs[OP[1]];
 885   result = op0 | op1;
 886
 887   /* Compute the condition codes.  */
 888   z = (result == 0);
 889   s = (result & 0x80000000);
 890
 891   /* Store the result and condition codes.  */
 892   State.regs[OP[1]] = result;
 893   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 894   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 895 }
 896
 897 /* ori zero_extend(imm16), reg, reg */
 898 void
 899 OP_680 ()
 900 {
 901   unsigned int op0, op1, result, z, s, cy, ov;
 902
 903   op0 = OP[0] & 0xffff;
 904   op1 = State.regs[OP[1]];
 905   result = op0 | op1;
 906
 907   /* Compute the condition codes.  */
 908   z = (result == 0);
 909   s = (result & 0x80000000);
 910
 911   /* Store the result and condition codes.  */
 912   State.regs[OP[2]] = result;
 913   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 914   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 915 }
 916
 917 /* and reg, reg */
 918 void
 919 OP_140 ()
 920 {
 921   unsigned int op0, op1, result, z, s, cy, ov;
 922
 923   /* Compute the result.  */
 924   op0 = State.regs[OP[0]];
 925   op1 = State.regs[OP[1]];
 926   result = op0 & op1;
 927
 928   /* Compute the condition codes.  */
 929   z = (result == 0);
 930   s = (result & 0x80000000);
 931
 932   /* Store the result and condition codes.  */
 933   State.regs[OP[1]] = result;
 934   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 935   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 936 }
 937
 938 /* andi zero_extend(imm16), reg, reg */
 939 void
 940 OP_6C0 ()
 941 {
 942   unsigned int op0, op1, result, z, s, cy, ov;
 943
 944   op0 = OP[0] & 0xffff;
 945   op1 = State.regs[OP[1]];
 946   result = op0 & op1;
 947
 948   /* Compute the condition codes.  */
 949   z = (result == 0);
 950
 951   /* Store the result and condition codes.  */
 952   State.regs[OP[2]] = result;
 953   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 954   State.psw |= (z ? PSW_Z : 0);
 955 }
 956
 957 /* xor reg, reg */
 958 void
 959 OP_120 ()
 960 {
 961   unsigned int op0, op1, result, z, s, cy, ov;
 962
 963   /* Compute the result.  */
 964   op0 = State.regs[OP[0]];
 965   op1 = State.regs[OP[1]];
 966   result = op0 ^ op1;
 967
 968   /* Compute the condition codes.  */
 969   z = (result == 0);
 970   s = (result & 0x80000000);
 971
 972   /* Store the result and condition codes.  */
 973   State.regs[OP[1]] = result;
 974   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 975   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 976 }
 977
 978 /* xori zero_extend(imm16), reg, reg */
 979 void
 980 OP_6A0 ()
 981 {
 982   unsigned int op0, op1, result, z, s, cy, ov;
 983
 984   op0 = OP[0] & 0xffff;
 985   op1 = State.regs[OP[1]];
 986   result = op0 ^ op1;
 987
 988   /* Compute the condition codes.  */
 989   z = (result == 0);
 990   s = (result & 0x80000000);
 991
 992   /* Store the result and condition codes.  */
 993   State.regs[OP[2]] = result;
 994   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 995   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 996 }
 997
 998 /* not reg1, reg2 */
 999 void
1000 OP_20 ()
1001 {
1002   unsigned int op0, result, z, s, cy, ov;
1003
1004   /* Compute the result.  */
1005   op0 = State.regs[OP[0]];
1006   result = ~op0;
1007
1008   /* Compute the condition codes.  */
1009   z = (result == 0);
1010   s = (result & 0x80000000);
1011
1012   /* Store the result and condition codes.  */
1013   State.regs[OP[1]] = result;
1014   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1015   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1016 }
1017
1018 void
1019 OP_C0 ()
1020 {
1021 }
1022
1023 void
1024 OP_480 ()
1025 {
1026 }
1027
1028 void
1029 OP_380 ()
1030 {
1031 }
1032
1033 void
1034 OP_501 ()
1035 {
1036 }
1037
1038 /* di */
1039 void
1040 OP_16007E0 ()
1041 {
1042   State.psw |= PSW_ID;
1043 }
1044
1045 /* ei */
1046 void
1047 OP_16087E0 ()
1048 {
1049   State.psw &= ~PSW_ID;
1050 }
1051
1052 /* halt, not supported */
1053 void
1054 OP_12007E0 ()
1055 {
1056   abort ();
1057 }
1058
1059 /* reti, not supported */
1060 void
1061 OP_14007E0 ()
1062 {
1063   abort ();
1064 }
1065
1066 /* trap, not supportd */
1067 void
1068 OP_10007E0 ()
1069 {
1070   abort ();
1071 }
1072
1073 /* ldsr, not supported */
1074 void
1075 OP_2007E0 ()
1076 {
1077   abort ();
1078 }
1079
1080 /* stsr, not supported */
1081 void
1082 OP_4007E0 ()
1083 {
1084   abort ();
1085 }
1086
1087 void
1088 OP_400 ()
1089 {
1090 }
1091
1092 void
1093 OP_700 ()
1094 {
1095 }
1096