4 #include "sys/syscall.h"
36 static void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
37 static void trace_output
PARAMS ((enum op_types result
));
38 static int init_text_p
= 0;
39 static asection
*text
;
40 static bfd_vma text_start
;
41 static bfd_vma text_end
;
44 #ifndef SIZE_INSTRUCTION
45 #define SIZE_INSTRUCTION 6
49 #define SIZE_OPERANDS 16
53 #define SIZE_VALUES 11
57 #define SIZE_LOCATION 40
61 trace_input (name
, type
, size
)
73 const char *functionname
;
74 unsigned int linenumber
;
76 if ((v850_debug
& DEBUG_TRACE
) == 0)
83 for (s
= exec_bfd
->sections
; s
; s
= s
->next
)
84 if (strcmp (bfd_get_section_name (exec_bfd
, s
), ".text") == 0)
87 text_start
= bfd_get_section_vma (exec_bfd
, s
);
88 text_end
= text_start
+ bfd_section_size (exec_bfd
, s
);
93 if (text
&& PC
>= text_start
&& PC
< text_end
)
95 filename
= (const char *)0;
96 functionname
= (const char *)0;
98 if (bfd_find_nearest_line (exec_bfd
, text
, (struct symbol_cache_entry
**)0, PC
- text_start
,
99 &filename
, &functionname
, &linenumber
))
104 sprintf (p
, "Line %5d ", linenumber
);
110 sprintf (p
, "Func %s ", functionname
);
115 char *q
= (char *) strrchr (filename
, '/');
116 sprintf (p
, "File %s ", (q
) ? q
+1 : filename
);
125 (*v850_callback
->printf_filtered
) (v850_callback
, "0x%.8x: %-*.*s %-*s",
127 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
128 SIZE_INSTRUCTION
, name
);
135 strcpy (buf
, "unknown");
139 sprintf (buf
, "%d", OP
[0]);
143 sprintf (buf
, "r%d", OP
[0]);
148 case OP_REG_REG_MOVE
:
149 sprintf (buf
, "r%d,r%d", OP
[0], OP
[1]);
154 case OP_IMM_REG_MOVE
:
155 sprintf (buf
, "%d,r%d", OP
[0], OP
[1]);
159 sprintf (buf
, "%d", SEXT9 (OP
[0]));
163 sprintf (buf
, "%d[r30],r%d", OP
[1] * size
, OP
[0]);
167 sprintf (buf
, "r%d,%d[r30]", OP
[0], OP
[1] * size
);
171 sprintf (buf
, "%d[r%d],r%d", SEXT16 (OP
[2]) & ~0x1, OP
[0], OP
[1]);
175 sprintf (buf
, "r%d,%d[r%d]", OP
[1], SEXT16 (OP
[2] & ~0x1), OP
[0]);
179 sprintf (buf
, "%d,r%d", SEXT22 (OP
[0]), OP
[1]);
183 sprintf (buf
, "%d,r%d,r%d", SEXT16 (OP
[0]), OP
[1], OP
[2]);
186 case OP_UIMM_REG_REG
:
187 sprintf (buf
, "%d,r%d,r%d", OP
[0] & 0xffff, OP
[1], OP
[2]);
191 sprintf (buf
, "%d,%d[r%d]", OP
[1] & 0x7, SEXT16 (OP
[2]), OP
[0]);
197 default: cond
= "?"; break;
198 case 0x0: cond
= "v"; break;
199 case 0x1: cond
= "c"; break;
200 case 0x2: cond
= "z"; break;
201 case 0x3: cond
= "nh"; break;
202 case 0x4: cond
= "s"; break;
203 case 0x5: cond
= "t"; break;
204 case 0x6: cond
= "lt"; break;
205 case 0x7: cond
= "le"; break;
206 case 0x8: cond
= "nv"; break;
207 case 0x9: cond
= "nc"; break;
208 case 0xa: cond
= "nz"; break;
209 case 0xb: cond
= "h"; break;
210 case 0xc: cond
= "ns"; break;
211 case 0xd: cond
= "sa"; break;
212 case 0xe: cond
= "ge"; break;
213 case 0xf: cond
= "gt"; break;
216 sprintf (buf
, "%s,r%d", cond
, OP
[1]);
225 sprintf (buf
, "r%d,s%d", OP
[0], OP
[1]);
229 if ((v850_debug
& DEBUG_VALUES
) == 0)
231 (*v850_callback
->printf_filtered
) (v850_callback
, "%s\n", buf
);
235 (*v850_callback
->printf_filtered
) (v850_callback
, "%-*s", SIZE_OPERANDS
, buf
);
246 case OP_REG_REG_MOVE
:
247 values
[0] = State
.regs
[OP
[0]];
253 values
[0] = State
.regs
[OP
[1]];
254 values
[1] = State
.regs
[OP
[0]];
260 values
[0] = SEXT5 (OP
[0]);
265 case OP_IMM_REG_MOVE
:
266 values
[0] = SEXT5 (OP
[0]);
271 values
[0] = State
.pc
;
272 values
[1] = SEXT9 (OP
[0]);
273 values
[2] = State
.sregs
[5];
278 values
[0] = OP
[1] * size
;
279 values
[1] = State
.regs
[30];
284 values
[0] = State
.regs
[OP
[0]];
285 values
[1] = OP
[1] * size
;
286 values
[2] = State
.regs
[30];
291 values
[0] = SEXT16 (OP
[2]);
292 values
[1] = State
.regs
[OP
[0]];
297 values
[0] = State
.regs
[OP
[1]];
298 values
[1] = SEXT16 (OP
[2]);
299 values
[2] = State
.regs
[OP
[0]];
304 values
[0] = SEXT22 (OP
[0]);
305 values
[1] = State
.pc
;
310 values
[0] = SEXT16 (OP
[0]) << size
;
311 values
[1] = State
.regs
[OP
[1]];
315 case OP_UIMM_REG_REG
:
316 values
[0] = (OP
[0] & 0xffff) << size
;
317 values
[1] = State
.regs
[OP
[1]];
326 values
[0] = State
.sregs
[5];
335 values
[0] = State
.regs
[OP
[0]];
340 values
[0] = State
.sregs
[OP
[1]];
344 for (i
= 0; i
< num_values
; i
++)
345 (*v850_callback
->printf_filtered
) (v850_callback
, "%*s0x%.8lx", SIZE_VALUES
- 10, "", values
[i
]);
348 (*v850_callback
->printf_filtered
) (v850_callback
, "%*s", SIZE_VALUES
, "");
353 trace_output (result
)
354 enum op_types result
;
356 if ((v850_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
376 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
377 (unsigned long)State
.regs
[OP
[0]]);
381 case OP_REG_REG_MOVE
:
383 case OP_IMM_REG_MOVE
:
386 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
387 (unsigned long)State
.regs
[OP
[1]]);
391 case OP_UIMM_REG_REG
:
392 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
393 (unsigned long)State
.regs
[OP
[2]]);
398 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
399 (unsigned long)State
.regs
[OP
[1]]);
403 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
404 (unsigned long)State
.sregs
[OP
[1]]);
408 (*v850_callback
->printf_filtered
) (v850_callback
, "\n");
413 #define trace_input(NAME, IN1, IN2)
414 #define trace_output(RESULT)
425 trace_input ("sld.b", OP_LOAD16
, 1);
429 result
= load_mem (State
.regs
[30] + op2
, 1);
430 State
.regs
[OP
[0]] = SEXT8 (result
);
431 trace_output (OP_LOAD16
);
441 trace_input ("sld.h", OP_LOAD16
, 2);
445 result
= load_mem (State
.regs
[30] + op2
, 2);
446 State
.regs
[OP
[0]] = SEXT16 (result
);
447 trace_output (OP_LOAD16
);
457 trace_input ("sld.w", OP_LOAD16
, 4);
461 result
= load_mem (State
.regs
[30] + op2
, 4);
462 State
.regs
[OP
[0]] = result
;
463 trace_output (OP_LOAD16
);
470 unsigned int op0
, op1
;
473 trace_input ("sst.b", OP_STORE16
, 1);
474 op0
= State
.regs
[OP
[0]];
478 store_mem (State
.regs
[30] + op1
, 1, op0
);
479 trace_output (OP_STORE16
);
486 unsigned int op0
, op1
;
489 trace_input ("sst.h", OP_STORE16
, 2);
490 op0
= State
.regs
[OP
[0]];
494 store_mem (State
.regs
[30] + op1
, 2, op0
);
495 trace_output (OP_STORE16
);
502 unsigned int op0
, op1
;
505 trace_input ("sst.w", OP_STORE16
, 4);
506 op0
= State
.regs
[OP
[0]];
510 store_mem (State
.regs
[30] + op1
, 4, op0
);
511 trace_output (OP_STORE16
);
518 unsigned int op0
, op2
;
521 trace_input ("ld.b", OP_LOAD32
, 1);
522 op0
= State
.regs
[OP
[0]];
523 temp
= SEXT16 (OP
[2]);
525 result
= load_mem (op0
+ op2
, 1);
526 State
.regs
[OP
[1]] = SEXT8 (result
);
527 trace_output (OP_LOAD32
);
534 unsigned int op0
, op2
;
537 trace_input ("ld.h", OP_LOAD32
, 2);
538 op0
= State
.regs
[OP
[0]];
539 temp
= SEXT16 (OP
[2]);
542 result
= load_mem (op0
+ op2
, 2);
543 State
.regs
[OP
[1]] = SEXT16 (result
);
544 trace_output (OP_LOAD32
);
551 unsigned int op0
, op2
;
554 trace_input ("ld.w", OP_LOAD32
, 4);
555 op0
= State
.regs
[OP
[0]];
556 temp
= SEXT16 (OP
[2]);
559 result
= load_mem (op0
+ op2
, 4);
560 State
.regs
[OP
[1]] = result
;
561 trace_output (OP_LOAD32
);
568 unsigned int op0
, op1
, op2
;
571 trace_input ("st.b", OP_STORE32
, 1);
572 op0
= State
.regs
[OP
[0]];
573 op1
= State
.regs
[OP
[1]];
574 temp
= SEXT16 (OP
[2]);
576 store_mem (op0
+ op2
, 1, op1
);
577 trace_output (OP_STORE32
);
584 unsigned int op0
, op1
, op2
;
587 trace_input ("st.h", OP_STORE32
, 2);
588 op0
= State
.regs
[OP
[0]];
589 op1
= State
.regs
[OP
[1]];
590 temp
= SEXT16 (OP
[2] & ~0x1);
592 store_mem (op0
+ op2
, 2, op1
);
593 trace_output (OP_STORE32
);
600 unsigned int op0
, op1
, op2
;
603 trace_input ("st.w", OP_STORE32
, 4);
604 op0
= State
.regs
[OP
[0]];
605 op1
= State
.regs
[OP
[1]];
606 temp
= SEXT16 (OP
[2] & ~0x1);
608 store_mem (op0
+ op2
, 4, op1
);
609 trace_output (OP_STORE32
);
619 trace_input ("bv", OP_COND_BR
, 0);
621 psw
= State
.sregs
[5];
623 if ((psw
& PSW_OV
) != 0)
627 trace_output (OP_COND_BR
);
637 trace_input ("bl", OP_COND_BR
, 0);
639 psw
= State
.sregs
[5];
641 if ((psw
& PSW_CY
) != 0)
645 trace_output (OP_COND_BR
);
655 trace_input ("be", OP_COND_BR
, 0);
657 psw
= State
.sregs
[5];
659 if ((psw
& PSW_Z
) != 0)
663 trace_output (OP_COND_BR
);
673 trace_input ("bnh", OP_COND_BR
, 0);
675 psw
= State
.sregs
[5];
677 if ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0)
681 trace_output (OP_COND_BR
);
691 trace_input ("bn", OP_COND_BR
, 0);
693 psw
= State
.sregs
[5];
695 if ((psw
& PSW_S
) != 0)
699 trace_output (OP_COND_BR
);
709 trace_input ("br", OP_COND_BR
, 0);
712 trace_output (OP_COND_BR
);
722 trace_input ("blt", OP_COND_BR
, 0);
724 psw
= State
.sregs
[5];
726 if ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0)
730 trace_output (OP_COND_BR
);
740 trace_input ("ble", OP_COND_BR
, 0);
742 psw
= State
.sregs
[5];
744 if ((((psw
& PSW_Z
) != 0)
745 || (((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))) != 0)
749 trace_output (OP_COND_BR
);
759 trace_input ("bnv", OP_COND_BR
, 0);
761 psw
= State
.sregs
[5];
763 if ((psw
& PSW_OV
) == 0)
767 trace_output (OP_COND_BR
);
777 trace_input ("bnl", OP_COND_BR
, 0);
779 psw
= State
.sregs
[5];
781 if ((psw
& PSW_CY
) == 0)
785 trace_output (OP_COND_BR
);
795 trace_input ("bne", OP_COND_BR
, 0);
797 psw
= State
.sregs
[5];
799 if ((psw
& PSW_Z
) == 0)
803 trace_output (OP_COND_BR
);
813 trace_input ("bh", OP_COND_BR
, 0);
815 psw
= State
.sregs
[5];
817 if ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0)
821 trace_output (OP_COND_BR
);
831 trace_input ("bp", OP_COND_BR
, 0);
833 psw
= State
.sregs
[5];
835 if ((psw
& PSW_S
) == 0)
839 trace_output (OP_COND_BR
);
849 trace_input ("bsa", OP_COND_BR
, 0);
851 psw
= State
.sregs
[5];
853 if ((psw
& PSW_SAT
) != 0)
857 trace_output (OP_COND_BR
);
867 trace_input ("bge", OP_COND_BR
, 0);
869 psw
= State
.sregs
[5];
871 if ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0)
875 trace_output (OP_COND_BR
);
885 trace_input ("bgt", OP_COND_BR
, 0);
887 psw
= State
.sregs
[5];
889 if ((((psw
& PSW_Z
) != 0)
890 || (((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))) == 0)
894 trace_output (OP_COND_BR
);
901 /* interp.c will bump this by +2, so correct for it here. */
902 trace_input ("jmp", OP_REG
, 0);
903 State
.pc
= State
.regs
[OP
[0]] - 2;
904 trace_output (OP_REG
);
907 /* jarl disp22, reg */
911 unsigned int op0
, opc
;
914 trace_input ("jarl", OP_JUMP
, 0);
915 temp
= SEXT22 (OP
[0]);
921 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
923 State
.regs
[OP
[1]] = opc
+ 4;
924 trace_output (OP_JUMP
);
931 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
933 trace_input ("add", OP_REG_REG
, 0);
934 /* Compute the result. */
935 op0
= State
.regs
[OP
[0]];
936 op1
= State
.regs
[OP
[1]];
939 /* Compute the condition codes. */
941 s
= (result
& 0x80000000);
942 cy
= (result
< op0
|| result
< op1
);
943 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
944 && (op0
& 0x80000000) != (result
& 0x80000000));
946 /* Store the result and condition codes. */
947 State
.regs
[OP
[1]] = result
;
948 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
949 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
950 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
951 trace_output (OP_REG_REG
);
954 /* add sign_extend(imm5), reg */
958 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
961 trace_input ("add", OP_IMM_REG
, 0);
963 /* Compute the result. */
964 temp
= SEXT5 (OP
[0]);
966 op1
= State
.regs
[OP
[1]];
969 /* Compute the condition codes. */
971 s
= (result
& 0x80000000);
972 cy
= (result
< op0
|| result
< op1
);
973 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
974 && (op0
& 0x80000000) != (result
& 0x80000000));
976 /* Store the result and condition codes. */
977 State
.regs
[OP
[1]] = result
;
978 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
979 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
980 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
981 trace_output (OP_IMM_REG
);
984 /* addi sign_extend(imm16), reg, reg */
988 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
991 trace_input ("addi", OP_IMM_REG_REG
, 0);
993 /* Compute the result. */
994 temp
= SEXT16 (OP
[0]);
996 op1
= State
.regs
[OP
[1]];
999 /* Compute the condition codes. */
1001 s
= (result
& 0x80000000);
1002 cy
= (result
< op0
|| result
< op1
);
1003 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1004 && (op0
& 0x80000000) != (result
& 0x80000000));
1006 /* Store the result and condition codes. */
1007 State
.regs
[OP
[2]] = result
;
1008 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1009 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1010 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1011 trace_output (OP_IMM_REG_REG
);
1014 /* sub reg1, reg2 */
1018 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1020 trace_input ("sub", OP_REG_REG
, 0);
1021 /* Compute the result. */
1022 op0
= State
.regs
[OP
[0]];
1023 op1
= State
.regs
[OP
[1]];
1026 /* Compute the condition codes. */
1028 s
= (result
& 0x80000000);
1030 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1031 && (op1
& 0x80000000) != (result
& 0x80000000));
1033 /* Store the result and condition codes. */
1034 State
.regs
[OP
[1]] = result
;
1035 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1036 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1037 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1038 trace_output (OP_REG_REG
);
1041 /* subr reg1, reg2 */
1045 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1047 trace_input ("subr", OP_REG_REG
, 0);
1048 /* Compute the result. */
1049 op0
= State
.regs
[OP
[0]];
1050 op1
= State
.regs
[OP
[1]];
1053 /* Compute the condition codes. */
1055 s
= (result
& 0x80000000);
1057 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
1058 && (op0
& 0x80000000) != (result
& 0x80000000));
1060 /* Store the result and condition codes. */
1061 State
.regs
[OP
[1]] = result
;
1062 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1063 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1064 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1065 trace_output (OP_REG_REG
);
1068 /* mulh reg1, reg2 */
1072 trace_input ("mulh", OP_REG_REG
, 0);
1073 State
.regs
[OP
[1]] = ((State
.regs
[OP
[1]] & 0xffff)
1074 * (State
.regs
[OP
[0]] & 0xffff));
1075 trace_output (OP_REG_REG
);
1078 /* mulh sign_extend(imm5), reg2
1084 int value
= SEXT5 (OP
[0]);
1086 trace_input ("mulh", OP_IMM_REG
, 0);
1087 State
.regs
[OP
[1]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
1088 trace_output (OP_IMM_REG
);
1091 /* mulhi imm16, reg1, reg2 */
1095 int value
= OP
[0] & 0xffff;
1097 trace_input ("mulhi", OP_IMM_REG_REG
, 0);
1098 State
.regs
[OP
[2]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
1099 trace_output (OP_IMM_REG_REG
);
1102 /* divh reg1, reg2 */
1106 unsigned int op0
, op1
, result
, ov
, s
, z
;
1109 trace_input ("divh", OP_REG_REG
, 0);
1111 /* Compute the result. */
1112 temp
= SEXT16 (State
.regs
[OP
[0]]);
1114 op1
= State
.regs
[OP
[1]];
1116 if (op0
== 0xffffffff && op1
== 0x80000000)
1118 result
= 0x80000000;
1132 /* Compute the condition codes. */
1134 s
= (result
& 0x80000000);
1136 /* Store the result and condition codes. */
1137 State
.regs
[OP
[1]] = result
;
1138 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1139 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1140 | (ov
? PSW_OV
: 0));
1141 trace_output (OP_REG_REG
);
1148 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1150 trace_input ("cmp", OP_REG_REG_CMP
, 0);
1151 /* Compute the result. */
1152 op0
= State
.regs
[OP
[0]];
1153 op1
= State
.regs
[OP
[1]];
1156 /* Compute the condition codes. */
1158 s
= (result
& 0x80000000);
1160 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1161 && (op1
& 0x80000000) != (result
& 0x80000000));
1163 /* Set condition codes. */
1164 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1165 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1166 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1167 trace_output (OP_REG_REG_CMP
);
1170 /* cmp sign_extend(imm5), reg */
1174 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1177 /* Compute the result. */
1178 trace_input ("cmp", OP_IMM_REG_CMP
, 0);
1179 temp
= SEXT5 (OP
[0]);
1181 op1
= State
.regs
[OP
[1]];
1184 /* Compute the condition codes. */
1186 s
= (result
& 0x80000000);
1188 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1189 && (op1
& 0x80000000) != (result
& 0x80000000));
1191 /* Set condition codes. */
1192 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1193 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1194 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1195 trace_output (OP_IMM_REG_CMP
);
1198 /* setf cccc,reg2 */
1202 /* Hack alert. We turn off a bit in op0 since we really only
1204 unsigned int op0
, psw
, result
= 0;
1206 trace_input ("setf", OP_EX1
, 0);
1208 psw
= State
.sregs
[5];
1213 result
= ((psw
& PSW_OV
) != 0);
1216 result
= ((psw
& PSW_CY
) != 0);
1219 result
= ((psw
& PSW_Z
) != 0);
1222 result
= ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0);
1225 result
= ((psw
& PSW_S
) != 0);
1231 result
= ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0);
1234 result
= (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))
1235 || ((psw
& PSW_Z
) != 0)) != 0);
1238 result
= ((psw
& PSW_OV
) == 0);
1241 result
= ((psw
& PSW_CY
) == 0);
1244 result
= ((psw
& PSW_Z
) == 0);
1247 result
= ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0);
1250 result
= ((psw
& PSW_S
) == 0);
1253 result
= ((psw
& PSW_SAT
) != 0);
1256 result
= ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0);
1259 result
= (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))
1260 || ((psw
& PSW_Z
) != 0)) == 0);
1264 State
.regs
[OP
[1]] = result
;
1265 trace_output (OP_EX1
);
1268 /* satadd reg,reg */
1272 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1274 trace_input ("satadd", OP_REG_REG
, 0);
1275 /* Compute the result. */
1276 op0
= State
.regs
[OP
[0]];
1277 op1
= State
.regs
[OP
[1]];
1280 /* Compute the condition codes. */
1282 s
= (result
& 0x80000000);
1283 cy
= (result
< op0
|| result
< op1
);
1284 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1285 && (op0
& 0x80000000) != (result
& 0x80000000));
1288 /* Store the result and condition codes. */
1289 State
.regs
[OP
[1]] = result
;
1290 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1291 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1292 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1293 | (sat
? PSW_SAT
: 0));
1295 /* Handle saturated results. */
1297 State
.regs
[OP
[1]] = 0x80000000;
1299 State
.regs
[OP
[1]] = 0x7fffffff;
1300 trace_output (OP_REG_REG
);
1303 /* satadd sign_extend(imm5), reg */
1307 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1311 trace_input ("satadd", OP_IMM_REG
, 0);
1313 /* Compute the result. */
1314 temp
= SEXT5 (OP
[0]);
1316 op1
= State
.regs
[OP
[1]];
1319 /* Compute the condition codes. */
1321 s
= (result
& 0x80000000);
1322 cy
= (result
< op0
|| result
< op1
);
1323 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1324 && (op0
& 0x80000000) != (result
& 0x80000000));
1327 /* Store the result and condition codes. */
1328 State
.regs
[OP
[1]] = result
;
1329 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1330 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1331 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1332 | (sat
? PSW_SAT
: 0));
1334 /* Handle saturated results. */
1336 State
.regs
[OP
[1]] = 0x80000000;
1338 State
.regs
[OP
[1]] = 0x7fffffff;
1339 trace_output (OP_IMM_REG
);
1342 /* satsub reg1, reg2 */
1346 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1348 trace_input ("satsub", OP_REG_REG
, 0);
1350 /* Compute the result. */
1351 op0
= State
.regs
[OP
[0]];
1352 op1
= State
.regs
[OP
[1]];
1355 /* Compute the condition codes. */
1357 s
= (result
& 0x80000000);
1359 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1360 && (op1
& 0x80000000) != (result
& 0x80000000));
1363 /* Store the result and condition codes. */
1364 State
.regs
[OP
[1]] = result
;
1365 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1366 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1367 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1368 | (sat
? PSW_SAT
: 0));
1370 /* Handle saturated results. */
1372 State
.regs
[OP
[1]] = 0x80000000;
1374 State
.regs
[OP
[1]] = 0x7fffffff;
1375 trace_output (OP_REG_REG
);
1378 /* satsubi sign_extend(imm16), reg */
1382 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1385 trace_input ("satsubi", OP_IMM_REG
, 0);
1387 /* Compute the result. */
1388 temp
= SEXT16 (OP
[0]);
1390 op1
= State
.regs
[OP
[1]];
1393 /* Compute the condition codes. */
1395 s
= (result
& 0x80000000);
1397 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1398 && (op1
& 0x80000000) != (result
& 0x80000000));
1401 /* Store the result and condition codes. */
1402 State
.regs
[OP
[1]] = result
;
1403 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1404 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1405 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1406 | (sat
? PSW_SAT
: 0));
1408 /* Handle saturated results. */
1410 State
.regs
[OP
[1]] = 0x80000000;
1412 State
.regs
[OP
[1]] = 0x7fffffff;
1413 trace_output (OP_IMM_REG
);
1416 /* satsubr reg,reg */
1420 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1422 trace_input ("satsubr", OP_REG_REG
, 0);
1424 /* Compute the result. */
1425 op0
= State
.regs
[OP
[0]];
1426 op1
= State
.regs
[OP
[1]];
1429 /* Compute the condition codes. */
1431 s
= (result
& 0x80000000);
1432 cy
= (result
< op0
);
1433 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1434 && (op1
& 0x80000000) != (result
& 0x80000000));
1437 /* Store the result and condition codes. */
1438 State
.regs
[OP
[1]] = result
;
1439 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1440 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1441 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1442 | (sat
? PSW_SAT
: 0));
1444 /* Handle saturated results. */
1446 State
.regs
[OP
[1]] = 0x80000000;
1448 State
.regs
[OP
[1]] = 0x7fffffff;
1449 trace_output (OP_REG_REG
);
1456 unsigned int op0
, op1
, result
, z
, s
;
1458 trace_input ("tst", OP_REG_REG_CMP
, 0);
1460 /* Compute the result. */
1461 op0
= State
.regs
[OP
[0]];
1462 op1
= State
.regs
[OP
[1]];
1465 /* Compute the condition codes. */
1467 s
= (result
& 0x80000000);
1469 /* Store the condition codes. */
1470 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1471 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1472 trace_output (OP_REG_REG_CMP
);
1479 trace_input ("mov", OP_REG_REG_MOVE
, 0);
1480 State
.regs
[OP
[1]] = State
.regs
[OP
[0]];
1481 trace_output (OP_REG_REG_MOVE
);
1484 /* mov sign_extend(imm5), reg */
1488 int value
= SEXT5 (OP
[0]);
1490 trace_input ("mov", OP_IMM_REG_MOVE
, 0);
1491 State
.regs
[OP
[1]] = value
;
1492 trace_output (OP_IMM_REG_MOVE
);
1495 /* movea sign_extend(imm16), reg, reg */
1500 int value
= SEXT16 (OP
[0]);
1502 trace_input ("movea", OP_IMM_REG_REG
, 0);
1503 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
1504 trace_output (OP_IMM_REG_REG
);
1507 /* movhi imm16, reg, reg */
1511 uint32 value
= (OP
[0] & 0xffff) << 16;
1513 trace_input ("movhi", OP_UIMM_REG_REG
, 16);
1514 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
1515 trace_output (OP_UIMM_REG_REG
);
1518 /* sar zero_extend(imm5),reg1 */
1522 unsigned int op0
, op1
, result
, z
, s
, cy
;
1524 trace_input ("sar", OP_IMM_REG
, 0);
1526 op1
= State
.regs
[OP
[1]];
1527 result
= (signed)op1
>> op0
;
1529 /* Compute the condition codes. */
1531 s
= (result
& 0x80000000);
1532 cy
= (op1
& (1 << (op0
- 1)));
1534 /* Store the result and condition codes. */
1535 State
.regs
[OP
[1]] = result
;
1536 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1537 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1538 | (cy
? PSW_CY
: 0));
1539 trace_output (OP_IMM_REG
);
1542 /* sar reg1, reg2 */
1546 unsigned int op0
, op1
, result
, z
, s
, cy
;
1548 trace_input ("sar", OP_REG_REG
, 0);
1549 op0
= State
.regs
[OP
[0]] & 0x1f;
1550 op1
= State
.regs
[OP
[1]];
1551 result
= (signed)op1
>> op0
;
1553 /* Compute the condition codes. */
1555 s
= (result
& 0x80000000);
1556 cy
= (op1
& (1 << (op0
- 1)));
1558 /* Store the result and condition codes. */
1559 State
.regs
[OP
[1]] = result
;
1560 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1561 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1562 | (cy
? PSW_CY
: 0));
1563 trace_output (OP_REG_REG
);
1566 /* shl zero_extend(imm5),reg1 */
1570 unsigned int op0
, op1
, result
, z
, s
, cy
;
1572 trace_input ("shl", OP_IMM_REG
, 0);
1574 op1
= State
.regs
[OP
[1]];
1575 result
= op1
<< op0
;
1577 /* Compute the condition codes. */
1579 s
= (result
& 0x80000000);
1580 cy
= (op1
& (1 << (32 - op0
)));
1582 /* Store the result and condition codes. */
1583 State
.regs
[OP
[1]] = result
;
1584 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1585 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1586 | (cy
? PSW_CY
: 0));
1587 trace_output (OP_IMM_REG
);
1590 /* shl reg1, reg2 */
1594 unsigned int op0
, op1
, result
, z
, s
, cy
;
1596 trace_input ("shl", OP_REG_REG
, 0);
1597 op0
= State
.regs
[OP
[0]] & 0x1f;
1598 op1
= State
.regs
[OP
[1]];
1599 result
= op1
<< op0
;
1601 /* Compute the condition codes. */
1603 s
= (result
& 0x80000000);
1604 cy
= (op1
& (1 << (32 - op0
)));
1606 /* Store the result and condition codes. */
1607 State
.regs
[OP
[1]] = result
;
1608 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1609 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1610 | (cy
? PSW_CY
: 0));
1611 trace_output (OP_REG_REG
);
1614 /* shr zero_extend(imm5),reg1 */
1618 unsigned int op0
, op1
, result
, z
, s
, cy
;
1620 trace_input ("shr", OP_IMM_REG
, 0);
1622 op1
= State
.regs
[OP
[1]];
1623 result
= op1
>> op0
;
1625 /* Compute the condition codes. */
1627 s
= (result
& 0x80000000);
1628 cy
= (op1
& (1 << (op0
- 1)));
1630 /* Store the result and condition codes. */
1631 State
.regs
[OP
[1]] = result
;
1632 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1633 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1634 | (cy
? PSW_CY
: 0));
1635 trace_output (OP_IMM_REG
);
1638 /* shr reg1, reg2 */
1642 unsigned int op0
, op1
, result
, z
, s
, cy
;
1644 trace_input ("shr", OP_REG_REG
, 0);
1645 op0
= State
.regs
[OP
[0]] & 0x1f;
1646 op1
= State
.regs
[OP
[1]];
1647 result
= op1
>> op0
;
1649 /* Compute the condition codes. */
1651 s
= (result
& 0x80000000);
1652 cy
= (op1
& (1 << (op0
- 1)));
1654 /* Store the result and condition codes. */
1655 State
.regs
[OP
[1]] = result
;
1656 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1657 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1658 | (cy
? PSW_CY
: 0));
1659 trace_output (OP_REG_REG
);
1666 unsigned int op0
, op1
, result
, z
, s
;
1668 trace_input ("or", OP_REG_REG
, 0);
1670 /* Compute the result. */
1671 op0
= State
.regs
[OP
[0]];
1672 op1
= State
.regs
[OP
[1]];
1675 /* Compute the condition codes. */
1677 s
= (result
& 0x80000000);
1679 /* Store the result and condition codes. */
1680 State
.regs
[OP
[1]] = result
;
1681 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1682 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1683 trace_output (OP_REG_REG
);
1686 /* ori zero_extend(imm16), reg, reg */
1690 unsigned int op0
, op1
, result
, z
, s
;
1692 trace_input ("ori", OP_UIMM_REG_REG
, 0);
1693 op0
= OP
[0] & 0xffff;
1694 op1
= State
.regs
[OP
[1]];
1697 /* Compute the condition codes. */
1699 s
= (result
& 0x80000000);
1701 /* Store the result and condition codes. */
1702 State
.regs
[OP
[2]] = result
;
1703 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1704 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1705 trace_output (OP_UIMM_REG_REG
);
1712 unsigned int op0
, op1
, result
, z
, s
;
1714 trace_input ("and", OP_REG_REG
, 0);
1716 /* Compute the result. */
1717 op0
= State
.regs
[OP
[0]];
1718 op1
= State
.regs
[OP
[1]];
1721 /* Compute the condition codes. */
1723 s
= (result
& 0x80000000);
1725 /* Store the result and condition codes. */
1726 State
.regs
[OP
[1]] = result
;
1727 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1728 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1729 trace_output (OP_REG_REG
);
1732 /* andi zero_extend(imm16), reg, reg */
1736 unsigned int op0
, op1
, result
, z
;
1738 trace_input ("andi", OP_UIMM_REG_REG
, 0);
1739 op0
= OP
[0] & 0xffff;
1740 op1
= State
.regs
[OP
[1]];
1743 /* Compute the condition codes. */
1746 /* Store the result and condition codes. */
1747 State
.regs
[OP
[2]] = result
;
1748 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1749 State
.sregs
[5] |= (z
? PSW_Z
: 0);
1750 trace_output (OP_UIMM_REG_REG
);
1757 unsigned int op0
, op1
, result
, z
, s
;
1759 trace_input ("xor", OP_REG_REG
, 0);
1761 /* Compute the result. */
1762 op0
= State
.regs
[OP
[0]];
1763 op1
= State
.regs
[OP
[1]];
1766 /* Compute the condition codes. */
1768 s
= (result
& 0x80000000);
1770 /* Store the result and condition codes. */
1771 State
.regs
[OP
[1]] = result
;
1772 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1773 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1774 trace_output (OP_REG_REG
);
1777 /* xori zero_extend(imm16), reg, reg */
1781 unsigned int op0
, op1
, result
, z
, s
;
1783 trace_input ("xori", OP_UIMM_REG_REG
, 0);
1784 op0
= OP
[0] & 0xffff;
1785 op1
= State
.regs
[OP
[1]];
1788 /* Compute the condition codes. */
1790 s
= (result
& 0x80000000);
1792 /* Store the result and condition codes. */
1793 State
.regs
[OP
[2]] = result
;
1794 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1795 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1796 trace_output (OP_UIMM_REG_REG
);
1799 /* not reg1, reg2 */
1803 unsigned int op0
, result
, z
, s
;
1805 trace_input ("not", OP_REG_REG_MOVE
, 0);
1806 /* Compute the result. */
1807 op0
= State
.regs
[OP
[0]];
1810 /* Compute the condition codes. */
1812 s
= (result
& 0x80000000);
1814 /* Store the result and condition codes. */
1815 State
.regs
[OP
[1]] = result
;
1816 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1817 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1818 trace_output (OP_REG_REG_MOVE
);
1825 unsigned int op0
, op1
, op2
;
1828 trace_input ("set1", OP_BIT
, 0);
1829 op0
= State
.regs
[OP
[0]];
1831 temp
= SEXT16 (OP
[2]);
1833 temp
= load_mem (op0
+ op2
, 1);
1834 State
.sregs
[5] &= ~PSW_Z
;
1835 if ((temp
& (1 << op1
)) == 0)
1836 State
.sregs
[5] |= PSW_Z
;
1838 store_mem (op0
+ op2
, 1, temp
);
1839 trace_output (OP_BIT
);
1846 unsigned int op0
, op1
, op2
;
1849 trace_input ("not1", OP_BIT
, 0);
1850 op0
= State
.regs
[OP
[0]];
1852 temp
= SEXT16 (OP
[2]);
1854 temp
= load_mem (op0
+ op2
, 1);
1855 State
.sregs
[5] &= ~PSW_Z
;
1856 if ((temp
& (1 << op1
)) == 0)
1857 State
.sregs
[5] |= PSW_Z
;
1859 store_mem (op0
+ op2
, 1, temp
);
1860 trace_output (OP_BIT
);
1867 unsigned int op0
, op1
, op2
;
1870 trace_input ("clr1", OP_BIT
, 0);
1871 op0
= State
.regs
[OP
[0]];
1873 temp
= SEXT16 (OP
[2]);
1875 temp
= load_mem (op0
+ op2
, 1);
1876 State
.sregs
[5] &= ~PSW_Z
;
1877 if ((temp
& (1 << op1
)) == 0)
1878 State
.sregs
[5] |= PSW_Z
;
1879 temp
&= ~(1 << op1
);
1880 store_mem (op0
+ op2
, 1, temp
);
1881 trace_output (OP_BIT
);
1888 unsigned int op0
, op1
, op2
;
1891 trace_input ("tst1", OP_BIT
, 0);
1892 op0
= State
.regs
[OP
[0]];
1894 temp
= SEXT16 (OP
[2]);
1896 temp
= load_mem (op0
+ op2
, 1);
1897 State
.sregs
[5] &= ~PSW_Z
;
1898 if ((temp
& (1 << op1
)) == 0)
1899 State
.sregs
[5] |= PSW_Z
;
1900 trace_output (OP_BIT
);
1907 State
.exception
= SIGTRAP
;
1915 trace_input ("di", OP_NONE
, 0);
1916 State
.sregs
[5] |= PSW_ID
;
1917 trace_output (OP_NONE
);
1924 trace_input ("ei", OP_NONE
, 0);
1925 State
.sregs
[5] &= ~PSW_ID
;
1926 trace_output (OP_NONE
);
1929 /* halt, not supported */
1933 trace_input ("halt", OP_NONE
, 0);
1934 State
.exception
= SIGQUIT
;
1935 trace_output (OP_NONE
);
1938 /* reti, not supported */
1942 trace_input ("reti", OP_NONE
, 0);
1943 trace_output (OP_NONE
);
1945 if ((State
.sregs
[5] & (PSW_NP
| PSW_EP
)) == PSW_NP
)
1946 { /* Only NP is on */
1947 PC
= State
.sregs
[2] - 4; /* FEPC */
1948 State
.sregs
[5] = State
.sregs
[3]; /* FEPSW */
1952 PC
= State
.sregs
[0] - 4; /* EIPC */
1953 State
.sregs
[5] = State
.sregs
[1]; /* EIPSW */
1957 /* trap, not supportd */
1961 trace_input ("trap", OP_TRAP
, 0);
1962 trace_output (OP_TRAP
);
1964 /* Trap 31 is used for simulating OS I/O functions */
1968 int save_errno
= errno
;
1971 /* Registers passed to trap 0 */
1973 #define FUNC State.regs[6] /* function number, return value */
1974 #define PARM1 State.regs[7] /* optional parm 1 */
1975 #define PARM2 State.regs[8] /* optional parm 2 */
1976 #define PARM3 State.regs[9] /* optional parm 3 */
1978 /* Registers set by trap 0 */
1980 #define RETVAL State.regs[10] /* return value */
1981 #define RETERR State.regs[11] /* return error code */
1983 /* Turn a pointer in a register into a pointer into real memory. */
1985 #define MEMPTR(x) (map (x))
1989 #if !defined(__GO32__) && !defined(_WIN32)
1994 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
1995 (char **)MEMPTR (PARM3
));
1998 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2007 RETVAL
= pipe (host_fd
);
2008 SW (buf
, host_fd
[0]);
2009 buf
+= sizeof(uint16
);
2010 SW (buf
, host_fd
[1]);
2018 RETVAL
= wait (&status
);
2026 RETVAL
= v850_callback
->read (v850_callback
, PARM1
, MEMPTR (PARM2
),
2031 RETVAL
= (int)v850_callback
->write_stdout (v850_callback
,
2032 MEMPTR (PARM2
), PARM3
);
2034 RETVAL
= (int)v850_callback
->write (v850_callback
, PARM1
,
2035 MEMPTR (PARM2
), PARM3
);
2038 RETVAL
= v850_callback
->lseek (v850_callback
, PARM1
, PARM2
, PARM3
);
2041 RETVAL
= v850_callback
->close (v850_callback
, PARM1
);
2044 RETVAL
= v850_callback
->open (v850_callback
, MEMPTR (PARM1
), PARM2
);
2047 /* EXIT - caller can look in PARM1 to work out the
2049 if (PARM1
== 0xdead || PARM1
== 0x1)
2050 State
.exception
= SIGABRT
;
2052 State
.exception
= SIGQUIT
;
2055 case SYS_stat
: /* added at hmsi */
2056 /* stat system call */
2058 struct stat host_stat
;
2061 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2065 /* Just wild-assed guesses. */
2066 store_mem (buf
, 2, host_stat
.st_dev
);
2067 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
2068 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
2069 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
2070 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
2071 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
2072 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
2073 store_mem (buf
+ 16, 4, host_stat
.st_size
);
2074 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
2075 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
2076 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
2081 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2084 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2087 RETVAL
= time (MEMPTR (PARM1
));
2090 /* Cast the second argument to void *, to avoid type mismatch
2091 if a prototype is present. */
2092 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2101 { /* Trap 0 -> 30 */
2102 State
.sregs
[0] = PC
+ 4; /* EIPC */
2103 State
.sregs
[1] = State
.sregs
[5]; /* EIPSW */
2104 State
.sregs
[4] &= 0xffff0000; /* Mask out EICC */
2105 State
.sregs
[4] |= 0x40 + OP
[0]; /* EICC */
2106 State
.sregs
[5] |= PSW_EP
| PSW_ID
; /* Now doing exception processing */
2107 PC
= ((OP
[0] < 0x10) ? 0x40 : 0x50) - 4;
2117 trace_input ("ldsr", OP_LDSR
, 0);
2118 op0
= State
.regs
[OP
[0]];
2119 State
.sregs
[OP
[1]] = op0
;
2120 trace_output (OP_LDSR
);
2123 /* stsr, not supported */
2129 trace_input ("stsr", OP_STSR
, 0);
2130 op0
= State
.sregs
[OP
[1]];
2131 State
.regs
[OP
[0]] = op0
;
2132 trace_output (OP_STSR
);