4 #include "sys/syscall.h"
7 #if !defined(__GO32__) && !defined(_WIN32)
38 /* start-sanitize-v850e */
42 /* end-sanitize-v850e */
43 /* start-sanitize-v850eq */
48 /* end-sanitize-v850eq */
51 /* start-sanitize-v850e */
52 /* This is an array of the bit positions of registers r20 .. r31 in that order in a prepare/dispose instruction. */
53 static int type1_regs
[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
54 /* end-sanitize-v850e */
55 /* start-sanitize-v850eq */
56 /* This is an array of the bit positions of registers r16 .. r31 in that order in a push/pop instruction. */
57 static int type2_regs
[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
58 /* This is an array of the bit positions of registers r1 .. r15 in that order in a push/pop instruction. */
59 static int type3_regs
[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
60 /* end-sanitize-v850eq */
63 static void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
64 static void trace_output
PARAMS ((enum op_types result
));
65 static int init_text_p
= 0;
66 static asection
*text
;
67 static bfd_vma text_start
;
68 static bfd_vma text_end
;
71 #ifndef SIZE_INSTRUCTION
72 #define SIZE_INSTRUCTION 6
76 #define SIZE_OPERANDS 16
80 #define SIZE_VALUES 11
84 #define SIZE_LOCATION 40
89 trace_input (name
, type
, size
)
100 const char *filename
;
101 const char *functionname
;
102 unsigned int linenumber
;
104 if ((v850_debug
& DEBUG_TRACE
) == 0)
111 for (s
= prog_bfd
->sections
; s
; s
= s
->next
)
112 if (strcmp (bfd_get_section_name (prog_bfd
, s
), ".text") == 0)
115 text_start
= bfd_get_section_vma (prog_bfd
, s
);
116 text_end
= text_start
+ bfd_section_size (prog_bfd
, s
);
121 if (text
&& PC
>= text_start
&& PC
< text_end
)
123 filename
= (const char *)0;
124 functionname
= (const char *)0;
126 if (bfd_find_nearest_line (prog_bfd
, text
, (struct symbol_cache_entry
**)0, PC
- text_start
,
127 &filename
, &functionname
, &linenumber
))
132 sprintf (p
, "Line %5d ", linenumber
);
138 sprintf (p
, "Func %s ", functionname
);
143 char *q
= (char *) strrchr (filename
, '/');
144 sprintf (p
, "File %s ", (q
) ? q
+1 : filename
);
153 (*v850_callback
->printf_filtered
) (v850_callback
, "0x%.8x: %-*.*s %-*s",
155 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
156 SIZE_INSTRUCTION
, name
);
163 strcpy (buf
, "unknown");
167 sprintf (buf
, "%d", OP
[0]);
171 sprintf (buf
, "r%d", OP
[0]);
176 case OP_REG_REG_MOVE
:
177 sprintf (buf
, "r%d,r%d", OP
[0], OP
[1]);
182 case OP_IMM_REG_MOVE
:
183 sprintf (buf
, "%d,r%d", OP
[0], OP
[1]);
187 sprintf (buf
, "%d", SEXT9 (OP
[0]));
191 sprintf (buf
, "%d[r30],r%d", OP
[1] * size
, OP
[0]);
195 sprintf (buf
, "r%d,%d[r30]", OP
[0], OP
[1] * size
);
199 sprintf (buf
, "%d[r%d],r%d", SEXT16 (OP
[2]) & ~0x1, OP
[0], OP
[1]);
203 sprintf (buf
, "r%d,%d[r%d]", OP
[1], SEXT16 (OP
[2] & ~0x1), OP
[0]);
207 sprintf (buf
, "%d,r%d", SEXT22 (OP
[0]), OP
[1]);
211 sprintf (buf
, "%d,r%d,r%d", SEXT16 (OP
[0]), OP
[1], OP
[2]);
214 case OP_UIMM_REG_REG
:
215 sprintf (buf
, "%d,r%d,r%d", OP
[0] & 0xffff, OP
[1], OP
[2]);
219 sprintf (buf
, "%d,%d[r%d]", OP
[1] & 0x7, SEXT16 (OP
[2]), OP
[0]);
225 default: cond
= "?"; break;
226 case 0x0: cond
= "v"; break;
227 case 0x1: cond
= "c"; break;
228 case 0x2: cond
= "z"; break;
229 case 0x3: cond
= "nh"; break;
230 case 0x4: cond
= "s"; break;
231 case 0x5: cond
= "t"; break;
232 case 0x6: cond
= "lt"; break;
233 case 0x7: cond
= "le"; break;
234 case 0x8: cond
= "nv"; break;
235 case 0x9: cond
= "nc"; break;
236 case 0xa: cond
= "nz"; break;
237 case 0xb: cond
= "h"; break;
238 case 0xc: cond
= "ns"; break;
239 case 0xd: cond
= "sa"; break;
240 case 0xe: cond
= "ge"; break;
241 case 0xf: cond
= "gt"; break;
244 sprintf (buf
, "%s,r%d", cond
, OP
[1]);
253 sprintf (buf
, "r%d,s%d", OP
[0], OP
[1]);
257 for (i
= 0; i
< 12; i
++)
258 if (OP
[3] & (1 << type1_regs
[i
]))
259 strcat (buf
, "r%d ", i
+ 20);
263 for (i
= 0; i
< 16; i
++)
264 if (OP
[3] & (1 << type2_regs
[i
]))
265 strcat (buf
, "r%d ", i
+ 16);
266 if (OP
[3] & (1 << 19))
267 strcat (buf
, "F/EIPC, F/EIPSW " );
271 for (i
= 0; i
< 15; i
++)
272 if (OP
[3] & (1 << type3_regs
[i
]))
273 strcat (buf
, "r%d ", i
+ 1);
274 if (OP
[3] & (1 << 3))
275 strcat (buf
, "PSW " );
276 if (OP
[3] & (1 << 19))
277 strcat (buf
, "F/EIPC, F/EIPSW " );
281 sprintf (buf
, "r%d, [r%d]", OP
[1], OP
[0] );
285 if ((v850_debug
& DEBUG_VALUES
) == 0)
287 (*v850_callback
->printf_filtered
) (v850_callback
, "%s\n", buf
);
291 (*v850_callback
->printf_filtered
) (v850_callback
, "%-*s", SIZE_OPERANDS
, buf
);
302 case OP_REG_REG_MOVE
:
303 values
[0] = State
.regs
[OP
[0]];
310 values
[0] = State
.regs
[OP
[1]];
311 values
[1] = State
.regs
[OP
[0]];
317 values
[0] = SEXT5 (OP
[0]);
322 case OP_IMM_REG_MOVE
:
323 values
[0] = SEXT5 (OP
[0]);
328 values
[0] = State
.pc
;
329 values
[1] = SEXT9 (OP
[0]);
335 values
[0] = OP
[1] * size
;
336 values
[1] = State
.regs
[30];
341 values
[0] = State
.regs
[OP
[0]];
342 values
[1] = OP
[1] * size
;
343 values
[2] = State
.regs
[30];
348 values
[0] = SEXT16 (OP
[2]);
349 values
[1] = State
.regs
[OP
[0]];
354 values
[0] = State
.regs
[OP
[1]];
355 values
[1] = SEXT16 (OP
[2]);
356 values
[2] = State
.regs
[OP
[0]];
361 values
[0] = SEXT22 (OP
[0]);
362 values
[1] = State
.pc
;
367 values
[0] = SEXT16 (OP
[0]) << size
;
368 values
[1] = State
.regs
[OP
[1]];
372 case OP_UIMM_REG_REG
:
373 values
[0] = (OP
[0] & 0xffff) << size
;
374 values
[1] = State
.regs
[OP
[1]];
392 values
[0] = State
.regs
[OP
[0]];
397 values
[0] = State
.sregs
[OP
[1]];
401 for (i
= 0; i
< num_values
; i
++)
402 (*v850_callback
->printf_filtered
) (v850_callback
, "%*s0x%.8lx", SIZE_VALUES
- 10, "", values
[i
]);
405 (*v850_callback
->printf_filtered
) (v850_callback
, "%*s", SIZE_VALUES
, "");
410 trace_output (result
)
411 enum op_types result
;
413 if ((v850_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
433 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
434 (unsigned long)State
.regs
[OP
[0]]);
438 case OP_REG_REG_MOVE
:
440 case OP_IMM_REG_MOVE
:
443 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
444 (unsigned long)State
.regs
[OP
[1]]);
448 case OP_UIMM_REG_REG
:
449 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
450 (unsigned long)State
.regs
[OP
[2]]);
455 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
456 (unsigned long)State
.regs
[OP
[1]]);
460 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
461 (unsigned long)State
.sregs
[OP
[1]]);
465 (*v850_callback
->printf_filtered
) (v850_callback
, "\n");
470 #define trace_input(NAME, IN1, IN2)
471 #define trace_output(RESULT)
473 //#define trace_input(NAME, IN1, IN2) fprintf (stderr, NAME "\n" );
478 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
480 condition_met (unsigned code
)
482 unsigned int psw
= PSW
;
486 case 0x0: return ((psw
& PSW_OV
) != 0);
487 case 0x1: return ((psw
& PSW_CY
) != 0);
488 case 0x2: return ((psw
& PSW_Z
) != 0);
489 case 0x3: return ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0);
490 case 0x4: return ((psw
& PSW_S
) != 0);
491 /*case 0x5: return 1;*/
492 case 0x6: return ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0);
493 case 0x7: return (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) || ((psw
& PSW_Z
) != 0)) != 0);
494 case 0x8: return ((psw
& PSW_OV
) == 0);
495 case 0x9: return ((psw
& PSW_CY
) == 0);
496 case 0xa: return ((psw
& PSW_Z
) == 0);
497 case 0xb: return ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0);
498 case 0xc: return ((psw
& PSW_S
) == 0);
499 case 0xd: return ((psw
& PSW_SAT
) != 0);
500 case 0xe: return ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0);
501 case 0xf: return (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) || ((psw
& PSW_Z
) != 0)) == 0);
507 /* start-sanitize-v850e */
509 Add32 (unsigned long a1
, unsigned long a2
, int * carry
)
511 unsigned long result
= (a1
+ a2
);
513 * carry
= (result
< a1
);
519 Multiply64 (boolean sign
, unsigned long op0
)
530 op1
= State
.regs
[ OP
[1] ];
534 /* Compute sign of result and adjust operands if necessary. */
536 sign
= (op0
^ op1
) & 0x80000000;
538 if (((signed long) op0
) < 0)
541 if (((signed long) op1
) < 0)
545 /* We can split the 32x32 into four 16x16 operations. This ensures
546 that we do not lose precision on 32bit only hosts: */
547 lo
= ( (op0
& 0xFFFF) * (op1
& 0xFFFF));
548 mid1
= ( (op0
& 0xFFFF) * ((op1
>> 16) & 0xFFFF));
549 mid2
= (((op0
>> 16) & 0xFFFF) * (op1
& 0xFFFF));
550 hi
= (((op0
>> 16) & 0xFFFF) * ((op1
>> 16) & 0xFFFF));
552 /* We now need to add all of these results together, taking care
553 to propogate the carries from the additions: */
554 RdLo
= Add32 (lo
, (mid1
<< 16), & carry
);
556 RdLo
= Add32 (RdLo
, (mid2
<< 16), & carry
);
557 RdHi
+= (carry
+ ((mid1
>> 16) & 0xFFFF) + ((mid2
>> 16) & 0xFFFF) + hi
);
561 /* Negate result if necessary. */
565 if (RdLo
== 0xFFFFFFFF)
574 State
.regs
[ OP
[1] ] = RdLo
;
575 State
.regs
[ OP
[2] >> 11 ] = RdHi
;
579 /* end-sanitize-v850e */
586 unsigned long result
;
588 result
= load_mem (State
.regs
[30] + (OP
[3] & 0x7f), 1);
590 /* start-sanitize-v850eq */
592 trace_input ("sld.bu", OP_LOAD16
, 1);
594 State
.regs
[ OP
[1] ] = result
;
596 /* end-sanitize-v850eq */
597 trace_input ("sld.b", OP_LOAD16
, 1);
599 State
.regs
[ OP
[1] ] = SEXT8 (result
);
600 /* start-sanitize-v850eq */
602 /* end-sanitize-v850eq */
604 trace_output (OP_LOAD16
);
613 unsigned long result
;
615 result
= load_mem (State
.regs
[30] + ((OP
[3] & 0x7f) << 1), 2);
617 /* start-sanitize-v850eq */
619 trace_input ("sld.hu", OP_LOAD16
, 2);
621 State
.regs
[ OP
[1] ] = result
;
623 /* end-sanitize-v850eq */
624 trace_input ("sld.h", OP_LOAD16
, 2);
626 State
.regs
[ OP
[1] ] = SEXT16 (result
);
627 /* start-sanitize-v850eq */
629 /* end-sanitize-v850eq */
631 trace_output (OP_LOAD16
);
640 trace_input ("sld.w", OP_LOAD16
, 4);
642 State
.regs
[ OP
[1] ] = load_mem (State
.regs
[30] + ((OP
[3] & 0x7f) << 1), 4);
644 trace_output (OP_LOAD16
);
653 trace_input ("sst.b", OP_STORE16
, 1);
655 store_mem (State
.regs
[30] + (OP
[3] & 0x7f), 1, State
.regs
[ OP
[1] ]);
657 trace_output (OP_STORE16
);
666 trace_input ("sst.h", OP_STORE16
, 2);
668 store_mem (State
.regs
[30] + ((OP
[3] & 0x7f) << 1), 2, State
.regs
[ OP
[1] ]);
670 trace_output (OP_STORE16
);
679 trace_input ("sst.w", OP_STORE16
, 4);
681 store_mem (State
.regs
[30] + ((OP
[3] & 0x7e) << 1), 4, State
.regs
[ OP
[1] ]);
683 trace_output (OP_STORE16
);
694 trace_input ("ld.b", OP_LOAD32
, 1);
696 adr
= State
.regs
[ OP
[0] ] + SEXT16 (OP
[2]);
698 State
.regs
[ OP
[1] ] = SEXT8 (load_mem (adr
, 1));
700 trace_output (OP_LOAD32
);
711 trace_input ("ld.h", OP_LOAD32
, 2);
713 adr
= State
.regs
[ OP
[0] ] + SEXT16 (OP
[2]);
716 State
.regs
[ OP
[1] ] = SEXT16 (load_mem (adr
, 2));
718 trace_output (OP_LOAD32
);
729 trace_input ("ld.w", OP_LOAD32
, 4);
731 adr
= State
.regs
[ OP
[0] ] + SEXT16 (OP
[2] & ~1);
734 State
.regs
[ OP
[1] ] = load_mem (adr
, 4);
736 trace_output (OP_LOAD32
);
745 trace_input ("st.b", OP_STORE32
, 1);
747 store_mem (State
.regs
[ OP
[0] ] + SEXT16 (OP
[2]), 1, State
.regs
[ OP
[1] ]);
749 trace_output (OP_STORE32
);
760 trace_input ("st.h", OP_STORE32
, 2);
762 adr
= State
.regs
[ OP
[0] ] + SEXT16 (OP
[2]);
765 store_mem (adr
, 2, State
.regs
[ OP
[1] ]);
767 trace_output (OP_STORE32
);
778 trace_input ("st.w", OP_STORE32
, 4);
780 adr
= State
.regs
[ OP
[0] ] + SEXT16 (OP
[2] & ~1);
783 store_mem (adr
, 4, State
.regs
[ OP
[1] ]);
785 trace_output (OP_STORE32
);
796 trace_input ("Bcond", OP_COND_BR
, 0);
797 trace_output (OP_COND_BR
);
799 if (condition_met (code
))
800 return SEXT9 (((OP
[3] & 0x70) >> 3) | ((OP
[3] & 0xf800) >> 7));
918 /* sld.bu disp4[ep], reg2 */
924 trace_input ("jmp", OP_REG
, 0);
926 PC
= State
.regs
[ OP
[0] ];
928 trace_output (OP_REG
);
930 return 0; /* Add nothing to the PC, we have already done it. */
932 /* start-sanitize-v850e */
935 unsigned long result
;
937 result
= load_mem (State
.regs
[30] + (OP
[3] & 0xf), 1);
939 /* start-sanitize-v850eq */
941 trace_input ("sld.b", OP_LOAD16
, 1);
943 State
.regs
[ OP
[1] ] = SEXT8 (result
);
945 /* end-sanitize-v850eq */
946 trace_input ("sld.bu", OP_LOAD16
, 1);
948 State
.regs
[ OP
[1] ] = result
;
949 /* start-sanitize-v850eq */
951 /* end-sanitize-v850eq */
953 trace_output (OP_LOAD16
);
957 /* end-sanitize-v850e */
960 /* jarl/jr disp22, reg */
964 trace_input ("jarl/jr", OP_JUMP
, 0);
967 State
.regs
[ OP
[1] ] = PC
+ 4;
969 trace_output (OP_JUMP
);
971 return SEXT22 (((OP
[3] & 0x3f) << 16) | OP
[2]);
978 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
980 trace_input ("add", OP_REG_REG
, 0);
982 /* Compute the result. */
984 op0
= State
.regs
[ OP
[0] ];
985 op1
= State
.regs
[ OP
[1] ];
989 /* Compute the condition codes. */
991 s
= (result
& 0x80000000);
992 cy
= (result
< op0
|| result
< op1
);
993 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
994 && (op0
& 0x80000000) != (result
& 0x80000000));
996 /* Store the result and condition codes. */
997 State
.regs
[OP
[1]] = result
;
998 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
999 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1000 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1001 trace_output (OP_REG_REG
);
1006 /* add sign_extend(imm5), reg */
1010 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1013 trace_input ("add", OP_IMM_REG
, 0);
1015 /* Compute the result. */
1016 temp
= SEXT5 (OP
[0]);
1018 op1
= State
.regs
[OP
[1]];
1021 /* Compute the condition codes. */
1023 s
= (result
& 0x80000000);
1024 cy
= (result
< op0
|| result
< op1
);
1025 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1026 && (op0
& 0x80000000) != (result
& 0x80000000));
1028 /* Store the result and condition codes. */
1029 State
.regs
[OP
[1]] = result
;
1030 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1031 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1032 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1033 trace_output (OP_IMM_REG
);
1038 /* addi sign_extend(imm16), reg, reg */
1042 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1044 trace_input ("addi", OP_IMM_REG_REG
, 0);
1046 /* Compute the result. */
1048 op0
= SEXT16 (OP
[2]);
1049 op1
= State
.regs
[ OP
[0] ];
1052 /* Compute the condition codes. */
1054 s
= (result
& 0x80000000);
1055 cy
= (result
< op0
|| result
< op1
);
1056 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1057 && (op0
& 0x80000000) != (result
& 0x80000000));
1059 /* Store the result and condition codes. */
1060 State
.regs
[OP
[1]] = result
;
1061 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1062 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1063 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1064 trace_output (OP_IMM_REG_REG
);
1069 /* sub reg1, reg2 */
1073 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1075 trace_input ("sub", OP_REG_REG
, 0);
1076 /* Compute the result. */
1077 op0
= State
.regs
[ OP
[0] ];
1078 op1
= State
.regs
[ OP
[1] ];
1081 /* Compute the condition codes. */
1083 s
= (result
& 0x80000000);
1085 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1086 && (op1
& 0x80000000) != (result
& 0x80000000));
1088 /* Store the result and condition codes. */
1089 State
.regs
[OP
[1]] = result
;
1090 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1091 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1092 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1093 trace_output (OP_REG_REG
);
1098 /* subr reg1, reg2 */
1102 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1104 trace_input ("subr", OP_REG_REG
, 0);
1105 /* Compute the result. */
1106 op0
= State
.regs
[ OP
[0] ];
1107 op1
= State
.regs
[ OP
[1] ];
1110 /* Compute the condition codes. */
1112 s
= (result
& 0x80000000);
1114 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
1115 && (op0
& 0x80000000) != (result
& 0x80000000));
1117 /* Store the result and condition codes. */
1118 State
.regs
[OP
[1]] = result
;
1119 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1120 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1121 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1122 trace_output (OP_REG_REG
);
1128 /* mulh reg1, reg2 */
1132 /* start-sanitize-v850e */
1135 trace_input ("sxh", OP_REG
, 0);
1137 State
.regs
[ OP
[0] ] = SEXT16 (State
.regs
[ OP
[0] ]);
1139 trace_output (OP_REG
);
1142 /* end-sanitize-v850e */
1144 trace_input ("mulh", OP_REG_REG
, 0);
1146 State
.regs
[ OP
[1] ] = (SEXT16 (State
.regs
[ OP
[1] ]) * SEXT16 (State
.regs
[ OP
[0] ]));
1148 trace_output (OP_REG_REG
);
1154 /* mulh sign_extend(imm5), reg2 */
1158 trace_input ("mulh", OP_IMM_REG
, 0);
1160 State
.regs
[ OP
[1] ] = SEXT16 (State
.regs
[ OP
[1] ]) * SEXT5 (OP
[0]);
1162 trace_output (OP_IMM_REG
);
1167 /* mulhi imm16, reg1, reg2 */
1176 trace_input ("mulhi", OP_IMM_REG_REG
, 0);
1178 State
.regs
[ OP
[1] ] = SEXT16 (State
.regs
[ OP
[0] ]) * SEXT16 (OP
[2]);
1180 trace_output (OP_IMM_REG_REG
);
1186 /* divh reg1, reg2 */
1191 /* start-sanitize-v850e */
1196 trace_input ("switch", OP_REG
, 0);
1198 adr
= State
.pc
+ 2 + (State
.regs
[ OP
[0] ] << 1);
1199 State
.pc
= State
.pc
+ 2 + (SEXT16 (load_mem (adr
, 2)) << 1);
1201 trace_output (OP_REG
);
1204 /* end-sanitize-v850e */
1206 unsigned int op0
, op1
, result
, ov
, s
, z
;
1209 trace_input ("divh", OP_REG_REG
, 0);
1211 /* Compute the result. */
1212 temp
= SEXT16 (State
.regs
[ OP
[0] ]);
1214 op1
= State
.regs
[OP
[1]];
1216 if (op0
== 0xffffffff && op1
== 0x80000000)
1218 result
= 0x80000000;
1232 /* Compute the condition codes. */
1234 s
= (result
& 0x80000000);
1236 /* Store the result and condition codes. */
1237 State
.regs
[OP
[1]] = result
;
1238 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1239 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1240 | (ov
? PSW_OV
: 0));
1241 trace_output (OP_REG_REG
);
1251 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1253 trace_input ("cmp", OP_REG_REG_CMP
, 0);
1254 /* Compute the result. */
1255 op0
= State
.regs
[ OP
[0] ];
1256 op1
= State
.regs
[ OP
[1] ];
1259 /* Compute the condition codes. */
1261 s
= (result
& 0x80000000);
1263 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1264 && (op1
& 0x80000000) != (result
& 0x80000000));
1266 /* Set condition codes. */
1267 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1268 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1269 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1270 trace_output (OP_REG_REG_CMP
);
1275 /* cmp sign_extend(imm5), reg */
1279 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1282 /* Compute the result. */
1283 trace_input ("cmp", OP_IMM_REG_CMP
, 0);
1284 temp
= SEXT5 (OP
[0]);
1286 op1
= State
.regs
[OP
[1]];
1289 /* Compute the condition codes. */
1291 s
= (result
& 0x80000000);
1293 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1294 && (op1
& 0x80000000) != (result
& 0x80000000));
1296 /* Set condition codes. */
1297 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1298 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1299 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1300 trace_output (OP_IMM_REG_CMP
);
1305 /* setf cccc,reg2 */
1309 trace_input ("setf", OP_EX1
, 0);
1311 State
.regs
[ OP
[1] ] = condition_met (OP
[0]);
1313 trace_output (OP_EX1
);
1319 /* satadd reg,reg */
1323 /* start-sanitize-v850e */
1326 trace_input ("zxh", OP_REG
, 0);
1328 State
.regs
[ OP
[0] ] &= 0xffff;
1330 trace_output (OP_REG
);
1333 /* end-sanitize-v850e */
1335 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1337 trace_input ("satadd", OP_REG_REG
, 0);
1338 /* Compute the result. */
1339 op0
= State
.regs
[ OP
[0] ];
1340 op1
= State
.regs
[ OP
[1] ];
1343 /* Compute the condition codes. */
1345 s
= (result
& 0x80000000);
1346 cy
= (result
< op0
|| result
< op1
);
1347 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1348 && (op0
& 0x80000000) != (result
& 0x80000000));
1351 /* Store the result and condition codes. */
1352 State
.regs
[OP
[1]] = result
;
1353 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1354 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1355 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1356 | (sat
? PSW_SAT
: 0));
1358 /* Handle saturated results. */
1360 State
.regs
[OP
[1]] = 0x80000000;
1362 State
.regs
[OP
[1]] = 0x7fffffff;
1363 trace_output (OP_REG_REG
);
1369 /* satadd sign_extend(imm5), reg */
1373 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1377 trace_input ("satadd", OP_IMM_REG
, 0);
1379 /* Compute the result. */
1380 temp
= SEXT5 (OP
[0]);
1382 op1
= State
.regs
[OP
[1]];
1385 /* Compute the condition codes. */
1387 s
= (result
& 0x80000000);
1388 cy
= (result
< op0
|| result
< op1
);
1389 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1390 && (op0
& 0x80000000) != (result
& 0x80000000));
1393 /* Store the result and condition codes. */
1394 State
.regs
[OP
[1]] = result
;
1395 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1396 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1397 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1398 | (sat
? PSW_SAT
: 0));
1400 /* Handle saturated results. */
1402 State
.regs
[OP
[1]] = 0x80000000;
1404 State
.regs
[OP
[1]] = 0x7fffffff;
1405 trace_output (OP_IMM_REG
);
1410 /* satsub reg1, reg2 */
1415 /* start-sanitize-v850e */
1418 trace_input ("sxb", OP_REG
, 0);
1420 State
.regs
[ OP
[0] ] = SEXT8 (State
.regs
[ OP
[0] ]);
1422 trace_output (OP_REG
);
1425 /* end-sanitize-v850e */
1427 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1429 trace_input ("satsub", OP_REG_REG
, 0);
1431 /* Compute the result. */
1432 op0
= State
.regs
[ OP
[0] ];
1433 op1
= State
.regs
[ OP
[1] ];
1436 /* Compute the condition codes. */
1438 s
= (result
& 0x80000000);
1440 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1441 && (op1
& 0x80000000) != (result
& 0x80000000));
1444 /* Store the result and condition codes. */
1445 State
.regs
[OP
[1]] = result
;
1446 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1447 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1448 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1449 | (sat
? PSW_SAT
: 0));
1451 /* Handle saturated results. */
1453 State
.regs
[OP
[1]] = 0x80000000;
1455 State
.regs
[OP
[1]] = 0x7fffffff;
1456 trace_output (OP_REG_REG
);
1462 /* satsubi sign_extend(imm16), reg */
1466 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1469 trace_input ("satsubi", OP_IMM_REG
, 0);
1471 /* Compute the result. */
1472 temp
= SEXT16 (OP
[2]);
1474 op1
= State
.regs
[ OP
[0] ];
1477 /* Compute the condition codes. */
1479 s
= (result
& 0x80000000);
1481 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1482 && (op1
& 0x80000000) != (result
& 0x80000000));
1485 /* Store the result and condition codes. */
1486 State
.regs
[OP
[1]] = result
;
1487 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1488 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1489 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1490 | (sat
? PSW_SAT
: 0));
1492 /* Handle saturated results. */
1494 State
.regs
[OP
[1]] = 0x80000000;
1496 State
.regs
[OP
[1]] = 0x7fffffff;
1497 trace_output (OP_IMM_REG
);
1502 /* satsubr reg,reg */
1507 /* start-sanitize-v850e */
1510 trace_input ("zxb", OP_REG
, 0);
1512 State
.regs
[ OP
[0] ] &= 0xff;
1514 trace_output (OP_REG
);
1517 /* end-sanitize-v850e */
1519 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1521 trace_input ("satsubr", OP_REG_REG
, 0);
1523 /* Compute the result. */
1524 op0
= State
.regs
[ OP
[0] ];
1525 op1
= State
.regs
[ OP
[1] ];
1528 /* Compute the condition codes. */
1530 s
= (result
& 0x80000000);
1531 cy
= (result
< op0
);
1532 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1533 && (op1
& 0x80000000) != (result
& 0x80000000));
1536 /* Store the result and condition codes. */
1537 State
.regs
[OP
[1]] = result
;
1538 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1539 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1540 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1541 | (sat
? PSW_SAT
: 0));
1543 /* Handle saturated results. */
1545 State
.regs
[OP
[1]] = 0x80000000;
1547 State
.regs
[OP
[1]] = 0x7fffffff;
1548 trace_output (OP_REG_REG
);
1558 unsigned int op0
, op1
, result
, z
, s
;
1560 trace_input ("tst", OP_REG_REG_CMP
, 0);
1562 /* Compute the result. */
1563 op0
= State
.regs
[ OP
[0] ];
1564 op1
= State
.regs
[ OP
[1] ];
1567 /* Compute the condition codes. */
1569 s
= (result
& 0x80000000);
1571 /* Store the condition codes. */
1572 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1573 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1574 trace_output (OP_REG_REG_CMP
);
1583 trace_input ("mov", OP_REG_REG_MOVE
, 0);
1585 State
.regs
[ OP
[1] ] = State
.regs
[ OP
[0] ];
1587 trace_output (OP_REG_REG_MOVE
);
1592 /* mov sign_extend(imm5), reg */
1597 /* start-sanitize-v850e */
1602 trace_input ("callt", OP_LOAD16
, 1);
1607 adr
= CTBP
+ ((OP
[3] & 0x3f) << 1);
1609 PC
= CTBP
+ load_mem (adr
, 1);
1611 trace_output (OP_LOAD16
);
1616 /* end-sanitize-v850e */
1618 int value
= SEXT5 (OP
[0]);
1620 trace_input ("mov", OP_IMM_REG_MOVE
, 0);
1622 State
.regs
[ OP
[1] ] = value
;
1624 trace_output (OP_IMM_REG_MOVE
);
1630 /* mov imm32, reg1 */
1631 /* movea sign_extend(imm16), reg, reg */
1635 /* start-sanitize-v850e */
1638 trace_input ("mov", OP_IMM32_REG
, 4);
1640 State
.regs
[ OP
[0] ] = load_mem (PC
+ 2, 4);
1642 trace_output (OP_IMM32_REG
);
1647 /* end-sanitize-v850e */
1649 trace_input ("movea", OP_IMM_REG_REG
, 0);
1651 State
.regs
[ OP
[1] ] = State
.regs
[ OP
[0] ] + SEXT16 (OP
[2]);
1653 trace_output (OP_IMM_REG_REG
);
1659 /* dispose imm5, list12 [, reg1] */
1660 /* movhi imm16, reg, reg */
1664 /* start-sanitize-v850e */
1670 trace_input ("dispose", OP_PUSHPOP1
, 0);
1672 SP
+= (OP
[3] & 0x3e) << 1;
1674 /* Load the registers with lower number registers being retrieved from lower addresses. */
1675 for (i
= 0; i
< 12; i
++)
1676 if ((OP
[3] & (1 << type1_regs
[ i
])))
1678 State
.regs
[ 20 + i
] = load_mem (SP
, 4);
1682 if ((OP
[3] & 0x1f0000) != 0)
1684 PC
= State
.regs
[ (OP
[3] >> 16) & 0x1f];
1688 trace_output (OP_PUSHPOP1
);
1691 /* end-sanitize-v850e */
1693 trace_input ("movhi", OP_UIMM_REG_REG
, 16);
1695 State
.regs
[ OP
[1] ] = State
.regs
[ OP
[0] ] + OP
[2] << 16;
1697 trace_output (OP_UIMM_REG_REG
);
1703 /* sar zero_extend(imm5),reg1 */
1707 unsigned int op0
, op1
, result
, z
, s
, cy
;
1709 trace_input ("sar", OP_IMM_REG
, 0);
1711 op1
= State
.regs
[ OP
[1] ];
1712 result
= (signed)op1
>> op0
;
1714 /* Compute the condition codes. */
1716 s
= (result
& 0x80000000);
1717 cy
= (op1
& (1 << (op0
- 1)));
1719 /* Store the result and condition codes. */
1720 State
.regs
[ OP
[1] ] = result
;
1721 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1722 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1723 | (cy
? PSW_CY
: 0));
1724 trace_output (OP_IMM_REG
);
1729 /* sar reg1, reg2 */
1733 unsigned int op0
, op1
, result
, z
, s
, cy
;
1735 trace_input ("sar", OP_REG_REG
, 0);
1737 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1738 op1
= State
.regs
[ OP
[1] ];
1739 result
= (signed)op1
>> op0
;
1741 /* Compute the condition codes. */
1743 s
= (result
& 0x80000000);
1744 cy
= (op1
& (1 << (op0
- 1)));
1746 /* Store the result and condition codes. */
1747 State
.regs
[OP
[1]] = result
;
1748 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1749 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1750 | (cy
? PSW_CY
: 0));
1751 trace_output (OP_REG_REG
);
1756 /* shl zero_extend(imm5),reg1 */
1760 unsigned int op0
, op1
, result
, z
, s
, cy
;
1762 trace_input ("shl", OP_IMM_REG
, 0);
1764 op1
= State
.regs
[ OP
[1] ];
1765 result
= op1
<< op0
;
1767 /* Compute the condition codes. */
1769 s
= (result
& 0x80000000);
1770 cy
= (op1
& (1 << (32 - op0
)));
1772 /* Store the result and condition codes. */
1773 State
.regs
[OP
[1]] = result
;
1774 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1775 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1776 | (cy
? PSW_CY
: 0));
1777 trace_output (OP_IMM_REG
);
1782 /* shl reg1, reg2 */
1786 unsigned int op0
, op1
, result
, z
, s
, cy
;
1788 trace_input ("shl", OP_REG_REG
, 0);
1789 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1790 op1
= State
.regs
[ OP
[1] ];
1791 result
= op1
<< op0
;
1793 /* Compute the condition codes. */
1795 s
= (result
& 0x80000000);
1796 cy
= (op1
& (1 << (32 - op0
)));
1798 /* Store the result and condition codes. */
1799 State
.regs
[OP
[1]] = result
;
1800 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1801 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1802 | (cy
? PSW_CY
: 0));
1803 trace_output (OP_REG_REG
);
1808 /* shr zero_extend(imm5),reg1 */
1812 unsigned int op0
, op1
, result
, z
, s
, cy
;
1814 trace_input ("shr", OP_IMM_REG
, 0);
1816 op1
= State
.regs
[ OP
[1] ];
1817 result
= op1
>> op0
;
1819 /* Compute the condition codes. */
1821 s
= (result
& 0x80000000);
1822 cy
= (op1
& (1 << (op0
- 1)));
1824 /* Store the result and condition codes. */
1825 State
.regs
[OP
[1]] = result
;
1826 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1827 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1828 | (cy
? PSW_CY
: 0));
1829 trace_output (OP_IMM_REG
);
1834 /* shr reg1, reg2 */
1838 unsigned int op0
, op1
, result
, z
, s
, cy
;
1840 trace_input ("shr", OP_REG_REG
, 0);
1841 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1842 op1
= State
.regs
[ OP
[1] ];
1843 result
= op1
>> op0
;
1845 /* Compute the condition codes. */
1847 s
= (result
& 0x80000000);
1848 cy
= (op1
& (1 << (op0
- 1)));
1850 /* Store the result and condition codes. */
1851 State
.regs
[OP
[1]] = result
;
1852 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1853 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1854 | (cy
? PSW_CY
: 0));
1855 trace_output (OP_REG_REG
);
1864 unsigned int op0
, op1
, result
, z
, s
;
1866 trace_input ("or", OP_REG_REG
, 0);
1868 /* Compute the result. */
1869 op0
= State
.regs
[ OP
[0] ];
1870 op1
= State
.regs
[ OP
[1] ];
1873 /* Compute the condition codes. */
1875 s
= (result
& 0x80000000);
1877 /* Store the result and condition codes. */
1878 State
.regs
[OP
[1]] = result
;
1879 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1880 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1881 trace_output (OP_REG_REG
);
1886 /* ori zero_extend(imm16), reg, reg */
1890 unsigned int op0
, op1
, result
, z
, s
;
1892 trace_input ("ori", OP_UIMM_REG_REG
, 0);
1894 op1
= State
.regs
[ OP
[0] ];
1897 /* Compute the condition codes. */
1899 s
= (result
& 0x80000000);
1901 /* Store the result and condition codes. */
1902 State
.regs
[OP
[1]] = result
;
1903 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1904 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1905 trace_output (OP_UIMM_REG_REG
);
1914 unsigned int op0
, op1
, result
, z
, s
;
1916 trace_input ("and", OP_REG_REG
, 0);
1918 /* Compute the result. */
1919 op0
= State
.regs
[ OP
[0] ];
1920 op1
= State
.regs
[ OP
[1] ];
1923 /* Compute the condition codes. */
1925 s
= (result
& 0x80000000);
1927 /* Store the result and condition codes. */
1928 State
.regs
[OP
[1]] = result
;
1929 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1930 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1931 trace_output (OP_REG_REG
);
1936 /* andi zero_extend(imm16), reg, reg */
1940 unsigned int result
, z
;
1942 trace_input ("andi", OP_UIMM_REG_REG
, 0);
1944 result
= OP
[2] & State
.regs
[ OP
[0] ];
1946 /* Compute the condition codes. */
1949 /* Store the result and condition codes. */
1950 State
.regs
[ OP
[1] ] = result
;
1952 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1953 PSW
|= (z
? PSW_Z
: 0);
1955 trace_output (OP_UIMM_REG_REG
);
1964 unsigned int op0
, op1
, result
, z
, s
;
1966 trace_input ("xor", OP_REG_REG
, 0);
1968 /* Compute the result. */
1969 op0
= State
.regs
[ OP
[0] ];
1970 op1
= State
.regs
[ OP
[1] ];
1973 /* Compute the condition codes. */
1975 s
= (result
& 0x80000000);
1977 /* Store the result and condition codes. */
1978 State
.regs
[OP
[1]] = result
;
1979 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1980 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1981 trace_output (OP_REG_REG
);
1986 /* xori zero_extend(imm16), reg, reg */
1990 unsigned int op0
, op1
, result
, z
, s
;
1992 trace_input ("xori", OP_UIMM_REG_REG
, 0);
1994 op1
= State
.regs
[ OP
[0] ];
1997 /* Compute the condition codes. */
1999 s
= (result
& 0x80000000);
2001 /* Store the result and condition codes. */
2002 State
.regs
[OP
[1]] = result
;
2003 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2004 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
2005 trace_output (OP_UIMM_REG_REG
);
2010 /* not reg1, reg2 */
2014 unsigned int op0
, result
, z
, s
;
2016 trace_input ("not", OP_REG_REG_MOVE
, 0);
2017 /* Compute the result. */
2018 op0
= State
.regs
[ OP
[0] ];
2021 /* Compute the condition codes. */
2023 s
= (result
& 0x80000000);
2025 /* Store the result and condition codes. */
2026 State
.regs
[OP
[1]] = result
;
2027 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2028 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
2029 trace_output (OP_REG_REG_MOVE
);
2038 unsigned int op0
, op1
, op2
;
2041 trace_input ("set1", OP_BIT
, 0);
2042 op0
= State
.regs
[ OP
[0] ];
2044 temp
= SEXT16 (OP
[2]);
2046 temp
= load_mem (op0
+ op2
, 1);
2048 if ((temp
& (1 << op1
)) == 0)
2051 store_mem (op0
+ op2
, 1, temp
);
2052 trace_output (OP_BIT
);
2061 unsigned int op0
, op1
, op2
;
2064 trace_input ("not1", OP_BIT
, 0);
2065 op0
= State
.regs
[ OP
[0] ];
2067 temp
= SEXT16 (OP
[2]);
2069 temp
= load_mem (op0
+ op2
, 1);
2071 if ((temp
& (1 << op1
)) == 0)
2074 store_mem (op0
+ op2
, 1, temp
);
2075 trace_output (OP_BIT
);
2084 unsigned int op0
, op1
, op2
;
2087 trace_input ("clr1", OP_BIT
, 0);
2088 op0
= State
.regs
[ OP
[0] ];
2090 temp
= SEXT16 (OP
[2]);
2092 temp
= load_mem (op0
+ op2
, 1);
2094 if ((temp
& (1 << op1
)) == 0)
2096 temp
&= ~(1 << op1
);
2097 store_mem (op0
+ op2
, 1, temp
);
2098 trace_output (OP_BIT
);
2107 unsigned int op0
, op1
, op2
;
2110 trace_input ("tst1", OP_BIT
, 0);
2111 op0
= State
.regs
[ OP
[0] ];
2113 temp
= SEXT16 (OP
[2]);
2115 temp
= load_mem (op0
+ op2
, 1);
2117 if ((temp
& (1 << op1
)) == 0)
2119 trace_output (OP_BIT
);
2128 State
.exception
= SIGTRAP
;
2136 trace_input ("di", OP_NONE
, 0);
2138 trace_output (OP_NONE
);
2147 trace_input ("ei", OP_NONE
, 0);
2149 trace_output (OP_NONE
);
2158 trace_input ("halt", OP_NONE
, 0);
2159 /* FIXME this should put processor into a mode where NMI still handled */
2160 State
.exception
= SIGQUIT
;
2161 trace_output (OP_NONE
);
2170 trace_input ("reti", OP_NONE
, 0);
2171 trace_output (OP_NONE
);
2173 /* Restore for NMI if only NP on, otherwise is interrupt or exception. */
2174 if ((PSW
& (PSW_NP
| PSW_EP
)) == PSW_NP
)
2192 trace_input ("trap", OP_TRAP
, 0);
2193 trace_output (OP_TRAP
);
2195 /* Trap 31 is used for simulating OS I/O functions */
2199 int save_errno
= errno
;
2202 /* Registers passed to trap 0 */
2204 #define FUNC State.regs[6] /* function number, return value */
2205 #define PARM1 State.regs[7] /* optional parm 1 */
2206 #define PARM2 State.regs[8] /* optional parm 2 */
2207 #define PARM3 State.regs[9] /* optional parm 3 */
2209 /* Registers set by trap 0 */
2211 #define RETVAL State.regs[10] /* return value */
2212 #define RETERR State.regs[11] /* return error code */
2214 /* Turn a pointer in a register into a pointer into real memory. */
2216 #define MEMPTR(x) (map (x))
2220 #if !defined(__GO32__) && !defined(_WIN32)
2225 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2226 (char **)MEMPTR (PARM3
));
2230 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2240 RETVAL
= pipe (host_fd
);
2241 SW (buf
, host_fd
[0]);
2242 buf
+= sizeof(uint16
);
2243 SW (buf
, host_fd
[1]);
2251 RETVAL
= wait (&status
);
2259 RETVAL
= v850_callback
->read (v850_callback
, PARM1
, MEMPTR (PARM2
),
2264 RETVAL
= (int)v850_callback
->write_stdout (v850_callback
,
2265 MEMPTR (PARM2
), PARM3
);
2267 RETVAL
= (int)v850_callback
->write (v850_callback
, PARM1
,
2268 MEMPTR (PARM2
), PARM3
);
2271 RETVAL
= v850_callback
->lseek (v850_callback
, PARM1
, PARM2
, PARM3
);
2274 RETVAL
= v850_callback
->close (v850_callback
, PARM1
);
2277 RETVAL
= v850_callback
->open (v850_callback
, MEMPTR (PARM1
), PARM2
);
2280 if ((PARM1
& 0xffff0000) == 0xdead0000 && (PARM1
& 0xffff) != 0)
2281 State
.exception
= PARM1
& 0xffff; /* get signal encoded by kill */
2282 else if (PARM1
== 0xdead)
2283 State
.exception
= SIGABRT
; /* old libraries */
2285 State
.exception
= SIG_V850_EXIT
; /* PARM1 has exit status encoded */
2288 #if !defined(__GO32__) && !defined(_WIN32)
2289 case SYS_stat
: /* added at hmsi */
2290 /* stat system call */
2292 struct stat host_stat
;
2295 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2299 /* Just wild-assed guesses. */
2300 store_mem (buf
, 2, host_stat
.st_dev
);
2301 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
2302 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
2303 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
2304 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
2305 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
2306 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
2307 store_mem (buf
+ 16, 4, host_stat
.st_size
);
2308 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
2309 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
2310 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
2315 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2318 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2324 RETVAL
= time (&now
);
2325 store_mem (PARM1
, 4, now
);
2333 RETVAL
= times (&tms
);
2334 store_mem (PARM1
, 4, tms
.tms_utime
);
2335 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
2336 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
2337 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
2341 case SYS_gettimeofday
:
2345 RETVAL
= gettimeofday (&t
, &tz
);
2346 store_mem (PARM1
, 4, t
.tv_sec
);
2347 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
2348 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
2349 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
2354 /* Cast the second argument to void *, to avoid type mismatch
2355 if a prototype is present. */
2356 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2369 { /* Trap 0 -> 30 */
2374 ECR
|= 0x40 + OP
[0];
2375 /* Flag that we are now doing exception processing. */
2376 PSW
|= PSW_EP
| PSW_ID
;
2377 PC
= ((OP
[0] < 0x10) ? 0x40 : 0x50) - 4;
2387 trace_input ("ldsr", OP_LDSR
, 0);
2389 State
.sregs
[ OP
[1] ] = State
.regs
[ OP
[0] ];
2391 trace_output (OP_LDSR
);
2402 trace_input ("stsr", OP_STSR
, 0);
2404 State
.regs
[ OP
[1] ] = State
.sregs
[ OP
[0] ];
2406 trace_output (OP_STSR
);
2411 /* tst1 reg2, [reg1] */
2417 trace_input ("tst1", OP_BIT_LOAD
, 1);
2419 temp
= load_mem (State
.regs
[ OP
[0] ], 1);
2422 if ((temp
& (1 << State
.regs
[ OP
[1] & 0x7 ])) == 0)
2425 trace_output (OP_BIT_LOAD
);
2430 /* start-sanitize-v850e */
2432 #define BIT_CHANGE_OP( name, binop ) \
2434 unsigned int temp; \
2436 trace_input (name, OP_BIT_CHANGE, 0); \
2438 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
2439 temp = load_mem (State.regs[ OP[0] ], 1); \
2442 if ((temp & bit) == 0) \
2446 store_mem (State.regs[ OP[0] ], 1, temp); \
2448 trace_output (OP_BIT_CHANGE); \
2452 /* clr1 reg2, [reg1] */
2456 BIT_CHANGE_OP ("clr1", &= ~ );
2459 /* not1 reg2, [reg1] */
2463 BIT_CHANGE_OP ("not1", ^= );
2470 BIT_CHANGE_OP ("set1", |= );
2477 trace_input ("sasf", OP_EX1
, 0);
2479 State
.regs
[ OP
[1] ] = (State
.regs
[ OP
[1] ] << 1) | condition_met (OP
[0]);
2481 trace_output (OP_EX1
);
2485 /* end-sanitize-v850e */
2487 /* start-sanitize-v850eq */
2488 /* sdivun imm5, reg1, reg2, reg3 */
2492 unsigned long long int quotient
;
2493 unsigned long long int remainder
;
2494 unsigned long long int divisor
;
2495 unsigned long long int dividend
;
2496 boolean overflow
= false;
2499 trace_input ("sdivun", OP_IMM_REG_REG_REG
, 0);
2501 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2503 divisor
= State
.regs
[ OP
[0] ] << imm5
;
2504 dividend
= State
.regs
[ OP
[1] ];
2506 State
.regs
[ OP
[1] ] = quotient
= dividend
/ divisor
;
2507 State
.regs
[ OP
[2] >> 11 ] = remainder
= dividend
% divisor
;
2512 quotient
= dividend
;
2515 /* Set condition codes. */
2516 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2518 if (overflow
) PSW
|= PSW_OV
;
2519 if (quotient
== 0) PSW
|= PSW_Z
;
2521 trace_output (OP_IMM_REG_REG_REG
);
2526 /* sdivn imm5, reg1, reg2, reg3 */
2530 signed long long int quotient
;
2531 signed long long int remainder
;
2532 signed long long int divisor
;
2533 signed long long int dividend
;
2534 boolean overflow
= false;
2537 trace_input ("sdivn", OP_IMM_REG_REG_REG
, 0);
2539 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2541 divisor
= State
.regs
[ OP
[0] ] << imm5
;
2542 dividend
= State
.regs
[ OP
[1] ];
2544 State
.regs
[ OP
[1] ] = quotient
= dividend
/ divisor
;
2545 State
.regs
[ OP
[2] >> 11 ] = remainder
= dividend
% divisor
;
2550 quotient
= dividend
;
2553 /* Set condition codes. */
2554 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2556 if (overflow
) PSW
|= PSW_OV
;
2557 if (quotient
== 0) PSW
|= PSW_Z
;
2558 if (quotient
< 0) PSW
|= PSW_S
;
2560 trace_output (OP_IMM_REG_REG_REG
);
2565 /* sdivhun imm5, reg1, reg2, reg3 */
2569 unsigned long long int quotient
;
2570 unsigned long long int remainder
;
2571 unsigned long long int divisor
;
2572 unsigned long long int dividend
;
2573 boolean overflow
= false;
2576 trace_input ("sdivhun", OP_IMM_REG_REG_REG
, 0);
2578 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2580 divisor
= State
.regs
[ OP
[0] ] << imm5
;
2581 dividend
= State
.regs
[ OP
[1] ] & 0xffff;
2583 State
.regs
[ OP
[1] ] = quotient
= dividend
/ divisor
;
2584 State
.regs
[ OP
[2] >> 11 ] = remainder
= dividend
% divisor
;
2589 quotient
= dividend
;
2592 /* Set condition codes. */
2593 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2595 if (overflow
) PSW
|= PSW_OV
;
2596 if (quotient
== 0) PSW
|= PSW_Z
;
2598 trace_output (OP_IMM_REG_REG_REG
);
2603 /* sdivhn imm5, reg1, reg2, reg3 */
2607 signed long long int quotient
;
2608 signed long long int remainder
;
2609 signed long long int divisor
;
2610 signed long long int dividend
;
2611 boolean overflow
= false;
2614 trace_input ("sdivhn", OP_IMM_REG_REG_REG
, 0);
2616 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2618 divisor
= State
.regs
[ OP
[0] ] << imm5
;
2619 dividend
= SEXT16 (State
.regs
[ OP
[1] ]);
2621 State
.regs
[ OP
[1] ] = quotient
= dividend
/ divisor
;
2622 State
.regs
[ OP
[2] >> 11 ] = remainder
= dividend
% divisor
;
2627 quotient
= dividend
;
2630 /* Set condition codes. */
2631 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2633 if (overflow
) PSW
|= PSW_OV
;
2634 if (quotient
== 0) PSW
|= PSW_Z
;
2635 if (quotient
< 0) PSW
|= PSW_S
;
2637 trace_output (OP_IMM_REG_REG_REG
);
2641 /* end-sanitize-v850eq */
2643 /* start-sanitize-v850e */
2644 /* divu reg1, reg2, reg3 */
2645 /* divun imm5, reg1, reg2, reg3 */
2649 unsigned long int quotient
;
2650 unsigned long int remainder
;
2651 unsigned long int divisor
;
2652 unsigned long int dividend
;
2653 boolean overflow
= false;
2655 if ((OP
[3] & 0x3c0000) == 0)
2657 trace_input ("divu", OP_REG_REG_REG
, 0);
2659 /* Compute the result. */
2661 divisor
= State
.regs
[ OP
[0] ];
2662 dividend
= State
.regs
[ OP
[1] ];
2670 State
.regs
[ OP
[1] ] = quotient
= dividend
/ divisor
;
2671 State
.regs
[ OP
[2] >> 11 ] = remainder
= dividend
% divisor
;
2673 /* Set condition codes. */
2674 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2676 if (overflow
) PSW
|= PSW_OV
;
2677 if (quotient
== 0) PSW
|= PSW_Z
;
2679 trace_output (OP_REG_REG_REG
);
2681 /* start-sanitize-v850eq */
2686 trace_input ("divun", OP_IMM_REG_REG_REG
, 0);
2688 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2690 divisor
= State
.regs
[ OP
[0] ];
2691 dividend
= State
.regs
[ OP
[1] ];
2693 State
.regs
[ OP
[1] ] = quotient
= dividend
/ divisor
;
2694 State
.regs
[ OP
[2] >> 11 ] = remainder
= dividend
% divisor
;
2697 || (quotient
> (1 << imm5
))
2698 || (quotient
< (((imm5
& 1) ? 1 : -1) << imm5
)))
2701 quotient
= dividend
;
2704 /* Set condition codes. */
2705 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2707 if (overflow
) PSW
|= PSW_OV
;
2708 if (quotient
== 0) PSW
|= PSW_Z
;
2710 trace_output (OP_IMM_REG_REG_REG
);
2712 /* end-sanitize-v850eq */
2717 /* div reg1, reg2, reg3 */
2718 /* divn imm5, reg1, reg2, reg3 */
2722 signed long int quotient
;
2723 signed long int remainder
;
2724 signed long int divisor
;
2725 signed long int dividend
;
2726 boolean overflow
= false;
2728 if ((OP
[3] & 0x3c0000) == 0)
2730 trace_input ("div", OP_REG_REG_REG
, 0);
2732 /* Compute the result. */
2734 divisor
= State
.regs
[ OP
[0] ];
2735 dividend
= State
.regs
[ OP
[1] ];
2737 if (divisor
== 0 || (divisor
== -1 && dividend
== (1 << 31)))
2743 State
.regs
[ OP
[1] ] = quotient
= dividend
/ divisor
;
2744 State
.regs
[ OP
[2] >> 11 ] = remainder
= dividend
% divisor
;
2746 /* Set condition codes. */
2747 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2749 if (overflow
) PSW
|= PSW_OV
;
2750 if (quotient
== 0) PSW
|= PSW_Z
;
2751 if (quotient
< 0) PSW
|= PSW_S
;
2753 trace_output (OP_REG_REG_REG
);
2755 /* start-sanitize-v850eq */
2760 trace_input ("divn", OP_IMM_REG_REG_REG
, 0);
2762 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2764 divisor
= State
.regs
[ OP
[0] ];
2765 dividend
= State
.regs
[ OP
[1] ];
2767 State
.regs
[ OP
[1] ] = quotient
= dividend
/ divisor
;
2768 State
.regs
[ OP
[2] >> 11 ] = remainder
= dividend
% divisor
;
2771 || (quotient
> (1 << imm5
))
2772 || (divisor
== -1 && dividend
== (1 << 31))
2773 || (quotient
< (((imm5
& 1) ? 1 : -1) << imm5
)))
2776 quotient
= dividend
;
2779 /* Set condition codes. */
2780 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2782 if (overflow
) PSW
|= PSW_OV
;
2783 if (quotient
== 0) PSW
|= PSW_Z
;
2784 if (quotient
< 0) PSW
|= PSW_S
;
2786 trace_output (OP_IMM_REG_REG_REG
);
2788 /* end-sanitize-v850eq */
2793 /* divhu reg1, reg2, reg3 */
2794 /* divhun imm5, reg1, reg2, reg3 */
2798 unsigned long int quotient
;
2799 unsigned long int remainder
;
2800 unsigned long int divisor
;
2801 unsigned long int dividend
;
2802 boolean overflow
= false;
2804 if ((OP
[3] & 0x3c0000) == 0)
2806 trace_input ("divhu", OP_REG_REG_REG
, 0);
2808 /* Compute the result. */
2810 divisor
= State
.regs
[ OP
[0] ];
2811 dividend
= State
.regs
[ OP
[1] ] & 0xffff;
2819 State
.regs
[ OP
[1] ] = quotient
= dividend
/ divisor
;
2820 State
.regs
[ OP
[2] >> 11 ] = remainder
= dividend
% divisor
;
2822 /* Set condition codes. */
2823 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2825 if (overflow
) PSW
|= PSW_OV
;
2826 if (quotient
== 0) PSW
|= PSW_Z
;
2828 trace_output (OP_REG_REG_REG
);
2830 /* start-sanitize-v850eq */
2835 trace_input ("divhun", OP_IMM_REG_REG_REG
, 0);
2837 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2839 divisor
= State
.regs
[ OP
[0] ];
2840 dividend
= State
.regs
[ OP
[1] ] & 0xffff;
2842 State
.regs
[ OP
[1] ] = quotient
= dividend
/ divisor
;
2843 State
.regs
[ OP
[2] >> 11 ] = remainder
= dividend
% divisor
;
2846 || (quotient
> (1 << imm5
))
2847 || (quotient
< (((imm5
& 1) ? 1 : -1) << imm5
)))
2850 quotient
= dividend
;
2853 /* Set condition codes. */
2854 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2856 if (overflow
) PSW
|= PSW_OV
;
2857 if (quotient
== 0) PSW
|= PSW_Z
;
2859 trace_output (OP_IMM_REG_REG_REG
);
2861 /* end-sanitize-v850eq */
2866 /* divh reg1, reg2, reg3 */
2867 /* divhn imm5, reg1, reg2, reg3 */
2871 signed long int quotient
;
2872 signed long int remainder
;
2873 signed long int divisor
;
2874 signed long int dividend
;
2875 boolean overflow
= false;
2877 if ((OP
[3] & 0x3c0000) == 0)
2879 trace_input ("divh", OP_REG_REG_REG
, 0);
2881 /* Compute the result. */
2883 divisor
= State
.regs
[ OP
[0] ];
2884 dividend
= SEXT16 (State
.regs
[ OP
[1] ]);
2886 if (divisor
== 0 || (divisor
== -1 && dividend
== (1 << 31)))
2892 State
.regs
[ OP
[1] ] = quotient
= dividend
/ divisor
;
2893 State
.regs
[ OP
[2] >> 11 ] = remainder
= dividend
% divisor
;
2895 /* Set condition codes. */
2896 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2898 if (overflow
) PSW
|= PSW_OV
;
2899 if (quotient
== 0) PSW
|= PSW_Z
;
2900 if (quotient
< 0) PSW
|= PSW_S
;
2902 trace_output (OP_REG_REG_REG
);
2904 /* start-sanitize-v850eq */
2909 trace_input ("divhn", OP_IMM_REG_REG_REG
, 0);
2911 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2913 divisor
= State
.regs
[ OP
[0] ];
2914 dividend
= SEXT16 (State
.regs
[ OP
[1] ]);
2916 State
.regs
[ OP
[1] ] = quotient
= dividend
/ divisor
;
2917 State
.regs
[ OP
[2] >> 11 ] = remainder
= dividend
% divisor
;
2920 || (quotient
> (1 << imm5
))
2921 || (divisor
== -1 && dividend
== (1 << 31))
2922 || (quotient
< (((imm5
& 1) ? 1 : -1) << imm5
)))
2925 quotient
= dividend
;
2928 /* Set condition codes. */
2929 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2931 if (overflow
) PSW
|= PSW_OV
;
2932 if (quotient
== 0) PSW
|= PSW_Z
;
2933 if (quotient
< 0) PSW
|= PSW_S
;
2935 trace_output (OP_IMM_REG_REG_REG
);
2937 /* end-sanitize-v850eq */
2942 /* mulu imm9, reg2, reg3 */
2946 trace_input ("mulu", OP_IMM_REG_REG
, 0);
2948 Multiply64 (false, (OP
[3] & 0x1f) | ((OP
[3] >> 13) & 0x1e0));
2950 trace_output (OP_IMM_REG_REG
);
2955 /* end-sanitize-v850e */
2957 /* mulu reg1, reg2, reg3 */
2961 trace_input ("mulu", OP_REG_REG_REG
, 0);
2963 Multiply64 (false, State
.regs
[ OP
[0] ]);
2965 trace_output (OP_REG_REG_REG
);
2970 /* start-sanitize-v850e */
2972 /* mul imm9, reg2, reg3 */
2976 trace_input ("mul", OP_IMM_REG_REG
, 0);
2978 Multiply64 (true, (OP
[3] & 0x1f) | ((OP
[3] >> 13) & 0x1e0));
2980 trace_output (OP_IMM_REG_REG
);
2985 /* cmov imm5, reg2, reg3 */
2989 trace_input ("cmov", OP_IMM_REG_REG
, 0);
2991 State
.regs
[ OP
[2] >> 11 ] = condition_met (OP
[0]) ? SEXT5( OP
[0] ) : State
.regs
[ OP
[1] ];
2993 trace_output (OP_IMM_REG_REG
);
3003 trace_input ("ctret", OP_NONE
, 0);
3008 trace_output (OP_NONE
);
3017 unsigned long value
;
3019 trace_input ("hsw", OP_REG_REG3
, 0);
3021 value
= State
.regs
[ OP
[ 1 ] ];
3023 value
|= (State
.regs
[ OP
[ 1 ] ] << 16);
3025 State
.regs
[ OP
[2] >> 11 ] = value
;
3027 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
3029 if (value
== 0) PSW
|= PSW_Z
;
3030 if (value
& 0x80000000) PSW
|= PSW_S
;
3031 if (((value
& 0xffff) == 0) || (value
& 0xffff0000) == 0) PSW
|= PSW_CY
;
3033 trace_output (OP_REG_REG3
);
3038 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
3044 unsigned long value
;
3046 trace_input ("bsw", OP_REG_REG3
, 0);
3048 value
= State
.regs
[ OP
[ 1 ] ];
3050 value
|= (State
.regs
[ OP
[ 1 ] ] << 24);
3051 value
|= ((State
.regs
[ OP
[ 1 ] ] << 8) & 0x00ff0000);
3052 value
|= ((State
.regs
[ OP
[ 1 ] ] >> 8) & 0x0000ff00);
3054 State
.regs
[ OP
[2] >> 11 ] = value
;
3056 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
3058 if (value
== 0) PSW
|= PSW_Z
;
3059 if (value
& 0x80000000) PSW
|= PSW_S
;
3060 if (WORDHASNULLBYTE (value
)) PSW
|= PSW_CY
;
3062 trace_output (OP_REG_REG3
);
3071 unsigned long value
;
3073 trace_input ("bsh", OP_REG_REG3
, 0);
3075 value
= State
.regs
[ OP
[ 1 ] ];
3077 value
|= ((State
.regs
[ OP
[ 1 ] ] << 8) & 0xff00ff00);
3078 value
|= ((State
.regs
[ OP
[ 1 ] ] >> 8) & 0x000000ff);
3080 State
.regs
[ OP
[2] >> 11 ] = value
;
3082 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
3084 if (value
== 0) PSW
|= PSW_Z
;
3085 if (value
& 0x80000000) PSW
|= PSW_S
;
3086 if (((value
& 0xffff) == 0) || (value
& 0xffff0000) == 0) PSW
|= PSW_CY
;
3088 trace_output (OP_REG_REG3
);
3102 trace_input ("pushml", OP_PUSHPOP3
, 0);
3104 if (OP
[3] & (1 << 19))
3108 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
3110 store_mem ((SP
+ 4) & ~ 3, 4, FEPC
);
3111 store_mem ( SP
& ~ 3, 4, FEPSW
);
3115 store_mem ((SP
+ 4) & ~ 3, 4, EIPC
);
3116 store_mem ( SP
& ~ 3, 4, EIPSW
);
3120 if (OP
[3] & (1 << 3))
3124 store_mem (SP
& ~ 3, 4, PSW
);
3127 /* Store the registers with lower number registers being placed at lower addresses. */
3129 if ((OP
[3] & (1 << type3_regs
[ i
])))
3132 store_mem (SP
& ~ 3, 4, State
.regs
[ i
+ 1 ]);
3135 trace_output (OP_PUSHPOP2
);
3141 trace_input ("ld.hu", OP_LOAD32
, 2);
3143 adr
= State
.regs
[ OP
[0] ] + SEXT16 (OP
[2] & ~1);
3146 State
.regs
[ OP
[1] ] = load_mem (adr
, 2);
3148 trace_output (OP_LOAD32
);
3154 /* prepare list12, imm5 */
3163 trace_input ("prepare", OP_PUSHPOP1
, 0);
3165 /* Store the registers with lower number registers being placed at lower addresses. */
3167 if ((OP
[3] & (1 << type1_regs
[ i
])))
3170 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
3173 SP
-= (OP
[3] & 0x3e) << 1;
3175 trace_output (OP_PUSHPOP1
);
3181 trace_input ("ld.bu", OP_LOAD32
, 1);
3183 adr
= State
.regs
[ OP
[0] ] + SEXT16 (OP
[2] & ~1) | ((OP
[3] >> 5) & 1);
3185 State
.regs
[ OP
[1] ] = load_mem (adr
, 1);
3187 trace_output (OP_LOAD32
);
3193 /* prepare list12, imm5, imm32 */
3199 trace_input ("prepare", OP_PUSHPOP1
, 0);
3201 /* Store the registers with lower number registers being placed at lower addresses. */
3203 if ((OP
[3] & (1 << type1_regs
[ i
])))
3206 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
3209 SP
-= (OP
[3] & 0x3e) << 1;
3211 EP
= load_mem (PC
+ 4, 4);
3213 trace_output (OP_PUSHPOP1
);
3218 /* prepare list12, imm5, imm16-32 */
3224 trace_input ("prepare", OP_PUSHPOP1
, 0);
3226 /* Store the registers with lower number registers being placed at lower addresses. */
3228 if ((OP
[3] & (1 << type1_regs
[ i
])))
3231 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
3234 SP
-= (OP
[3] & 0x3e) << 1;
3236 EP
= load_mem (PC
+ 4, 2) << 16;
3238 trace_output (OP_PUSHPOP1
);
3243 /* prepare list12, imm5, imm16 */
3249 trace_input ("prepare", OP_PUSHPOP1
, 0);
3251 /* Store the registers with lower number registers being placed at lower addresses. */
3253 if ((OP
[3] & (1 << type1_regs
[ i
])))
3256 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
3259 SP
-= (OP
[3] & 0x3e) << 1;
3261 EP
= SEXT16 (load_mem (PC
+ 4, 2));
3263 trace_output (OP_PUSHPOP1
);
3268 /* prepare list12, imm5, sp */
3274 trace_input ("prepare", OP_PUSHPOP1
, 0);
3276 /* Store the registers with lower number registers being placed at lower addresses. */
3278 if ((OP
[3] & (1 << type1_regs
[ i
])))
3281 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
3284 SP
-= (OP
[3] & 0x3e) << 1;
3288 trace_output (OP_PUSHPOP1
);
3293 /* end-sanitize-v850e */
3294 /* start-sanitize-v850eq */
3302 trace_input ("popmh", OP_PUSHPOP2
, 0);
3304 /* Load the registers with lower number registers being retrieved from lower addresses. */
3305 for (i
= 0; i
++; i
< 16)
3306 if ((OP
[3] & (1 << type2_regs
[ i
])))
3308 State
.regs
[ i
+ 16 ] = load_mem (SP
& ~ 3, 4);
3312 if (OP
[3] & (1 << 19))
3314 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
3316 FEPSW
= load_mem ( SP
& ~ 3, 4);
3317 FEPC
= load_mem ((SP
+ 4) & ~ 3, 4);
3321 EIPSW
= load_mem ( SP
& ~ 3, 4);
3322 EIPC
= load_mem ((SP
+ 4) & ~ 3, 4);
3328 trace_output (OP_PUSHPOP2
);
3339 trace_input ("popml", OP_PUSHPOP3
, 0);
3341 /* Load the registers with lower number registers being retrieved from lower addresses. */
3342 for (i
= 0; i
++; i
< 15)
3343 if ((OP
[3] & (1 << type3_regs
[ i
])))
3345 State
.regs
[ i
+ 1 ] = load_mem (SP
& ~ 3, 4);
3349 if (OP
[3] & (1 << 3))
3351 PSW
= load_mem (SP
& ~ 3, 4);
3355 if (OP
[3] & (1 << 19))
3357 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
3359 FEPSW
= load_mem ( SP
& ~ 3, 4);
3360 FEPC
= load_mem ((SP
+ 4) & ~ 3, 4);
3364 EIPSW
= load_mem ( SP
& ~ 3, 4);
3365 EIPC
= load_mem ((SP
+ 4) & ~ 3, 4);
3371 trace_output (OP_PUSHPOP2
);
3380 trace_input ("pushmh", OP_PUSHPOP2
, 0);
3382 if (OP
[3] & (1 << 19))
3386 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
3388 store_mem ((SP
+ 4) & ~ 3, 4, FEPC
);
3389 store_mem ( SP
& ~ 3, 4, FEPSW
);
3393 store_mem ((SP
+ 4) & ~ 3, 4, EIPC
);
3394 store_mem ( SP
& ~ 3, 4, EIPSW
);
3398 /* Store the registers with lower number registers being placed at lower addresses. */
3400 if ((OP
[3] & (1 << type2_regs
[ i
])))
3403 store_mem (SP
& ~ 3, 4, State
.regs
[ i
+ 16 ]);
3406 trace_output (OP_PUSHPOP2
);
3411 /* end-sanitize-v850eq */
3412 /* start-sanitize-v850e */
3418 unsigned long result
;
3420 result
= load_mem (State
.regs
[30] + ((OP
[3] & 0xf) << 1), 2);
3422 /* start-sanitize-v850eq */
3424 trace_input ("sld.h", OP_LOAD16
, 2);
3426 State
.regs
[ OP
[1] ] = SEXT16 (result
);
3428 /* end-sanitize-v850eq */
3429 trace_input ("sld.hu", OP_LOAD16
, 2);
3431 State
.regs
[ OP
[1] ] = result
;
3432 /* start-sanitize-v850eq */
3434 /* end-sanitize-v850eq */
3436 trace_output (OP_LOAD16
);
3441 /* cmov reg1, reg2, reg3 */
3445 trace_input ("cmov", OP_REG_REG_REG
, 0);
3447 State
.regs
[ OP
[2] >> 11 ] = condition_met (OP
[0]) ? State
.regs
[ OP
[0] ] : State
.regs
[ OP
[1] ];
3449 trace_output (OP_REG_REG_REG
);
3454 /* mul reg1, reg2, reg3 */
3458 trace_input ("mul", OP_REG_REG_REG
, 0);
3460 Multiply64 (true, State
.regs
[ OP
[0] ]);
3462 trace_output (OP_REG_REG_REG
);
3467 /* end-sanitize-v850e */