128 XXX condition codes. */
132 State
.regs
[OP
[1]] += State
.regs
[OP
[0]];
135 /* add sign_extend(imm5), reg
137 XXX condition codes. */
143 value
= (value
<< 27) >> 27;
145 State
.regs
[OP
[1]] += value
;
148 /* addi sign_extend(imm16), reg, reg
150 XXX condition codes. */
156 value
= (value
<< 16) >> 16;
158 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
163 XXX condition codes */
167 State
.regs
[OP
[1]] -= State
.regs
[OP
[0]];
172 XXX condition codes */
176 State
.regs
[OP
[1]] = State
.regs
[OP
[0]] - State
.regs
[OP
[1]];
181 XXX condition codes */
185 State
.regs
[OP
[1]] = ((State
.regs
[OP
[1]] & 0xffff)
186 * (State
.regs
[OP
[0]] & 0xffff));
189 /* mulh sign_extend(imm5), reg2
197 value
= (value
<< 27) >> 27;
199 State
.regs
[OP
[1]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
202 /* mulhi imm16, reg1, reg2
204 XXX condition codes */
210 value
= value
& 0xffff;
212 State
.regs
[OP
[2]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
218 XXX Is this signed or unsigned? */
222 State
.regs
[OP
[1]] /= (State
.regs
[OP
[0]] & 0xffff);
259 State
.regs
[OP
[1]] = State
.regs
[OP
[0]];
262 /* mov sign_extend(imm5), reg */
268 value
= (value
<< 27) >> 27;
269 State
.regs
[OP
[1]] = value
;
272 /* movea sign_extend(imm16), reg, reg */
279 value
= (value
<< 16) >> 16;
281 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
284 /* movhi imm16, reg, reg */
290 value
= (value
& 0xffff) << 16;
292 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
332 XXX condition codes */
336 State
.regs
[OP
[1]] = ~State
.regs
[OP
[0]];
339 /* sar zero_extend(imm5),reg1
341 XXX condition codes. */
345 int temp
= State
.regs
[OP
[1]];
347 temp
>>= (OP
[0] & 0x1f);
349 State
.regs
[OP
[1]] = temp
;
354 XXX condition codes. */
358 int temp
= State
.regs
[OP
[1]];
360 temp
>>= (State
.regs
[OP
[0]] & 0x1f);
362 State
.regs
[OP
[1]] = temp
;
365 /* shl zero_extend(imm5),reg1
367 XXX condition codes. */
371 State
.regs
[OP
[1]] <<= (OP
[0] & 0x1f);
376 XXX condition codes. */
380 State
.regs
[OP
[1]] <<= (State
.regs
[OP
[0]] & 0x1f);
383 /* shr zero_extend(imm5),reg1
385 XXX condition codes. */
389 State
.regs
[OP
[1]] >>= (OP
[0] & 0x1f);
394 XXX condition codes. */
398 State
.regs
[OP
[1]] >>= (State
.regs
[OP
[0]] & 0x1f);
418 XXX condition codes. */
422 State
.regs
[OP
[1]] |= State
.regs
[OP
[0]];
425 /* ori zero_extend(imm16), reg, reg
427 XXX condition codes */
435 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] | value
;
440 XXX condition codes. */
444 State
.regs
[OP
[1]] &= State
.regs
[OP
[0]];
447 /* andi zero_extend(imm16), reg, reg
449 XXX condition codes. */
457 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] & value
;
462 XXX condition codes. */
466 State
.regs
[OP
[1]] ^= State
.regs
[OP
[0]];
469 /* xori zero_extend(imm16), reg, reg
471 XXX condition codes. */
479 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] ^ value
;
502 /* di, not supported */
509 /* ei, not supported */
516 /* halt, not supported */
523 /* reti, not supported */
530 /* trap, not supportd */
537 /* ldsr, not supported */
544 /* stsr, not supported */