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Fix linux build problem.
[binutils-gdb.git] / sim / v850 / simops.c
1 #include <signal.h>
2 #include "v850_sim.h"
3 #include "simops.h"
4 #include "sys/syscall.h"
5 #include "bfd.h"
6 #include <errno.h>
7 #include <sys/stat.h>
8 #include <sys/times.h>
9 #include <sys/time.h>
10
11 enum op_types {
12 OP_UNKNOWN,
13 OP_NONE,
14 OP_TRAP,
15 OP_REG,
16 OP_REG_REG,
17 OP_REG_REG_CMP,
18 OP_REG_REG_MOVE,
19 OP_IMM_REG,
20 OP_IMM_REG_CMP,
21 OP_IMM_REG_MOVE,
22 OP_COND_BR,
23 OP_LOAD16,
24 OP_STORE16,
25 OP_LOAD32,
26 OP_STORE32,
27 OP_JUMP,
28 OP_IMM_REG_REG,
29 OP_UIMM_REG_REG,
30 OP_BIT,
31 OP_EX1,
32 OP_EX2,
33 OP_LDSR,
34 OP_STSR
35 };
36
37 #ifdef DEBUG
38 static void trace_input PARAMS ((char *name, enum op_types type, int size));
39 static void trace_output PARAMS ((enum op_types result));
40 static int init_text_p = 0;
41 static asection *text;
42 static bfd_vma text_start;
43 static bfd_vma text_end;
44 extern bfd *exec_bfd;
45
46 #ifndef SIZE_INSTRUCTION
47 #define SIZE_INSTRUCTION 6
48 #endif
49
50 #ifndef SIZE_OPERANDS
51 #define SIZE_OPERANDS 16
52 #endif
53
54 #ifndef SIZE_VALUES
55 #define SIZE_VALUES 11
56 #endif
57
58 #ifndef SIZE_LOCATION
59 #define SIZE_LOCATION 40
60 #endif
61
62 static void
63 trace_input (name, type, size)
64 char *name;
65 enum op_types type;
66 int size;
67 {
68 char buf[1024];
69 char *p;
70 uint32 values[3];
71 int num_values, i;
72 char *cond;
73 asection *s;
74 const char *filename;
75 const char *functionname;
76 unsigned int linenumber;
77
78 if ((v850_debug & DEBUG_TRACE) == 0)
79 return;
80
81 buf[0] = '\0';
82 if (!init_text_p)
83 {
84 init_text_p = 1;
85 for (s = exec_bfd->sections; s; s = s->next)
86 if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
87 {
88 text = s;
89 text_start = bfd_get_section_vma (exec_bfd, s);
90 text_end = text_start + bfd_section_size (exec_bfd, s);
91 break;
92 }
93 }
94
95 if (text && PC >= text_start && PC < text_end)
96 {
97 filename = (const char *)0;
98 functionname = (const char *)0;
99 linenumber = 0;
100 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
101 &filename, &functionname, &linenumber))
102 {
103 p = buf;
104 if (linenumber)
105 {
106 sprintf (p, "Line %5d ", linenumber);
107 p += strlen (p);
108 }
109
110 if (functionname)
111 {
112 sprintf (p, "Func %s ", functionname);
113 p += strlen (p);
114 }
115 else if (filename)
116 {
117 char *q = (char *) strrchr (filename, '/');
118 sprintf (p, "File %s ", (q) ? q+1 : filename);
119 p += strlen (p);
120 }
121
122 if (*p == ' ')
123 *p = '\0';
124 }
125 }
126
127 (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
128 (unsigned)PC,
129 SIZE_LOCATION, SIZE_LOCATION, buf,
130 SIZE_INSTRUCTION, name);
131
132 switch (type)
133 {
134 default:
135 case OP_UNKNOWN:
136 case OP_NONE:
137 strcpy (buf, "unknown");
138 break;
139
140 case OP_TRAP:
141 sprintf (buf, "%d", OP[0]);
142 break;
143
144 case OP_REG:
145 sprintf (buf, "r%d", OP[0]);
146 break;
147
148 case OP_REG_REG:
149 case OP_REG_REG_CMP:
150 case OP_REG_REG_MOVE:
151 sprintf (buf, "r%d,r%d", OP[0], OP[1]);
152 break;
153
154 case OP_IMM_REG:
155 case OP_IMM_REG_CMP:
156 case OP_IMM_REG_MOVE:
157 sprintf (buf, "%d,r%d", OP[0], OP[1]);
158 break;
159
160 case OP_COND_BR:
161 sprintf (buf, "%d", SEXT9 (OP[0]));
162 break;
163
164 case OP_LOAD16:
165 sprintf (buf, "%d[r30],r%d", OP[1] * size, OP[0]);
166 break;
167
168 case OP_STORE16:
169 sprintf (buf, "r%d,%d[r30]", OP[0], OP[1] * size);
170 break;
171
172 case OP_LOAD32:
173 sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
174 break;
175
176 case OP_STORE32:
177 sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
178 break;
179
180 case OP_JUMP:
181 sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
182 break;
183
184 case OP_IMM_REG_REG:
185 sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
186 break;
187
188 case OP_UIMM_REG_REG:
189 sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
190 break;
191
192 case OP_BIT:
193 sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
194 break;
195
196 case OP_EX1:
197 switch (OP[0] & 0xf)
198 {
199 default: cond = "?"; break;
200 case 0x0: cond = "v"; break;
201 case 0x1: cond = "c"; break;
202 case 0x2: cond = "z"; break;
203 case 0x3: cond = "nh"; break;
204 case 0x4: cond = "s"; break;
205 case 0x5: cond = "t"; break;
206 case 0x6: cond = "lt"; break;
207 case 0x7: cond = "le"; break;
208 case 0x8: cond = "nv"; break;
209 case 0x9: cond = "nc"; break;
210 case 0xa: cond = "nz"; break;
211 case 0xb: cond = "h"; break;
212 case 0xc: cond = "ns"; break;
213 case 0xd: cond = "sa"; break;
214 case 0xe: cond = "ge"; break;
215 case 0xf: cond = "gt"; break;
216 }
217
218 sprintf (buf, "%s,r%d", cond, OP[1]);
219 break;
220
221 case OP_EX2:
222 strcpy (buf, "EX2");
223 break;
224
225 case OP_LDSR:
226 case OP_STSR:
227 sprintf (buf, "r%d,s%d", OP[0], OP[1]);
228 break;
229 }
230
231 if ((v850_debug & DEBUG_VALUES) == 0)
232 {
233 (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
234 }
235 else
236 {
237 (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
238 switch (type)
239 {
240 default:
241 case OP_UNKNOWN:
242 case OP_NONE:
243 case OP_TRAP:
244 num_values = 0;
245 break;
246
247 case OP_REG:
248 case OP_REG_REG_MOVE:
249 values[0] = State.regs[OP[0]];
250 num_values = 1;
251 break;
252
253 case OP_REG_REG:
254 case OP_REG_REG_CMP:
255 values[0] = State.regs[OP[1]];
256 values[1] = State.regs[OP[0]];
257 num_values = 2;
258 break;
259
260 case OP_IMM_REG:
261 case OP_IMM_REG_CMP:
262 values[0] = SEXT5 (OP[0]);
263 values[1] = OP[1];
264 num_values = 2;
265 break;
266
267 case OP_IMM_REG_MOVE:
268 values[0] = SEXT5 (OP[0]);
269 num_values = 1;
270 break;
271
272 case OP_COND_BR:
273 values[0] = State.pc;
274 values[1] = SEXT9 (OP[0]);
275 values[2] = State.sregs[5];
276 num_values = 3;
277 break;
278
279 case OP_LOAD16:
280 values[0] = OP[1] * size;
281 values[1] = State.regs[30];
282 num_values = 2;
283 break;
284
285 case OP_STORE16:
286 values[0] = State.regs[OP[0]];
287 values[1] = OP[1] * size;
288 values[2] = State.regs[30];
289 num_values = 3;
290 break;
291
292 case OP_LOAD32:
293 values[0] = SEXT16 (OP[2]);
294 values[1] = State.regs[OP[0]];
295 num_values = 2;
296 break;
297
298 case OP_STORE32:
299 values[0] = State.regs[OP[1]];
300 values[1] = SEXT16 (OP[2]);
301 values[2] = State.regs[OP[0]];
302 num_values = 3;
303 break;
304
305 case OP_JUMP:
306 values[0] = SEXT22 (OP[0]);
307 values[1] = State.pc;
308 num_values = 2;
309 break;
310
311 case OP_IMM_REG_REG:
312 values[0] = SEXT16 (OP[0]) << size;
313 values[1] = State.regs[OP[1]];
314 num_values = 2;
315 break;
316
317 case OP_UIMM_REG_REG:
318 values[0] = (OP[0] & 0xffff) << size;
319 values[1] = State.regs[OP[1]];
320 num_values = 2;
321 break;
322
323 case OP_BIT:
324 num_values = 0;
325 break;
326
327 case OP_EX1:
328 values[0] = State.sregs[5];
329 num_values = 1;
330 break;
331
332 case OP_EX2:
333 num_values = 0;
334 break;
335
336 case OP_LDSR:
337 values[0] = State.regs[OP[0]];
338 num_values = 1;
339 break;
340
341 case OP_STSR:
342 values[0] = State.sregs[OP[1]];
343 num_values = 1;
344 }
345
346 for (i = 0; i < num_values; i++)
347 (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
348
349 while (i++ < 3)
350 (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
351 }
352 }
353
354 static void
355 trace_output (result)
356 enum op_types result;
357 {
358 if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
359 {
360 switch (result)
361 {
362 default:
363 case OP_UNKNOWN:
364 case OP_NONE:
365 case OP_TRAP:
366 case OP_REG:
367 case OP_REG_REG_CMP:
368 case OP_IMM_REG_CMP:
369 case OP_COND_BR:
370 case OP_STORE16:
371 case OP_STORE32:
372 case OP_BIT:
373 case OP_EX2:
374 break;
375
376 case OP_LOAD16:
377 case OP_STSR:
378 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
379 (unsigned long)State.regs[OP[0]]);
380 break;
381
382 case OP_REG_REG:
383 case OP_REG_REG_MOVE:
384 case OP_IMM_REG:
385 case OP_IMM_REG_MOVE:
386 case OP_LOAD32:
387 case OP_EX1:
388 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
389 (unsigned long)State.regs[OP[1]]);
390 break;
391
392 case OP_IMM_REG_REG:
393 case OP_UIMM_REG_REG:
394 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
395 (unsigned long)State.regs[OP[2]]);
396 break;
397
398 case OP_JUMP:
399 if (OP[1] != 0)
400 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
401 (unsigned long)State.regs[OP[1]]);
402 break;
403
404 case OP_LDSR:
405 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
406 (unsigned long)State.sregs[OP[1]]);
407 break;
408 }
409
410 (*v850_callback->printf_filtered) (v850_callback, "\n");
411 }
412 }
413
414 #else
415 #define trace_input(NAME, IN1, IN2)
416 #define trace_output(RESULT)
417 #endif
418
419 \f
420 /* sld.b */
421 void
422 OP_300 ()
423 {
424 unsigned int op2;
425 int result, temp;
426
427 trace_input ("sld.b", OP_LOAD16, 1);
428 temp = OP[1];
429 temp &= 0x7f;
430 op2 = temp;
431 result = load_mem (State.regs[30] + op2, 1);
432 State.regs[OP[0]] = SEXT8 (result);
433 trace_output (OP_LOAD16);
434 }
435
436 /* sld.h */
437 void
438 OP_400 ()
439 {
440 unsigned int op2;
441 int result, temp;
442
443 trace_input ("sld.h", OP_LOAD16, 2);
444 temp = OP[1];
445 temp &= 0x7f;
446 op2 = temp << 1;
447 result = load_mem (State.regs[30] + op2, 2);
448 State.regs[OP[0]] = SEXT16 (result);
449 trace_output (OP_LOAD16);
450 }
451
452 /* sld.w */
453 void
454 OP_500 ()
455 {
456 unsigned int op2;
457 int result, temp;
458
459 trace_input ("sld.w", OP_LOAD16, 4);
460 temp = OP[1];
461 temp &= 0x7e;
462 op2 = temp << 1;
463 result = load_mem (State.regs[30] + op2, 4);
464 State.regs[OP[0]] = result;
465 trace_output (OP_LOAD16);
466 }
467
468 /* sst.b */
469 void
470 OP_380 ()
471 {
472 unsigned int op0, op1;
473 int temp;
474
475 trace_input ("sst.b", OP_STORE16, 1);
476 op0 = State.regs[OP[0]];
477 temp = OP[1];
478 temp &= 0x7f;
479 op1 = temp;
480 store_mem (State.regs[30] + op1, 1, op0);
481 trace_output (OP_STORE16);
482 }
483
484 /* sst.h */
485 void
486 OP_480 ()
487 {
488 unsigned int op0, op1;
489 int temp;
490
491 trace_input ("sst.h", OP_STORE16, 2);
492 op0 = State.regs[OP[0]];
493 temp = OP[1];
494 temp &= 0x7f;
495 op1 = temp << 1;
496 store_mem (State.regs[30] + op1, 2, op0);
497 trace_output (OP_STORE16);
498 }
499
500 /* sst.w */
501 void
502 OP_501 ()
503 {
504 unsigned int op0, op1;
505 int temp;
506
507 trace_input ("sst.w", OP_STORE16, 4);
508 op0 = State.regs[OP[0]];
509 temp = OP[1];
510 temp &= 0x7e;
511 op1 = temp << 1;
512 store_mem (State.regs[30] + op1, 4, op0);
513 trace_output (OP_STORE16);
514 }
515
516 /* ld.b */
517 void
518 OP_700 ()
519 {
520 unsigned int op0, op2;
521 int result, temp;
522
523 trace_input ("ld.b", OP_LOAD32, 1);
524 op0 = State.regs[OP[0]];
525 temp = SEXT16 (OP[2]);
526 op2 = temp;
527 result = load_mem (op0 + op2, 1);
528 State.regs[OP[1]] = SEXT8 (result);
529 trace_output (OP_LOAD32);
530 }
531
532 /* ld.h */
533 void
534 OP_720 ()
535 {
536 unsigned int op0, op2;
537 int result, temp;
538
539 trace_input ("ld.h", OP_LOAD32, 2);
540 op0 = State.regs[OP[0]];
541 temp = SEXT16 (OP[2]);
542 temp &= ~0x1;
543 op2 = temp;
544 result = load_mem (op0 + op2, 2);
545 State.regs[OP[1]] = SEXT16 (result);
546 trace_output (OP_LOAD32);
547 }
548
549 /* ld.w */
550 void
551 OP_10720 ()
552 {
553 unsigned int op0, op2;
554 int result, temp;
555
556 trace_input ("ld.w", OP_LOAD32, 4);
557 op0 = State.regs[OP[0]];
558 temp = SEXT16 (OP[2]);
559 temp &= ~0x1;
560 op2 = temp;
561 result = load_mem (op0 + op2, 4);
562 State.regs[OP[1]] = result;
563 trace_output (OP_LOAD32);
564 }
565
566 /* st.b */
567 void
568 OP_740 ()
569 {
570 unsigned int op0, op1, op2;
571 int temp;
572
573 trace_input ("st.b", OP_STORE32, 1);
574 op0 = State.regs[OP[0]];
575 op1 = State.regs[OP[1]];
576 temp = SEXT16 (OP[2]);
577 op2 = temp;
578 store_mem (op0 + op2, 1, op1);
579 trace_output (OP_STORE32);
580 }
581
582 /* st.h */
583 void
584 OP_760 ()
585 {
586 unsigned int op0, op1, op2;
587 int temp;
588
589 trace_input ("st.h", OP_STORE32, 2);
590 op0 = State.regs[OP[0]];
591 op1 = State.regs[OP[1]];
592 temp = SEXT16 (OP[2] & ~0x1);
593 op2 = temp;
594 store_mem (op0 + op2, 2, op1);
595 trace_output (OP_STORE32);
596 }
597
598 /* st.w */
599 void
600 OP_10760 ()
601 {
602 unsigned int op0, op1, op2;
603 int temp;
604
605 trace_input ("st.w", OP_STORE32, 4);
606 op0 = State.regs[OP[0]];
607 op1 = State.regs[OP[1]];
608 temp = SEXT16 (OP[2] & ~0x1);
609 op2 = temp;
610 store_mem (op0 + op2, 4, op1);
611 trace_output (OP_STORE32);
612 }
613
614 /* bv disp9 */
615 void
616 OP_580 ()
617 {
618 unsigned int psw;
619 int op0;
620
621 trace_input ("bv", OP_COND_BR, 0);
622 op0 = SEXT9 (OP[0]);
623 psw = State.sregs[5];
624
625 if ((psw & PSW_OV) != 0)
626 State.pc += op0;
627 else
628 State.pc += 2;
629 trace_output (OP_COND_BR);
630 }
631
632 /* bl disp9 */
633 void
634 OP_581 ()
635 {
636 unsigned int psw;
637 int op0;
638
639 trace_input ("bl", OP_COND_BR, 0);
640 op0 = SEXT9 (OP[0]);
641 psw = State.sregs[5];
642
643 if ((psw & PSW_CY) != 0)
644 State.pc += op0;
645 else
646 State.pc += 2;
647 trace_output (OP_COND_BR);
648 }
649
650 /* be disp9 */
651 void
652 OP_582 ()
653 {
654 unsigned int psw;
655 int op0;
656
657 trace_input ("be", OP_COND_BR, 0);
658 op0 = SEXT9 (OP[0]);
659 psw = State.sregs[5];
660
661 if ((psw & PSW_Z) != 0)
662 State.pc += op0;
663 else
664 State.pc += 2;
665 trace_output (OP_COND_BR);
666 }
667
668 /* bnh disp 9*/
669 void
670 OP_583 ()
671 {
672 unsigned int psw;
673 int op0;
674
675 trace_input ("bnh", OP_COND_BR, 0);
676 op0 = SEXT9 (OP[0]);
677 psw = State.sregs[5];
678
679 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
680 State.pc += op0;
681 else
682 State.pc += 2;
683 trace_output (OP_COND_BR);
684 }
685
686 /* bn disp9 */
687 void
688 OP_584 ()
689 {
690 unsigned int psw;
691 int op0;
692
693 trace_input ("bn", OP_COND_BR, 0);
694 op0 = SEXT9 (OP[0]);
695 psw = State.sregs[5];
696
697 if ((psw & PSW_S) != 0)
698 State.pc += op0;
699 else
700 State.pc += 2;
701 trace_output (OP_COND_BR);
702 }
703
704 /* br disp9 */
705 void
706 OP_585 ()
707 {
708 unsigned int psw;
709 int op0;
710
711 trace_input ("br", OP_COND_BR, 0);
712 op0 = SEXT9 (OP[0]);
713 State.pc += op0;
714 trace_output (OP_COND_BR);
715 }
716
717 /* blt disp9 */
718 void
719 OP_586 ()
720 {
721 unsigned int psw;
722 int op0;
723
724 trace_input ("blt", OP_COND_BR, 0);
725 op0 = SEXT9 (OP[0]);
726 psw = State.sregs[5];
727
728 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
729 State.pc += op0;
730 else
731 State.pc += 2;
732 trace_output (OP_COND_BR);
733 }
734
735 /* ble disp9 */
736 void
737 OP_587 ()
738 {
739 unsigned int psw;
740 int op0;
741
742 trace_input ("ble", OP_COND_BR, 0);
743 op0 = SEXT9 (OP[0]);
744 psw = State.sregs[5];
745
746 if ((((psw & PSW_Z) != 0)
747 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
748 State.pc += op0;
749 else
750 State.pc += 2;
751 trace_output (OP_COND_BR);
752 }
753
754 /* bnv disp9 */
755 void
756 OP_588 ()
757 {
758 unsigned int psw;
759 int op0;
760
761 trace_input ("bnv", OP_COND_BR, 0);
762 op0 = SEXT9 (OP[0]);
763 psw = State.sregs[5];
764
765 if ((psw & PSW_OV) == 0)
766 State.pc += op0;
767 else
768 State.pc += 2;
769 trace_output (OP_COND_BR);
770 }
771
772 /* bnl disp9 */
773 void
774 OP_589 ()
775 {
776 unsigned int psw;
777 int op0;
778
779 trace_input ("bnl", OP_COND_BR, 0);
780 op0 = SEXT9 (OP[0]);
781 psw = State.sregs[5];
782
783 if ((psw & PSW_CY) == 0)
784 State.pc += op0;
785 else
786 State.pc += 2;
787 trace_output (OP_COND_BR);
788 }
789
790 /* bne disp9 */
791 void
792 OP_58A ()
793 {
794 unsigned int psw;
795 int op0;
796
797 trace_input ("bne", OP_COND_BR, 0);
798 op0 = SEXT9 (OP[0]);
799 psw = State.sregs[5];
800
801 if ((psw & PSW_Z) == 0)
802 State.pc += op0;
803 else
804 State.pc += 2;
805 trace_output (OP_COND_BR);
806 }
807
808 /* bh disp9 */
809 void
810 OP_58B ()
811 {
812 unsigned int psw;
813 int op0;
814
815 trace_input ("bh", OP_COND_BR, 0);
816 op0 = SEXT9 (OP[0]);
817 psw = State.sregs[5];
818
819 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
820 State.pc += op0;
821 else
822 State.pc += 2;
823 trace_output (OP_COND_BR);
824 }
825
826 /* bp disp9 */
827 void
828 OP_58C ()
829 {
830 unsigned int psw;
831 int op0;
832
833 trace_input ("bp", OP_COND_BR, 0);
834 op0 = SEXT9 (OP[0]);
835 psw = State.sregs[5];
836
837 if ((psw & PSW_S) == 0)
838 State.pc += op0;
839 else
840 State.pc += 2;
841 trace_output (OP_COND_BR);
842 }
843
844 /* bsa disp9 */
845 void
846 OP_58D ()
847 {
848 unsigned int psw;
849 int op0;
850
851 trace_input ("bsa", OP_COND_BR, 0);
852 op0 = SEXT9 (OP[0]);
853 psw = State.sregs[5];
854
855 if ((psw & PSW_SAT) != 0)
856 State.pc += op0;
857 else
858 State.pc += 2;
859 trace_output (OP_COND_BR);
860 }
861
862 /* bge disp9 */
863 void
864 OP_58E ()
865 {
866 unsigned int psw;
867 int op0;
868
869 trace_input ("bge", OP_COND_BR, 0);
870 op0 = SEXT9 (OP[0]);
871 psw = State.sregs[5];
872
873 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
874 State.pc += op0;
875 else
876 State.pc += 2;
877 trace_output (OP_COND_BR);
878 }
879
880 /* bgt disp9 */
881 void
882 OP_58F ()
883 {
884 unsigned int psw;
885 int op0;
886
887 trace_input ("bgt", OP_COND_BR, 0);
888 op0 = SEXT9 (OP[0]);
889 psw = State.sregs[5];
890
891 if ((((psw & PSW_Z) != 0)
892 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
893 State.pc += op0;
894 else
895 State.pc += 2;
896 trace_output (OP_COND_BR);
897 }
898
899 /* jmp [reg1] */
900 void
901 OP_60 ()
902 {
903 /* interp.c will bump this by +2, so correct for it here. */
904 trace_input ("jmp", OP_REG, 0);
905 State.pc = State.regs[OP[0]] - 2;
906 trace_output (OP_REG);
907 }
908
909 /* jarl disp22, reg */
910 void
911 OP_780 ()
912 {
913 unsigned int op0, opc;
914 int temp;
915
916 trace_input ("jarl", OP_JUMP, 0);
917 temp = SEXT22 (OP[0]);
918 op0 = temp;
919 opc = State.pc;
920
921 State.pc += temp;
922
923 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
924 if (OP[1] != 0)
925 State.regs[OP[1]] = opc + 4;
926 trace_output (OP_JUMP);
927 }
928
929 /* add reg, reg */
930 void
931 OP_1C0 ()
932 {
933 unsigned int op0, op1, result, z, s, cy, ov;
934
935 trace_input ("add", OP_REG_REG, 0);
936 /* Compute the result. */
937 op0 = State.regs[OP[0]];
938 op1 = State.regs[OP[1]];
939 result = op0 + op1;
940
941 /* Compute the condition codes. */
942 z = (result == 0);
943 s = (result & 0x80000000);
944 cy = (result < op0 || result < op1);
945 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
946 && (op0 & 0x80000000) != (result & 0x80000000));
947
948 /* Store the result and condition codes. */
949 State.regs[OP[1]] = result;
950 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
951 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
952 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
953 trace_output (OP_REG_REG);
954 }
955
956 /* add sign_extend(imm5), reg */
957 void
958 OP_240 ()
959 {
960 unsigned int op0, op1, result, z, s, cy, ov;
961 int temp;
962
963 trace_input ("add", OP_IMM_REG, 0);
964
965 /* Compute the result. */
966 temp = SEXT5 (OP[0]);
967 op0 = temp;
968 op1 = State.regs[OP[1]];
969 result = op0 + op1;
970
971 /* Compute the condition codes. */
972 z = (result == 0);
973 s = (result & 0x80000000);
974 cy = (result < op0 || result < op1);
975 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
976 && (op0 & 0x80000000) != (result & 0x80000000));
977
978 /* Store the result and condition codes. */
979 State.regs[OP[1]] = result;
980 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
981 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
982 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
983 trace_output (OP_IMM_REG);
984 }
985
986 /* addi sign_extend(imm16), reg, reg */
987 void
988 OP_600 ()
989 {
990 unsigned int op0, op1, result, z, s, cy, ov;
991 int temp;
992
993 trace_input ("addi", OP_IMM_REG_REG, 0);
994
995 /* Compute the result. */
996 temp = SEXT16 (OP[0]);
997 op0 = temp;
998 op1 = State.regs[OP[1]];
999 result = op0 + op1;
1000
1001 /* Compute the condition codes. */
1002 z = (result == 0);
1003 s = (result & 0x80000000);
1004 cy = (result < op0 || result < op1);
1005 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1006 && (op0 & 0x80000000) != (result & 0x80000000));
1007
1008 /* Store the result and condition codes. */
1009 State.regs[OP[2]] = result;
1010 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1011 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1012 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1013 trace_output (OP_IMM_REG_REG);
1014 }
1015
1016 /* sub reg1, reg2 */
1017 void
1018 OP_1A0 ()
1019 {
1020 unsigned int op0, op1, result, z, s, cy, ov;
1021
1022 trace_input ("sub", OP_REG_REG, 0);
1023 /* Compute the result. */
1024 op0 = State.regs[OP[0]];
1025 op1 = State.regs[OP[1]];
1026 result = op1 - op0;
1027
1028 /* Compute the condition codes. */
1029 z = (result == 0);
1030 s = (result & 0x80000000);
1031 cy = (op1 < op0);
1032 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1033 && (op1 & 0x80000000) != (result & 0x80000000));
1034
1035 /* Store the result and condition codes. */
1036 State.regs[OP[1]] = result;
1037 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1038 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1039 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1040 trace_output (OP_REG_REG);
1041 }
1042
1043 /* subr reg1, reg2 */
1044 void
1045 OP_180 ()
1046 {
1047 unsigned int op0, op1, result, z, s, cy, ov;
1048
1049 trace_input ("subr", OP_REG_REG, 0);
1050 /* Compute the result. */
1051 op0 = State.regs[OP[0]];
1052 op1 = State.regs[OP[1]];
1053 result = op0 - op1;
1054
1055 /* Compute the condition codes. */
1056 z = (result == 0);
1057 s = (result & 0x80000000);
1058 cy = (op0 < op1);
1059 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1060 && (op0 & 0x80000000) != (result & 0x80000000));
1061
1062 /* Store the result and condition codes. */
1063 State.regs[OP[1]] = result;
1064 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1065 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1066 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1067 trace_output (OP_REG_REG);
1068 }
1069
1070 /* mulh reg1, reg2 */
1071 void
1072 OP_E0 ()
1073 {
1074 trace_input ("mulh", OP_REG_REG, 0);
1075 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
1076 * (State.regs[OP[0]] & 0xffff));
1077 trace_output (OP_REG_REG);
1078 }
1079
1080 /* mulh sign_extend(imm5), reg2
1081
1082 Condition codes */
1083 void
1084 OP_2E0 ()
1085 {
1086 int value = SEXT5 (OP[0]);
1087
1088 trace_input ("mulh", OP_IMM_REG, 0);
1089 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
1090 trace_output (OP_IMM_REG);
1091 }
1092
1093 /* mulhi imm16, reg1, reg2 */
1094 void
1095 OP_6E0 ()
1096 {
1097 int value = OP[0] & 0xffff;
1098
1099 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1100 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
1101 trace_output (OP_IMM_REG_REG);
1102 }
1103
1104 /* divh reg1, reg2 */
1105 void
1106 OP_40 ()
1107 {
1108 unsigned int op0, op1, result, ov, s, z;
1109 int temp;
1110
1111 trace_input ("divh", OP_REG_REG, 0);
1112
1113 /* Compute the result. */
1114 temp = SEXT16 (State.regs[OP[0]]);
1115 op0 = temp;
1116 op1 = State.regs[OP[1]];
1117
1118 if (op0 == 0xffffffff && op1 == 0x80000000)
1119 {
1120 result = 0x80000000;
1121 ov = 1;
1122 }
1123 else if (op0 != 0)
1124 {
1125 result = op1 / op0;
1126 ov = 0;
1127 }
1128 else
1129 {
1130 result = 0x0;
1131 ov = 1;
1132 }
1133
1134 /* Compute the condition codes. */
1135 z = (result == 0);
1136 s = (result & 0x80000000);
1137
1138 /* Store the result and condition codes. */
1139 State.regs[OP[1]] = result;
1140 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1141 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1142 | (ov ? PSW_OV : 0));
1143 trace_output (OP_REG_REG);
1144 }
1145
1146 /* cmp reg, reg */
1147 void
1148 OP_1E0 ()
1149 {
1150 unsigned int op0, op1, result, z, s, cy, ov;
1151
1152 trace_input ("cmp", OP_REG_REG_CMP, 0);
1153 /* Compute the result. */
1154 op0 = State.regs[OP[0]];
1155 op1 = State.regs[OP[1]];
1156 result = op1 - op0;
1157
1158 /* Compute the condition codes. */
1159 z = (result == 0);
1160 s = (result & 0x80000000);
1161 cy = (op1 < op0);
1162 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1163 && (op1 & 0x80000000) != (result & 0x80000000));
1164
1165 /* Set condition codes. */
1166 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1167 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1168 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1169 trace_output (OP_REG_REG_CMP);
1170 }
1171
1172 /* cmp sign_extend(imm5), reg */
1173 void
1174 OP_260 ()
1175 {
1176 unsigned int op0, op1, result, z, s, cy, ov;
1177 int temp;
1178
1179 /* Compute the result. */
1180 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1181 temp = SEXT5 (OP[0]);
1182 op0 = temp;
1183 op1 = State.regs[OP[1]];
1184 result = op1 - op0;
1185
1186 /* Compute the condition codes. */
1187 z = (result == 0);
1188 s = (result & 0x80000000);
1189 cy = (op1 < op0);
1190 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1191 && (op1 & 0x80000000) != (result & 0x80000000));
1192
1193 /* Set condition codes. */
1194 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1195 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1196 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1197 trace_output (OP_IMM_REG_CMP);
1198 }
1199
1200 /* setf cccc,reg2 */
1201 void
1202 OP_7E0 ()
1203 {
1204 /* Hack alert. We turn off a bit in op0 since we really only
1205 wanted 4 bits. */
1206 unsigned int op0, psw, result = 0;
1207
1208 trace_input ("setf", OP_EX1, 0);
1209 op0 = OP[0] & 0xf;
1210 psw = State.sregs[5];
1211
1212 switch (op0)
1213 {
1214 case 0x0:
1215 result = ((psw & PSW_OV) != 0);
1216 break;
1217 case 0x1:
1218 result = ((psw & PSW_CY) != 0);
1219 break;
1220 case 0x2:
1221 result = ((psw & PSW_Z) != 0);
1222 break;
1223 case 0x3:
1224 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
1225 break;
1226 case 0x4:
1227 result = ((psw & PSW_S) != 0);
1228 break;
1229 case 0x5:
1230 result = 1;
1231 break;
1232 case 0x6:
1233 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
1234 break;
1235 case 0x7:
1236 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
1237 || ((psw & PSW_Z) != 0)) != 0);
1238 break;
1239 case 0x8:
1240 result = ((psw & PSW_OV) == 0);
1241 break;
1242 case 0x9:
1243 result = ((psw & PSW_CY) == 0);
1244 break;
1245 case 0xa:
1246 result = ((psw & PSW_Z) == 0);
1247 break;
1248 case 0xb:
1249 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
1250 break;
1251 case 0xc:
1252 result = ((psw & PSW_S) == 0);
1253 break;
1254 case 0xd:
1255 result = ((psw & PSW_SAT) != 0);
1256 break;
1257 case 0xe:
1258 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
1259 break;
1260 case 0xf:
1261 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
1262 || ((psw & PSW_Z) != 0)) == 0);
1263 break;
1264 }
1265
1266 State.regs[OP[1]] = result;
1267 trace_output (OP_EX1);
1268 }
1269
1270 /* satadd reg,reg */
1271 void
1272 OP_C0 ()
1273 {
1274 unsigned int op0, op1, result, z, s, cy, ov, sat;
1275
1276 trace_input ("satadd", OP_REG_REG, 0);
1277 /* Compute the result. */
1278 op0 = State.regs[OP[0]];
1279 op1 = State.regs[OP[1]];
1280 result = op0 + op1;
1281
1282 /* Compute the condition codes. */
1283 z = (result == 0);
1284 s = (result & 0x80000000);
1285 cy = (result < op0 || result < op1);
1286 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1287 && (op0 & 0x80000000) != (result & 0x80000000));
1288 sat = ov;
1289
1290 /* Store the result and condition codes. */
1291 State.regs[OP[1]] = result;
1292 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1293 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1294 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1295 | (sat ? PSW_SAT : 0));
1296
1297 /* Handle saturated results. */
1298 if (sat && s)
1299 State.regs[OP[1]] = 0x80000000;
1300 else if (sat)
1301 State.regs[OP[1]] = 0x7fffffff;
1302 trace_output (OP_REG_REG);
1303 }
1304
1305 /* satadd sign_extend(imm5), reg */
1306 void
1307 OP_220 ()
1308 {
1309 unsigned int op0, op1, result, z, s, cy, ov, sat;
1310
1311 int temp;
1312
1313 trace_input ("satadd", OP_IMM_REG, 0);
1314
1315 /* Compute the result. */
1316 temp = SEXT5 (OP[0]);
1317 op0 = temp;
1318 op1 = State.regs[OP[1]];
1319 result = op0 + op1;
1320
1321 /* Compute the condition codes. */
1322 z = (result == 0);
1323 s = (result & 0x80000000);
1324 cy = (result < op0 || result < op1);
1325 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1326 && (op0 & 0x80000000) != (result & 0x80000000));
1327 sat = ov;
1328
1329 /* Store the result and condition codes. */
1330 State.regs[OP[1]] = result;
1331 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1332 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1333 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1334 | (sat ? PSW_SAT : 0));
1335
1336 /* Handle saturated results. */
1337 if (sat && s)
1338 State.regs[OP[1]] = 0x80000000;
1339 else if (sat)
1340 State.regs[OP[1]] = 0x7fffffff;
1341 trace_output (OP_IMM_REG);
1342 }
1343
1344 /* satsub reg1, reg2 */
1345 void
1346 OP_A0 ()
1347 {
1348 unsigned int op0, op1, result, z, s, cy, ov, sat;
1349
1350 trace_input ("satsub", OP_REG_REG, 0);
1351
1352 /* Compute the result. */
1353 op0 = State.regs[OP[0]];
1354 op1 = State.regs[OP[1]];
1355 result = op1 - op0;
1356
1357 /* Compute the condition codes. */
1358 z = (result == 0);
1359 s = (result & 0x80000000);
1360 cy = (op1 < op0);
1361 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1362 && (op1 & 0x80000000) != (result & 0x80000000));
1363 sat = ov;
1364
1365 /* Store the result and condition codes. */
1366 State.regs[OP[1]] = result;
1367 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1368 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1369 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1370 | (sat ? PSW_SAT : 0));
1371
1372 /* Handle saturated results. */
1373 if (sat && s)
1374 State.regs[OP[1]] = 0x80000000;
1375 else if (sat)
1376 State.regs[OP[1]] = 0x7fffffff;
1377 trace_output (OP_REG_REG);
1378 }
1379
1380 /* satsubi sign_extend(imm16), reg */
1381 void
1382 OP_660 ()
1383 {
1384 unsigned int op0, op1, result, z, s, cy, ov, sat;
1385 int temp;
1386
1387 trace_input ("satsubi", OP_IMM_REG, 0);
1388
1389 /* Compute the result. */
1390 temp = SEXT16 (OP[0]);
1391 op0 = temp;
1392 op1 = State.regs[OP[1]];
1393 result = op1 - op0;
1394
1395 /* Compute the condition codes. */
1396 z = (result == 0);
1397 s = (result & 0x80000000);
1398 cy = (op1 < op0);
1399 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1400 && (op1 & 0x80000000) != (result & 0x80000000));
1401 sat = ov;
1402
1403 /* Store the result and condition codes. */
1404 State.regs[OP[1]] = result;
1405 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1406 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1407 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1408 | (sat ? PSW_SAT : 0));
1409
1410 /* Handle saturated results. */
1411 if (sat && s)
1412 State.regs[OP[1]] = 0x80000000;
1413 else if (sat)
1414 State.regs[OP[1]] = 0x7fffffff;
1415 trace_output (OP_IMM_REG);
1416 }
1417
1418 /* satsubr reg,reg */
1419 void
1420 OP_80 ()
1421 {
1422 unsigned int op0, op1, result, z, s, cy, ov, sat;
1423
1424 trace_input ("satsubr", OP_REG_REG, 0);
1425
1426 /* Compute the result. */
1427 op0 = State.regs[OP[0]];
1428 op1 = State.regs[OP[1]];
1429 result = op0 - op1;
1430
1431 /* Compute the condition codes. */
1432 z = (result == 0);
1433 s = (result & 0x80000000);
1434 cy = (result < op0);
1435 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1436 && (op1 & 0x80000000) != (result & 0x80000000));
1437 sat = ov;
1438
1439 /* Store the result and condition codes. */
1440 State.regs[OP[1]] = result;
1441 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1442 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1443 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1444 | (sat ? PSW_SAT : 0));
1445
1446 /* Handle saturated results. */
1447 if (sat && s)
1448 State.regs[OP[1]] = 0x80000000;
1449 else if (sat)
1450 State.regs[OP[1]] = 0x7fffffff;
1451 trace_output (OP_REG_REG);
1452 }
1453
1454 /* tst reg,reg */
1455 void
1456 OP_160 ()
1457 {
1458 unsigned int op0, op1, result, z, s;
1459
1460 trace_input ("tst", OP_REG_REG_CMP, 0);
1461
1462 /* Compute the result. */
1463 op0 = State.regs[OP[0]];
1464 op1 = State.regs[OP[1]];
1465 result = op0 & op1;
1466
1467 /* Compute the condition codes. */
1468 z = (result == 0);
1469 s = (result & 0x80000000);
1470
1471 /* Store the condition codes. */
1472 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1473 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1474 trace_output (OP_REG_REG_CMP);
1475 }
1476
1477 /* mov reg, reg */
1478 void
1479 OP_0 ()
1480 {
1481 trace_input ("mov", OP_REG_REG_MOVE, 0);
1482 State.regs[OP[1]] = State.regs[OP[0]];
1483 trace_output (OP_REG_REG_MOVE);
1484 }
1485
1486 /* mov sign_extend(imm5), reg */
1487 void
1488 OP_200 ()
1489 {
1490 int value = SEXT5 (OP[0]);
1491
1492 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1493 State.regs[OP[1]] = value;
1494 trace_output (OP_IMM_REG_MOVE);
1495 }
1496
1497 /* movea sign_extend(imm16), reg, reg */
1498
1499 void
1500 OP_620 ()
1501 {
1502 int value = SEXT16 (OP[0]);
1503
1504 trace_input ("movea", OP_IMM_REG_REG, 0);
1505 State.regs[OP[2]] = State.regs[OP[1]] + value;
1506 trace_output (OP_IMM_REG_REG);
1507 }
1508
1509 /* movhi imm16, reg, reg */
1510 void
1511 OP_640 ()
1512 {
1513 uint32 value = (OP[0] & 0xffff) << 16;
1514
1515 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1516 State.regs[OP[2]] = State.regs[OP[1]] + value;
1517 trace_output (OP_UIMM_REG_REG);
1518 }
1519
1520 /* sar zero_extend(imm5),reg1 */
1521 void
1522 OP_2A0 ()
1523 {
1524 unsigned int op0, op1, result, z, s, cy;
1525
1526 trace_input ("sar", OP_IMM_REG, 0);
1527 op0 = OP[0] & 0x1f;
1528 op1 = State.regs[OP[1]];
1529 result = (signed)op1 >> op0;
1530
1531 /* Compute the condition codes. */
1532 z = (result == 0);
1533 s = (result & 0x80000000);
1534 cy = (op1 & (1 << (op0 - 1)));
1535
1536 /* Store the result and condition codes. */
1537 State.regs[OP[1]] = result;
1538 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1539 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1540 | (cy ? PSW_CY : 0));
1541 trace_output (OP_IMM_REG);
1542 }
1543
1544 /* sar reg1, reg2 */
1545 void
1546 OP_A007E0 ()
1547 {
1548 unsigned int op0, op1, result, z, s, cy;
1549
1550 trace_input ("sar", OP_REG_REG, 0);
1551 op0 = State.regs[OP[0]] & 0x1f;
1552 op1 = State.regs[OP[1]];
1553 result = (signed)op1 >> op0;
1554
1555 /* Compute the condition codes. */
1556 z = (result == 0);
1557 s = (result & 0x80000000);
1558 cy = (op1 & (1 << (op0 - 1)));
1559
1560 /* Store the result and condition codes. */
1561 State.regs[OP[1]] = result;
1562 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1563 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1564 | (cy ? PSW_CY : 0));
1565 trace_output (OP_REG_REG);
1566 }
1567
1568 /* shl zero_extend(imm5),reg1 */
1569 void
1570 OP_2C0 ()
1571 {
1572 unsigned int op0, op1, result, z, s, cy;
1573
1574 trace_input ("shl", OP_IMM_REG, 0);
1575 op0 = OP[0] & 0x1f;
1576 op1 = State.regs[OP[1]];
1577 result = op1 << op0;
1578
1579 /* Compute the condition codes. */
1580 z = (result == 0);
1581 s = (result & 0x80000000);
1582 cy = (op1 & (1 << (32 - op0)));
1583
1584 /* Store the result and condition codes. */
1585 State.regs[OP[1]] = result;
1586 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1587 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1588 | (cy ? PSW_CY : 0));
1589 trace_output (OP_IMM_REG);
1590 }
1591
1592 /* shl reg1, reg2 */
1593 void
1594 OP_C007E0 ()
1595 {
1596 unsigned int op0, op1, result, z, s, cy;
1597
1598 trace_input ("shl", OP_REG_REG, 0);
1599 op0 = State.regs[OP[0]] & 0x1f;
1600 op1 = State.regs[OP[1]];
1601 result = op1 << op0;
1602
1603 /* Compute the condition codes. */
1604 z = (result == 0);
1605 s = (result & 0x80000000);
1606 cy = (op1 & (1 << (32 - op0)));
1607
1608 /* Store the result and condition codes. */
1609 State.regs[OP[1]] = result;
1610 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1611 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1612 | (cy ? PSW_CY : 0));
1613 trace_output (OP_REG_REG);
1614 }
1615
1616 /* shr zero_extend(imm5),reg1 */
1617 void
1618 OP_280 ()
1619 {
1620 unsigned int op0, op1, result, z, s, cy;
1621
1622 trace_input ("shr", OP_IMM_REG, 0);
1623 op0 = OP[0] & 0x1f;
1624 op1 = State.regs[OP[1]];
1625 result = op1 >> op0;
1626
1627 /* Compute the condition codes. */
1628 z = (result == 0);
1629 s = (result & 0x80000000);
1630 cy = (op1 & (1 << (op0 - 1)));
1631
1632 /* Store the result and condition codes. */
1633 State.regs[OP[1]] = result;
1634 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1635 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1636 | (cy ? PSW_CY : 0));
1637 trace_output (OP_IMM_REG);
1638 }
1639
1640 /* shr reg1, reg2 */
1641 void
1642 OP_8007E0 ()
1643 {
1644 unsigned int op0, op1, result, z, s, cy;
1645
1646 trace_input ("shr", OP_REG_REG, 0);
1647 op0 = State.regs[OP[0]] & 0x1f;
1648 op1 = State.regs[OP[1]];
1649 result = op1 >> op0;
1650
1651 /* Compute the condition codes. */
1652 z = (result == 0);
1653 s = (result & 0x80000000);
1654 cy = (op1 & (1 << (op0 - 1)));
1655
1656 /* Store the result and condition codes. */
1657 State.regs[OP[1]] = result;
1658 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1659 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1660 | (cy ? PSW_CY : 0));
1661 trace_output (OP_REG_REG);
1662 }
1663
1664 /* or reg, reg */
1665 void
1666 OP_100 ()
1667 {
1668 unsigned int op0, op1, result, z, s;
1669
1670 trace_input ("or", OP_REG_REG, 0);
1671
1672 /* Compute the result. */
1673 op0 = State.regs[OP[0]];
1674 op1 = State.regs[OP[1]];
1675 result = op0 | op1;
1676
1677 /* Compute the condition codes. */
1678 z = (result == 0);
1679 s = (result & 0x80000000);
1680
1681 /* Store the result and condition codes. */
1682 State.regs[OP[1]] = result;
1683 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1684 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1685 trace_output (OP_REG_REG);
1686 }
1687
1688 /* ori zero_extend(imm16), reg, reg */
1689 void
1690 OP_680 ()
1691 {
1692 unsigned int op0, op1, result, z, s;
1693
1694 trace_input ("ori", OP_UIMM_REG_REG, 0);
1695 op0 = OP[0] & 0xffff;
1696 op1 = State.regs[OP[1]];
1697 result = op0 | op1;
1698
1699 /* Compute the condition codes. */
1700 z = (result == 0);
1701 s = (result & 0x80000000);
1702
1703 /* Store the result and condition codes. */
1704 State.regs[OP[2]] = result;
1705 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1706 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1707 trace_output (OP_UIMM_REG_REG);
1708 }
1709
1710 /* and reg, reg */
1711 void
1712 OP_140 ()
1713 {
1714 unsigned int op0, op1, result, z, s;
1715
1716 trace_input ("and", OP_REG_REG, 0);
1717
1718 /* Compute the result. */
1719 op0 = State.regs[OP[0]];
1720 op1 = State.regs[OP[1]];
1721 result = op0 & op1;
1722
1723 /* Compute the condition codes. */
1724 z = (result == 0);
1725 s = (result & 0x80000000);
1726
1727 /* Store the result and condition codes. */
1728 State.regs[OP[1]] = result;
1729 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1730 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1731 trace_output (OP_REG_REG);
1732 }
1733
1734 /* andi zero_extend(imm16), reg, reg */
1735 void
1736 OP_6C0 ()
1737 {
1738 unsigned int op0, op1, result, z;
1739
1740 trace_input ("andi", OP_UIMM_REG_REG, 0);
1741 op0 = OP[0] & 0xffff;
1742 op1 = State.regs[OP[1]];
1743 result = op0 & op1;
1744
1745 /* Compute the condition codes. */
1746 z = (result == 0);
1747
1748 /* Store the result and condition codes. */
1749 State.regs[OP[2]] = result;
1750 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1751 State.sregs[5] |= (z ? PSW_Z : 0);
1752 trace_output (OP_UIMM_REG_REG);
1753 }
1754
1755 /* xor reg, reg */
1756 void
1757 OP_120 ()
1758 {
1759 unsigned int op0, op1, result, z, s;
1760
1761 trace_input ("xor", OP_REG_REG, 0);
1762
1763 /* Compute the result. */
1764 op0 = State.regs[OP[0]];
1765 op1 = State.regs[OP[1]];
1766 result = op0 ^ op1;
1767
1768 /* Compute the condition codes. */
1769 z = (result == 0);
1770 s = (result & 0x80000000);
1771
1772 /* Store the result and condition codes. */
1773 State.regs[OP[1]] = result;
1774 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1775 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1776 trace_output (OP_REG_REG);
1777 }
1778
1779 /* xori zero_extend(imm16), reg, reg */
1780 void
1781 OP_6A0 ()
1782 {
1783 unsigned int op0, op1, result, z, s;
1784
1785 trace_input ("xori", OP_UIMM_REG_REG, 0);
1786 op0 = OP[0] & 0xffff;
1787 op1 = State.regs[OP[1]];
1788 result = op0 ^ op1;
1789
1790 /* Compute the condition codes. */
1791 z = (result == 0);
1792 s = (result & 0x80000000);
1793
1794 /* Store the result and condition codes. */
1795 State.regs[OP[2]] = result;
1796 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1797 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1798 trace_output (OP_UIMM_REG_REG);
1799 }
1800
1801 /* not reg1, reg2 */
1802 void
1803 OP_20 ()
1804 {
1805 unsigned int op0, result, z, s;
1806
1807 trace_input ("not", OP_REG_REG_MOVE, 0);
1808 /* Compute the result. */
1809 op0 = State.regs[OP[0]];
1810 result = ~op0;
1811
1812 /* Compute the condition codes. */
1813 z = (result == 0);
1814 s = (result & 0x80000000);
1815
1816 /* Store the result and condition codes. */
1817 State.regs[OP[1]] = result;
1818 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1819 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1820 trace_output (OP_REG_REG_MOVE);
1821 }
1822
1823 /* set1 */
1824 void
1825 OP_7C0 ()
1826 {
1827 unsigned int op0, op1, op2;
1828 int temp;
1829
1830 trace_input ("set1", OP_BIT, 0);
1831 op0 = State.regs[OP[0]];
1832 op1 = OP[1] & 0x7;
1833 temp = SEXT16 (OP[2]);
1834 op2 = temp;
1835 temp = load_mem (op0 + op2, 1);
1836 State.sregs[5] &= ~PSW_Z;
1837 if ((temp & (1 << op1)) == 0)
1838 State.sregs[5] |= PSW_Z;
1839 temp |= (1 << op1);
1840 store_mem (op0 + op2, 1, temp);
1841 trace_output (OP_BIT);
1842 }
1843
1844 /* not1 */
1845 void
1846 OP_47C0 ()
1847 {
1848 unsigned int op0, op1, op2;
1849 int temp;
1850
1851 trace_input ("not1", OP_BIT, 0);
1852 op0 = State.regs[OP[0]];
1853 op1 = OP[1] & 0x7;
1854 temp = SEXT16 (OP[2]);
1855 op2 = temp;
1856 temp = load_mem (op0 + op2, 1);
1857 State.sregs[5] &= ~PSW_Z;
1858 if ((temp & (1 << op1)) == 0)
1859 State.sregs[5] |= PSW_Z;
1860 temp ^= (1 << op1);
1861 store_mem (op0 + op2, 1, temp);
1862 trace_output (OP_BIT);
1863 }
1864
1865 /* clr1 */
1866 void
1867 OP_87C0 ()
1868 {
1869 unsigned int op0, op1, op2;
1870 int temp;
1871
1872 trace_input ("clr1", OP_BIT, 0);
1873 op0 = State.regs[OP[0]];
1874 op1 = OP[1] & 0x7;
1875 temp = SEXT16 (OP[2]);
1876 op2 = temp;
1877 temp = load_mem (op0 + op2, 1);
1878 State.sregs[5] &= ~PSW_Z;
1879 if ((temp & (1 << op1)) == 0)
1880 State.sregs[5] |= PSW_Z;
1881 temp &= ~(1 << op1);
1882 store_mem (op0 + op2, 1, temp);
1883 trace_output (OP_BIT);
1884 }
1885
1886 /* tst1 */
1887 void
1888 OP_C7C0 ()
1889 {
1890 unsigned int op0, op1, op2;
1891 int temp;
1892
1893 trace_input ("tst1", OP_BIT, 0);
1894 op0 = State.regs[OP[0]];
1895 op1 = OP[1] & 0x7;
1896 temp = SEXT16 (OP[2]);
1897 op2 = temp;
1898 temp = load_mem (op0 + op2, 1);
1899 State.sregs[5] &= ~PSW_Z;
1900 if ((temp & (1 << op1)) == 0)
1901 State.sregs[5] |= PSW_Z;
1902 trace_output (OP_BIT);
1903 }
1904
1905 /* breakpoint */
1906 void
1907 OP_FFFF ()
1908 {
1909 State.exception = SIGTRAP;
1910 PC -= 4;
1911 }
1912
1913 /* di */
1914 void
1915 OP_16007E0 ()
1916 {
1917 trace_input ("di", OP_NONE, 0);
1918 State.sregs[5] |= PSW_ID;
1919 trace_output (OP_NONE);
1920 }
1921
1922 /* ei */
1923 void
1924 OP_16087E0 ()
1925 {
1926 trace_input ("ei", OP_NONE, 0);
1927 State.sregs[5] &= ~PSW_ID;
1928 trace_output (OP_NONE);
1929 }
1930
1931 /* halt, not supported */
1932 void
1933 OP_12007E0 ()
1934 {
1935 trace_input ("halt", OP_NONE, 0);
1936 State.exception = SIGQUIT;
1937 trace_output (OP_NONE);
1938 }
1939
1940 /* reti, not supported */
1941 void
1942 OP_14007E0 ()
1943 {
1944 trace_input ("reti", OP_NONE, 0);
1945 trace_output (OP_NONE);
1946
1947 if ((State.sregs[5] & (PSW_NP | PSW_EP)) == PSW_NP)
1948 { /* Only NP is on */
1949 PC = State.sregs[2] - 4; /* FEPC */
1950 State.sregs[5] = State.sregs[3]; /* FEPSW */
1951 }
1952 else
1953 {
1954 PC = State.sregs[0] - 4; /* EIPC */
1955 State.sregs[5] = State.sregs[1]; /* EIPSW */
1956 }
1957 }
1958
1959 /* trap, not supportd */
1960 void
1961 OP_10007E0 ()
1962 {
1963 trace_input ("trap", OP_TRAP, 0);
1964 trace_output (OP_TRAP);
1965
1966 /* Trap 31 is used for simulating OS I/O functions */
1967
1968 if (OP[0] == 31)
1969 {
1970 int save_errno = errno;
1971 errno = 0;
1972
1973 /* Registers passed to trap 0 */
1974
1975 #define FUNC State.regs[6] /* function number, return value */
1976 #define PARM1 State.regs[7] /* optional parm 1 */
1977 #define PARM2 State.regs[8] /* optional parm 2 */
1978 #define PARM3 State.regs[9] /* optional parm 3 */
1979
1980 /* Registers set by trap 0 */
1981
1982 #define RETVAL State.regs[10] /* return value */
1983 #define RETERR State.regs[11] /* return error code */
1984
1985 /* Turn a pointer in a register into a pointer into real memory. */
1986
1987 #define MEMPTR(x) (map (x))
1988
1989 switch (FUNC)
1990 {
1991 #if !defined(__GO32__) && !defined(_WIN32)
1992 case SYS_fork:
1993 RETVAL = fork ();
1994 break;
1995 case SYS_execve:
1996 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
1997 (char **)MEMPTR (PARM3));
1998 break;
1999 case SYS_execv:
2000 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2001 break;
2002 #if 0
2003 case SYS_pipe:
2004 {
2005 reg_t buf;
2006 int host_fd[2];
2007
2008 buf = PARM1;
2009 RETVAL = pipe (host_fd);
2010 SW (buf, host_fd[0]);
2011 buf += sizeof(uint16);
2012 SW (buf, host_fd[1]);
2013 }
2014 break;
2015
2016 case SYS_wait:
2017 {
2018 int status;
2019
2020 RETVAL = wait (&status);
2021 SW (PARM1, status);
2022 }
2023 break;
2024 #endif
2025 #endif
2026
2027 case SYS_read:
2028 RETVAL = v850_callback->read (v850_callback, PARM1, MEMPTR (PARM2),
2029 PARM3);
2030 break;
2031 case SYS_write:
2032 if (PARM1 == 1)
2033 RETVAL = (int)v850_callback->write_stdout (v850_callback,
2034 MEMPTR (PARM2), PARM3);
2035 else
2036 RETVAL = (int)v850_callback->write (v850_callback, PARM1,
2037 MEMPTR (PARM2), PARM3);
2038 break;
2039 case SYS_lseek:
2040 RETVAL = v850_callback->lseek (v850_callback, PARM1, PARM2, PARM3);
2041 break;
2042 case SYS_close:
2043 RETVAL = v850_callback->close (v850_callback, PARM1);
2044 break;
2045 case SYS_open:
2046 RETVAL = v850_callback->open (v850_callback, MEMPTR (PARM1), PARM2);
2047 break;
2048 case SYS_exit:
2049 /* EXIT - caller can look in PARM1 to work out the
2050 reason */
2051 if (PARM1 == 0xdead || PARM1 == 0x1)
2052 State.exception = SIGABRT;
2053 else
2054 State.exception = SIGQUIT;
2055 break;
2056
2057 case SYS_stat: /* added at hmsi */
2058 /* stat system call */
2059 {
2060 struct stat host_stat;
2061 reg_t buf;
2062
2063 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2064
2065 buf = PARM2;
2066
2067 /* Just wild-assed guesses. */
2068 store_mem (buf, 2, host_stat.st_dev);
2069 store_mem (buf + 2, 2, host_stat.st_ino);
2070 store_mem (buf + 4, 4, host_stat.st_mode);
2071 store_mem (buf + 8, 2, host_stat.st_nlink);
2072 store_mem (buf + 10, 2, host_stat.st_uid);
2073 store_mem (buf + 12, 2, host_stat.st_gid);
2074 store_mem (buf + 14, 2, host_stat.st_rdev);
2075 store_mem (buf + 16, 4, host_stat.st_size);
2076 store_mem (buf + 20, 4, host_stat.st_atime);
2077 store_mem (buf + 28, 4, host_stat.st_mtime);
2078 store_mem (buf + 36, 4, host_stat.st_ctime);
2079 }
2080 break;
2081
2082 case SYS_chown:
2083 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2084 break;
2085 case SYS_chmod:
2086 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2087 break;
2088 case SYS_time:
2089 RETVAL = time (MEMPTR (PARM1));
2090 break;
2091 case SYS_times:
2092 {
2093 struct tms tms;
2094 RETVAL = times (&tms);
2095 store_mem (PARM1, 4, tms.tms_utime);
2096 store_mem (PARM1 + 4, 4, tms.tms_stime);
2097 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2098 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2099 break;
2100 }
2101 case SYS_gettimeofday:
2102 {
2103 struct timeval t;
2104 struct timezone tz;
2105 RETVAL = gettimeofday (&t, &tz);
2106 store_mem (PARM1, 4, t.tv_sec);
2107 store_mem (PARM1 + 4, 4, t.tv_usec);
2108 store_mem (PARM2, 4, tz.tz_minuteswest);
2109 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2110 break;
2111 }
2112 case SYS_utime:
2113 /* Cast the second argument to void *, to avoid type mismatch
2114 if a prototype is present. */
2115 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2116 break;
2117 default:
2118 abort ();
2119 }
2120 RETERR = errno;
2121 errno = save_errno;
2122 }
2123 else
2124 { /* Trap 0 -> 30 */
2125 State.sregs[0] = PC + 4; /* EIPC */
2126 State.sregs[1] = State.sregs[5]; /* EIPSW */
2127 State.sregs[4] &= 0xffff0000; /* Mask out EICC */
2128 State.sregs[4] |= 0x40 + OP[0]; /* EICC */
2129 State.sregs[5] |= PSW_EP | PSW_ID; /* Now doing exception processing */
2130 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
2131 }
2132 }
2133
2134 /* ldsr, reg,reg */
2135 void
2136 OP_2007E0 ()
2137 {
2138 unsigned int op0;
2139
2140 trace_input ("ldsr", OP_LDSR, 0);
2141 op0 = State.regs[OP[0]];
2142 State.sregs[OP[1]] = op0;
2143 trace_output (OP_LDSR);
2144 }
2145
2146 /* stsr, not supported */
2147 void
2148 OP_4007E0 ()
2149 {
2150 unsigned int op0;
2151
2152 trace_input ("stsr", OP_STSR, 0);
2153 op0 = State.sregs[OP[1]];
2154 State.regs[OP[0]] = op0;
2155 trace_output (OP_STSR);
2156 }