sim/v850/simops.c

   1 #include <signal.h>
   2 #include "v850_sim.h"
   3 #include "simops.h"
   4
   5 /* sld.b */
   6 void
   7 OP_300 ()
   8 {
   9   unsigned int op0, op1, op2;
  10   int result, temp;
  11
  12   temp = OP[1];
  13   temp = (temp << 25) >> 25;
  14   op2 = temp;
  15   result = get_byte (State.mem + State.regs[30] + op2);
  16   result = (result << 24) >> 24;
  17   State.regs[OP[0]] = result;
  18 }
  19
  20 /* sld.h */
  21 void
  22 OP_400 ()
  23 {
  24   unsigned int op0, op1, op2;
  25   int result, temp;
  26
  27   temp = OP[1];
  28   temp = (temp << 25) >> 25;
  29   op2 = temp << 1;
  30   result = get_half (State.mem + State.regs[30] + op2);
  31   result = (result << 16) >> 16;
  32   State.regs[OP[0]] = result;
  33 }
  34
  35 /* sld.w */
  36 void
  37 OP_500 ()
  38 {
  39   unsigned int op0, op1, op2;
  40   int result, temp;
  41
  42   temp = OP[1];
  43   temp = (temp << 25) >> 25;
  44   op2 = temp << 2;
  45   result = get_word (State.mem + State.regs[30] + op2);
  46   State.regs[OP[0]] = result;
  47 }
  48
  49 /* sst.b */
  50 void
  51 OP_380 ()
  52 {
  53   unsigned int op0, op1, op2;
  54   int result, temp;
  55
  56   op0 = State.regs[OP[0]];
  57   temp = OP[1];
  58   temp = (temp << 25) >> 25;
  59   op1 = temp;
  60   put_byte (State.mem + State.regs[30] + op1, op0);
  61 }
  62
  63 /* sst.h */
  64 void
  65 OP_480 ()
  66 {
  67   unsigned int op0, op1, op2;
  68   int result, temp;
  69
  70   op0 = State.regs[OP[0]];
  71   temp = OP[1];
  72   temp = (temp << 25) >> 25;
  73   op1 = temp << 1;
  74   put_half (State.mem + State.regs[30] + op1, op0);
  75 }
  76
  77 /* sst.w */
  78 void
  79 OP_501 ()
  80 {
  81   unsigned int op0, op1, op2;
  82   int result, temp;
  83
  84   op0 = State.regs[OP[0]];
  85   temp = OP[1];
  86   temp = (temp << 25) >> 25;
  87   op1 = temp << 2;
  88   put_word (State.mem + State.regs[30] + op1, op0);
  89 }
  90
  91 /* ld.b */
  92 void
  93 OP_700 ()
  94 {
  95   unsigned int op0, op1, op2;
  96   int result, temp;
  97
  98   op0 = State.regs[OP[0]];
  99   temp = OP[2];
 100   temp = (temp << 16) >> 16;
 101   op2 = temp;
 102   result = get_byte (State.mem + op0 + op2);
 103   result = (result << 24) >> 24;
 104   State.regs[OP[1]] = result;
 105 }
 106
 107 /* ld.h */
 108 void
 109 OP_720 ()
 110 {
 111   unsigned int op0, op1, op2;
 112   int result, temp;
 113
 114   op0 = State.regs[OP[0]];
 115   temp = (temp << 16) >> 16;
 116   temp &= ~0x1;
 117   op2 = temp;
 118   result = get_half (State.mem + op0 + op2);
 119   result = (result << 16) >> 16;
 120   State.regs[OP[1]] = result;
 121 }
 122
 123 /* ld.w */
 124 void
 125 OP_10720 ()
 126 {
 127   unsigned int op0, op1, op2;
 128   int result, temp;
 129
 130   op0 = State.regs[OP[0]];
 131   temp = (temp << 16) >> 16;
 132   temp &= ~0x1;
 133   op2 = temp;
 134   result = get_word (State.mem + op0 + op2);
 135   State.regs[OP[1]] = result;
 136 }
 137
 138 /* st.b */
 139 void
 140 OP_740 ()
 141 {
 142   unsigned int op0, op1, op2;
 143   int result, temp;
 144
 145   op0 = State.regs[OP[0]];
 146   op1 = State.regs[OP[1]];
 147   temp = OP[2];
 148   temp = (temp << 16) >> 16;
 149   op2 = temp;
 150   put_byte (State.mem + op0 + op2, op1);
 151 }
 152
 153 /* st.h */
 154 void
 155 OP_760 ()
 156 {
 157   unsigned int op0, op1, op2;
 158   int result, temp;
 159
 160   op0 = State.regs[OP[0]];
 161   op1 = State.regs[OP[1]];
 162   temp = OP[2];
 163   temp &= ~0x1;
 164   temp = (temp << 16) >> 16;
 165   op2 = temp;
 166   put_half (State.mem + op0 + op2, op1);
 167 }
 168
 169 /* st.w */
 170 void
 171 OP_10760 ()
 172 {
 173   unsigned int op0, op1, op2;
 174   int result, temp;
 175
 176   op0 = State.regs[OP[0]];
 177   op1 = State.regs[OP[1]];
 178   temp = OP[2];
 179   temp &= ~0x1;
 180   temp = (temp << 16) >> 16;
 181   op2 = temp;
 182   put_word (State.mem + op0 + op2, op1);
 183 }
 184
 185 /* bv disp9 */
 186 void
 187 OP_580 ()
 188 {
 189   unsigned int op0, psw;
 190   int temp;
 191
 192   temp = (State.regs[OP[0]] << 23) >> 23;
 193   op0 = temp;
 194   psw = State.sregs[5];
 195
 196   if ((psw & PSW_OV) != 0)
 197     State.pc += op0;
 198   else
 199     State.pc += 2;
 200 }
 201
 202 /* bl disp9 */
 203 void
 204 OP_581 ()
 205 {
 206   unsigned int op0, psw;
 207   int temp;
 208
 209   temp = (State.regs[OP[0]] << 23) >> 23;
 210   op0 = temp;
 211   psw = State.sregs[5];
 212
 213   if ((psw & PSW_CY) != 0)
 214     State.pc += op0;
 215   else
 216     State.pc += 2;
 217 }
 218
 219 /* be disp9 */
 220 void
 221 OP_582 ()
 222 {
 223   unsigned int op0, psw;
 224   int temp;
 225
 226   temp = (State.regs[OP[0]] << 23) >> 23;
 227   op0 = temp;
 228   psw = State.sregs[5];
 229
 230   if ((psw & PSW_Z) != 0)
 231     State.pc += op0;
 232   else
 233     State.pc += 2;
 234 }
 235
 236 /* bnh disp 9*/
 237 void
 238 OP_583 ()
 239 {
 240   unsigned int op0, psw;
 241   int temp;
 242
 243   temp = (State.regs[OP[0]] << 23) >> 23;
 244   op0 = temp;
 245   psw = State.sregs[5];
 246
 247   if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
 248     State.pc += op0;
 249   else
 250     State.pc += 2;
 251 }
 252
 253 /* bn disp9 */
 254 void
 255 OP_584 ()
 256 {
 257   unsigned int op0, psw;
 258   int temp;
 259
 260   temp = (State.regs[OP[0]] << 23) >> 23;
 261   op0 = temp;
 262   psw = State.sregs[5];
 263
 264   if ((psw & PSW_S) != 0)
 265     State.pc += op0;
 266   else
 267     State.pc += 2;
 268 }
 269
 270 /* br disp9 */
 271 void
 272 OP_585 ()
 273 {
 274   unsigned int op0;
 275   int temp;
 276
 277   temp = (State.regs[OP[0]] << 23) >> 23;
 278   op0 = temp;
 279   State.pc += op0;
 280 }
 281
 282 /* blt disp9 */
 283 void
 284 OP_586 ()
 285 {
 286   unsigned int op0, psw;
 287   int temp;
 288
 289   temp = (State.regs[OP[0]] << 23) >> 23;
 290   op0 = temp;
 291   psw = State.sregs[5];
 292
 293   if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
 294     State.pc += op0;
 295   else
 296     State.pc += 2;
 297 }
 298
 299 /* ble disp9 */
 300 void
 301 OP_587 ()
 302 {
 303   unsigned int op0, psw;
 304   int temp;
 305
 306   temp = (State.regs[OP[0]] << 23) >> 23;
 307   op0 = temp;
 308   psw = State.sregs[5];
 309
 310   if ((((psw & PSW_Z) != 0)
 311        || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
 312     State.pc += op0;
 313   else
 314     State.pc += 2;
 315 }
 316
 317 /* bnv disp9 */
 318 void
 319 OP_588 ()
 320 {
 321   unsigned int op0, psw;
 322   int temp;
 323
 324   temp = (State.regs[OP[0]] << 23) >> 23;
 325   op0 = temp;
 326   psw = State.sregs[5];
 327
 328   if ((psw & PSW_OV) == 0)
 329     State.pc += op0;
 330   else
 331     State.pc += 2;
 332 }
 333
 334 /* bnl disp9 */
 335 void
 336 OP_589 ()
 337 {
 338   unsigned int op0, psw;
 339   int temp;
 340
 341   temp = (State.regs[OP[0]] << 23) >> 23;
 342   op0 = temp;
 343   psw = State.sregs[5];
 344
 345   if ((psw & PSW_CY) == 0)
 346     State.pc += op0;
 347   else
 348     State.pc += 2;
 349 }
 350
 351 /* bne disp9 */
 352 void
 353 OP_58A ()
 354 {
 355   unsigned int op0, psw;
 356   int temp;
 357
 358   temp = (State.regs[OP[0]] << 23) >> 23;
 359   op0 = temp;
 360   psw = State.sregs[5];
 361
 362   if ((psw & PSW_Z) == 0)
 363     State.pc += op0;
 364   else
 365     State.pc += 2;
 366 }
 367
 368 /* bh disp9 */
 369 void
 370 OP_58B ()
 371 {
 372   unsigned int op0, psw;
 373   int temp;
 374
 375   temp = (State.regs[OP[0]] << 23) >> 23;
 376   op0 = temp;
 377   psw = State.sregs[5];
 378
 379   if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
 380     State.pc += op0;
 381   else
 382     State.pc += 2;
 383 }
 384
 385 /* bp disp9 */
 386 void
 387 OP_58C ()
 388 {
 389   unsigned int op0, psw;
 390   int temp;
 391
 392   temp = (State.regs[OP[0]] << 23) >> 23;
 393   op0 = temp;
 394   psw = State.sregs[5];
 395
 396   if ((psw & PSW_S) == 0)
 397     State.pc += op0;
 398   else
 399     State.pc += 2;
 400 }
 401
 402 /* bsa disp9 */
 403 void
 404 OP_58D ()
 405 {
 406   unsigned int op0, psw;
 407   int temp;
 408
 409   temp = (State.regs[OP[0]] << 23) >> 23;
 410   op0 = temp;
 411   psw = State.sregs[5];
 412
 413   if ((psw & PSW_SAT) != 0)
 414     State.pc += op0;
 415   else
 416     State.pc += 2;
 417 }
 418
 419 /* bge disp9 */
 420 void
 421 OP_58E ()
 422 {
 423   unsigned int op0, psw;
 424   int temp;
 425
 426   temp = (State.regs[OP[0]] << 23) >> 23;
 427   op0 = temp;
 428   psw = State.sregs[5];
 429
 430   if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
 431     State.pc += op0;
 432   else
 433     State.pc += 2;
 434 }
 435
 436 /* bgt disp9 */
 437 void
 438 OP_58F ()
 439 {
 440   unsigned int op0, psw;
 441   int temp;
 442
 443   temp = (State.regs[OP[0]] << 23) >> 23;
 444   op0 = temp;
 445   psw = State.sregs[5];
 446
 447   if ((((psw & PSW_Z) != 0)
 448        || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
 449     State.pc += op0;
 450   else
 451     State.pc += 2;
 452 }
 453
 454 /* jmp [reg1] */
 455 void
 456 OP_60 ()
 457 {
 458   /* interp.c will bump this by +2, so correct for it here.  */
 459   State.pc = State.regs[OP[0]] - 2;
 460 }
 461
 462 /* jarl disp22, reg */
 463 void
 464 OP_780 ()
 465 {
 466   unsigned int op0, opc;
 467   int temp;
 468
 469   temp = OP[0];
 470   temp = (temp << 10) >> 10;
 471   op0 = temp;
 472   opc = State.pc;
 473
 474   State.pc += temp;
 475
 476   /* Gross.  jarl X,r0 is really jr and doesn't save its result.  */
 477   if (OP[1] != 0)
 478     State.regs[OP[1]] = opc + 4;
 479 }
 480
 481 /* add reg, reg */
 482 void
 483 OP_1C0 ()
 484 {
 485   unsigned int op0, op1, result, z, s, cy, ov;
 486
 487   /* Compute the result.  */
 488   op0 = State.regs[OP[0]];
 489   op1 = State.regs[OP[1]];
 490   result = op0 + op1;
 491
 492   /* Compute the condition codes.  */
 493   z = (result == 0);
 494   s = (result & 0x80000000);
 495   cy = (result < op0 || result < op1);
 496   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 497         && (op0 & 0x80000000) != (result & 0x80000000));
 498
 499   /* Store the result and condition codes.  */
 500   State.regs[OP[1]] = result;
 501   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 502   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 503                      | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 504 }
 505
 506 /* add sign_extend(imm5), reg */
 507 void
 508 OP_240 ()
 509 {
 510   unsigned int op0, op1, result, z, s, cy, ov;
 511   int temp;
 512
 513   /* Compute the result.  */
 514   temp = (OP[0] & 0x1f);
 515   temp = (temp << 27) >> 27;
 516   op0 = temp;
 517   op1 = State.regs[OP[1]];
 518   result = op0 + op1;
 519
 520   /* Compute the condition codes.  */
 521   z = (result == 0);
 522   s = (result & 0x80000000);
 523   cy = (result < op0 || result < op1);
 524   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 525         && (op0 & 0x80000000) != (result & 0x80000000));
 526
 527   /* Store the result and condition codes.  */
 528   State.regs[OP[1]] = result;
 529   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 530   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 531                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 532 }
 533
 534 /* addi sign_extend(imm16), reg, reg */
 535 void
 536 OP_600 ()
 537 {
 538   unsigned int op0, op1, result, z, s, cy, ov;
 539   int temp;
 540
 541   /* Compute the result.  */
 542   temp = (OP[0] & 0xffff);
 543   temp = (temp << 16) >> 16;
 544   op0 = temp;
 545   op1 = State.regs[OP[1]];
 546   result = op0 + op1;
 547
 548   /* Compute the condition codes.  */
 549   z = (result == 0);
 550   s = (result & 0x80000000);
 551   cy = (result < op0 || result < op1);
 552   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 553         && (op0 & 0x80000000) != (result & 0x80000000));
 554
 555   /* Store the result and condition codes.  */
 556   State.regs[OP[2]] = result;
 557   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 558   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 559                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 560 }
 561
 562 /* sub reg1, reg2 */
 563 void
 564 OP_1A0 ()
 565 {
 566   unsigned int op0, op1, result, z, s, cy, ov;
 567
 568   /* Compute the result.  */
 569   op0 = State.regs[OP[0]];
 570   op1 = State.regs[OP[1]];
 571   result = op1 - op0;
 572
 573   /* Compute the condition codes.  */
 574   z = (result == 0);
 575   s = (result & 0x80000000);
 576   cy = (result < -op0);
 577   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 578         && (op1 & 0x80000000) != (result & 0x80000000));
 579
 580   /* Store the result and condition codes.  */
 581   State.regs[OP[1]] = result;
 582   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 583   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 584                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 585 }
 586
 587 /* subr reg1, reg2 */
 588 void
 589 OP_180 ()
 590 {
 591   unsigned int op0, op1, result, z, s, cy, ov;
 592
 593   /* Compute the result.  */
 594   op0 = State.regs[OP[0]];
 595   op1 = State.regs[OP[1]];
 596   result = op0 - op1;
 597
 598   /* Compute the condition codes.  */
 599   z = (result == 0);
 600   s = (result & 0x80000000);
 601   cy = (result < -op1);
 602   ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
 603         && (op0 & 0x80000000) != (result & 0x80000000));
 604
 605   /* Store the result and condition codes.  */
 606   State.regs[OP[1]] = result;
 607   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 608   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 609                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 610 }
 611
 612 /* mulh reg1, reg2 */
 613 void
 614 OP_E0 ()
 615 {
 616   State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
 617                        * (State.regs[OP[0]] & 0xffff));
 618 }
 619
 620 /* mulh sign_extend(imm5), reg2
 621
 622    Condition codes */
 623 void
 624 OP_2E0 ()
 625 {
 626   int value = OP[0];
 627
 628   value = (value << 27) >> 27;
 629
 630   State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
 631 }
 632
 633 /* mulhi imm16, reg1, reg2 */
 634 void
 635 OP_6E0 ()
 636 {
 637   int value = OP[0];
 638
 639   value = value & 0xffff;
 640
 641   State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
 642 }
 643
 644 /* divh reg1, reg2 */
 645 void
 646 OP_40 ()
 647 {
 648   unsigned int op0, op1, result, z, s, cy, ov;
 649   int temp;
 650
 651   /* Compute the result.  */
 652   temp = State.regs[OP[0]] & 0xffff;
 653   temp = (temp << 16) >> 16;
 654   op0 = temp;
 655   op1 = State.regs[OP[1]];
 656
 657   if (op0 == 0xffffffff && op1 == 0x80000000)
 658     {
 659       result = 0x80000000;
 660       ov = 1;
 661     }
 662   else if (op0 != 0)
 663     {
 664       result = op1 / op0;
 665       ov = 0;
 666     }
 667   else
 668     ov = 1;
 669
 670   /* Compute the condition codes.  */
 671   z = (result == 0);
 672   s = (result & 0x80000000);
 673
 674   /* Store the result and condition codes.  */
 675   State.regs[OP[1]] = result;
 676   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
 677   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 678                 | (ov ? PSW_OV : 0));
 679 }
 680
 681 /* cmp reg, reg */
 682 void
 683 OP_1E0 ()
 684 {
 685   unsigned int op0, op1, result, z, s, cy, ov;
 686
 687   /* Compute the result.  */
 688   op0 = State.regs[OP[0]];
 689   op1 = State.regs[OP[1]];
 690   result = op1 - op0;
 691
 692   /* Compute the condition codes.  */
 693   z = (result == 0);
 694   s = (result & 0x80000000);
 695   cy = (result < -op0);
 696   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 697         && (op1 & 0x80000000) != (result & 0x80000000));
 698
 699   /* Set condition codes.  */
 700   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 701   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 702                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 703 }
 704
 705 /* cmp sign_extend(imm5), reg */
 706 void
 707 OP_260 ()
 708 {
 709   unsigned int op0, op1, result, z, s, cy, ov;
 710   int temp;
 711
 712   /* Compute the result.  */
 713   temp = OP[0];
 714   temp = (temp << 27) >> 27;
 715   op0 = temp;
 716   op1 = State.regs[OP[1]];
 717   result = op1 - op0;
 718
 719   /* Compute the condition codes.  */
 720   z = (result == 0);
 721   s = (result & 0x80000000);
 722   cy = (result < -op0);
 723   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 724         && (op1 & 0x80000000) != (result & 0x80000000));
 725
 726   /* Set condition codes.  */
 727   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 728   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 729                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 730 }
 731
 732 /* setf cccc,reg2 */
 733 void
 734 OP_7E0 ()
 735 {
 736   /* Hack alert.  We turn off a bit in op0 since we really only
 737      wanted 4 bits.  */
 738   unsigned int op0, psw, result;
 739
 740   op0 = OP[0] & 0xf;
 741   psw = State.sregs[5];
 742
 743   switch (op0)
 744     {
 745       case 0x0:
 746         result = ((psw & PSW_OV) != 0);
 747         break;
 748       case 0x1:
 749         result = ((psw & PSW_CY) != 0);
 750         break;
 751       case 0x2:
 752         result = ((psw & PSW_Z) != 0);
 753         break;
 754       case 0x3:
 755         result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
 756         break;
 757       case 0x4:
 758         result = ((psw & PSW_S) != 0);
 759         break;
 760       case 0x5:
 761         result = 1;
 762         break;
 763       case 0x6:
 764         result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
 765         break;
 766       case 0x7:
 767         result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
 768                   || ((psw & PSW_Z) != 0)) != 0);
 769         break;
 770       case 0x8:
 771         result = ((psw & PSW_OV) == 0);
 772         break;
 773       case 0x9:
 774         result = ((psw & PSW_CY) == 0);
 775         break;
 776       case 0xa:
 777         result = ((psw & PSW_Z) == 0);
 778         break;
 779       case 0xb:
 780         result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
 781         break;
 782       case 0xc:
 783         result = ((psw & PSW_S) == 0);
 784         break;
 785       case 0xd:
 786         result = ((psw & PSW_SAT) != 0);
 787         break;
 788       case 0xe:
 789         result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
 790         break;
 791       case 0xf:
 792         result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
 793                   || ((psw & PSW_Z) != 0)) == 0);
 794         break;
 795     }
 796
 797   State.regs[OP[1]] = result;
 798 }
 799
 800 /* satadd reg,reg */
 801 void
 802 OP_C0 ()
 803 {
 804   unsigned int op0, op1, result, z, s, cy, ov, sat;
 805
 806   /* Compute the result.  */
 807   op0 = State.regs[OP[0]];
 808   op1 = State.regs[OP[1]];
 809   result = op0 + op1;
 810
 811   /* Compute the condition codes.  */
 812   z = (result == 0);
 813   s = (result & 0x80000000);
 814   cy = (result < op0 || result < op1);
 815   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 816         && (op0 & 0x80000000) != (result & 0x80000000));
 817   sat = ov;
 818
 819   /* Store the result and condition codes.  */
 820   State.regs[OP[1]] = result;
 821   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 822   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 823                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 824                 | (sat ? PSW_SAT : 0));
 825
 826   /* Handle saturated results.  */
 827   if (sat && (op0 & 0x80000000))
 828     State.regs[OP[1]] = 0x80000000;
 829   else if (sat)
 830     State.regs[OP[1]] = 0x7fffffff;
 831 }
 832
 833 /* satadd sign_extend(imm5), reg */
 834 void
 835 OP_220 ()
 836 {
 837   unsigned int op0, op1, result, z, s, cy, ov, sat;
 838
 839   int temp;
 840
 841   /* Compute the result.  */
 842   temp = (OP[0] & 0x1f);
 843   temp = (temp << 27) >> 27;
 844   op0 = temp;
 845   op1 = State.regs[OP[1]];
 846   result = op0 + op1;
 847
 848   /* Compute the condition codes.  */
 849   z = (result == 0);
 850   s = (result & 0x80000000);
 851   cy = (result < op0 || result < op1);
 852   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 853         && (op0 & 0x80000000) != (result & 0x80000000));
 854   sat = ov;
 855
 856   /* Store the result and condition codes.  */
 857   State.regs[OP[1]] = result;
 858   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 859   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 860                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 861                 | (sat ? PSW_SAT : 0));
 862
 863   /* Handle saturated results.  */
 864   if (sat && (op0 & 0x80000000))
 865     State.regs[OP[1]] = 0x80000000;
 866   else if (sat)
 867     State.regs[OP[1]] = 0x7fffffff;
 868 }
 869
 870 /* satsub reg1, reg2 */
 871 void
 872 OP_A0 ()
 873 {
 874   unsigned int op0, op1, result, z, s, cy, ov, sat;
 875
 876   /* Compute the result.  */
 877   op0 = State.regs[OP[0]];
 878   op1 = State.regs[OP[1]];
 879   result = op1 - op0;
 880
 881   /* Compute the condition codes.  */
 882   z = (result == 0);
 883   s = (result & 0x80000000);
 884   cy = (result < -op0);
 885   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 886         && (op1 & 0x80000000) != (result & 0x80000000));
 887   sat = ov;
 888
 889   /* Store the result and condition codes.  */
 890   State.regs[OP[1]] = result;
 891   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 892   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 893                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 894                 | (sat ? PSW_SAT : 0));
 895
 896   /* Handle saturated results.  */
 897   if (sat && (op1 & 0x80000000))
 898     State.regs[OP[1]] = 0x80000000;
 899   else if (sat)
 900     State.regs[OP[1]] = 0x7fffffff;
 901 }
 902
 903 /* satsubi sign_extend(imm16), reg */
 904 void
 905 OP_660 ()
 906 {
 907   unsigned int op0, op1, result, z, s, cy, ov, sat;
 908   int temp;
 909
 910   /* Compute the result.  */
 911   temp = (OP[0] & 0xffff);
 912   temp = (temp << 16) >> 16;
 913   op0 = temp;
 914   op1 = State.regs[OP[1]];
 915   result = op1 - op0;
 916
 917   /* Compute the condition codes.  */
 918   z = (result == 0);
 919   s = (result & 0x80000000);
 920   cy = (result < -op0);
 921   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 922         && (op1 & 0x80000000) != (result & 0x80000000));
 923   sat = ov;
 924
 925   /* Store the result and condition codes.  */
 926   State.regs[OP[1]] = result;
 927   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 928   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 929                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 930                 | (sat ? PSW_SAT : 0));
 931
 932   /* Handle saturated results.  */
 933   if (sat && (op1 & 0x80000000))
 934     State.regs[OP[1]] = 0x80000000;
 935   else if (sat)
 936     State.regs[OP[1]] = 0x7fffffff;
 937 }
 938
 939 void
 940 OP_80 ()
 941 {
 942   unsigned int op0, op1, result, z, s, cy, ov, sat;
 943
 944   /* Compute the result.  */
 945   op0 = State.regs[OP[0]];
 946   op1 = State.regs[OP[1]];
 947   result = op0 - op1;
 948
 949   /* Compute the condition codes.  */
 950   z = (result == 0);
 951   s = (result & 0x80000000);
 952   cy = (result < -op0);
 953   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 954         && (op1 & 0x80000000) != (result & 0x80000000));
 955   sat = ov;
 956
 957   /* Store the result and condition codes.  */
 958   State.regs[OP[1]] = result;
 959   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 960   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 961                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
 962                 | (sat ? PSW_SAT : 0));
 963
 964   /* Handle saturated results.  */
 965   if (sat && (op0 & 0x80000000))
 966     State.regs[OP[1]] = 0x80000000;
 967   else if (sat)
 968     State.regs[OP[1]] = 0x7fffffff;
 969 }
 970
 971 /* tst reg,reg */
 972 void
 973 OP_160 ()
 974 {
 975   unsigned int op0, op1, result, z, s, cy, ov;
 976
 977   /* Compute the result.  */
 978   op0 = State.regs[OP[0]];
 979   op1 = State.regs[OP[1]];
 980   result = op0 & op1;
 981
 982   /* Compute the condition codes.  */
 983   z = (result == 0);
 984   s = (result & 0x80000000);
 985
 986   /* Store the condition codes.  */
 987   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
 988   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 989 }
 990
 991 /* mov reg, reg */
 992 void
 993 OP_0 ()
 994 {
 995   State.regs[OP[1]] = State.regs[OP[0]];
 996 }
 997
 998 /* mov sign_extend(imm5), reg */
 999 void
1000 OP_200 ()
1001 {
1002   int value = OP[0];
1003
1004   value = (value << 27) >> 27;
1005   State.regs[OP[1]] = value;
1006 }
1007
1008 /* movea sign_extend(imm16), reg, reg  */
1009
1010 void
1011 OP_620 ()
1012 {
1013   int value = OP[0];
1014
1015   value = (value << 16) >> 16;
1016
1017   State.regs[OP[2]] = State.regs[OP[1]] + value;
1018 }
1019
1020 /* movhi imm16, reg, reg */
1021 void
1022 OP_640 ()
1023 {
1024   int value = OP[0];
1025
1026   value = (value & 0xffff) << 16;
1027
1028   State.regs[OP[2]] = State.regs[OP[1]] + value;
1029 }
1030
1031 /* sar zero_extend(imm5),reg1 */
1032 void
1033 OP_2A0 ()
1034 {
1035   unsigned int op0, op1, result, z, s, cy, ov;
1036
1037   op0 = OP[0] & 0x1f;
1038   op1 = State.regs[OP[1]];
1039   result = (signed)op1 >> op0;
1040
1041   /* Compute the condition codes.  */
1042   z = (result == 0);
1043   s = (result & 0x80000000);
1044   cy = (op1 & (1 << (op0 - 1)));
1045
1046   /* Store the result and condition codes.  */
1047   State.regs[OP[1]] = result;
1048   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1049   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1050                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1051 }
1052
1053 /* sar reg1, reg2 */
1054 void
1055 OP_A007E0 ()
1056 {
1057   unsigned int op0, op1, result, z, s, cy, ov;
1058
1059   op0 = State.regs[OP[0]] & 0x1f;
1060   op1 = State.regs[OP[1]];
1061   result = (signed)op1 >> op0;
1062
1063   /* Compute the condition codes.  */
1064   z = (result == 0);
1065   s = (result & 0x80000000);
1066   cy = (op1 & (1 << (op0 - 1)));
1067
1068   /* Store the result and condition codes.  */
1069   State.regs[OP[1]] = result;
1070   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1071   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1072                 | (cy ? PSW_CY : 0));
1073 }
1074
1075 /* shl zero_extend(imm5),reg1 */
1076 void
1077 OP_2C0 ()
1078 {
1079   unsigned int op0, op1, result, z, s, cy, ov;
1080
1081   op0 = OP[0] & 0x1f;
1082   op1 = State.regs[OP[1]];
1083   result = op1 << op0;
1084
1085   /* Compute the condition codes.  */
1086   z = (result == 0);
1087   s = (result & 0x80000000);
1088   cy = (op1 & (1 << (32 - op0)));
1089
1090   /* Store the result and condition codes.  */
1091   State.regs[OP[1]] = result;
1092   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1093   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1094                 | (cy ? PSW_CY : 0));
1095 }
1096
1097 /* shl reg1, reg2 */
1098 void
1099 OP_C007E0 ()
1100 {
1101   unsigned int op0, op1, result, z, s, cy, ov;
1102
1103   op0 = State.regs[OP[0]] & 0x1f;
1104   op1 = State.regs[OP[1]];
1105   result = op1 << op0;
1106
1107   /* Compute the condition codes.  */
1108   z = (result == 0);
1109   s = (result & 0x80000000);
1110   cy = (op1 & (1 << (32 - op0)));
1111
1112   /* Store the result and condition codes.  */
1113   State.regs[OP[1]] = result;
1114   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1115   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1116                 | (cy ? PSW_CY : 0));
1117 }
1118
1119 /* shr zero_extend(imm5),reg1 */
1120 void
1121 OP_280 ()
1122 {
1123   unsigned int op0, op1, result, z, s, cy, ov;
1124
1125   op0 = OP[0] & 0x1f;
1126   op1 = State.regs[OP[1]];
1127   result = op1 >> op0;
1128
1129   /* Compute the condition codes.  */
1130   z = (result == 0);
1131   s = (result & 0x80000000);
1132   cy = (op1 & (1 << (op0 - 1)));
1133
1134   /* Store the result and condition codes.  */
1135   State.regs[OP[1]] = result;
1136   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1137   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1138                 | (cy ? PSW_CY : 0));
1139 }
1140
1141 /* shr reg1, reg2 */
1142 void
1143 OP_8007E0 ()
1144 {
1145   unsigned int op0, op1, result, z, s, cy, ov;
1146
1147   op0 = State.regs[OP[0]] & 0x1f;
1148   op1 = State.regs[OP[1]];
1149   result = op1 >> op0;
1150
1151   /* Compute the condition codes.  */
1152   z = (result == 0);
1153   s = (result & 0x80000000);
1154   cy = (op1 & (1 << (op0 - 1)));
1155
1156   /* Store the result and condition codes.  */
1157   State.regs[OP[1]] = result;
1158   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1159   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1160                 | (cy ? PSW_CY : 0));
1161 }
1162
1163 /* or reg, reg */
1164 void
1165 OP_100 ()
1166 {
1167   unsigned int op0, op1, result, z, s, cy, ov;
1168
1169   /* Compute the result.  */
1170   op0 = State.regs[OP[0]];
1171   op1 = State.regs[OP[1]];
1172   result = op0 | op1;
1173
1174   /* Compute the condition codes.  */
1175   z = (result == 0);
1176   s = (result & 0x80000000);
1177
1178   /* Store the result and condition codes.  */
1179   State.regs[OP[1]] = result;
1180   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1181   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1182 }
1183
1184 /* ori zero_extend(imm16), reg, reg */
1185 void
1186 OP_680 ()
1187 {
1188   unsigned int op0, op1, result, z, s, cy, ov;
1189
1190   op0 = OP[0] & 0xffff;
1191   op1 = State.regs[OP[1]];
1192   result = op0 | op1;
1193
1194   /* Compute the condition codes.  */
1195   z = (result == 0);
1196   s = (result & 0x80000000);
1197
1198   /* Store the result and condition codes.  */
1199   State.regs[OP[2]] = result;
1200   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1201   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1202 }
1203
1204 /* and reg, reg */
1205 void
1206 OP_140 ()
1207 {
1208   unsigned int op0, op1, result, z, s, cy, ov;
1209
1210   /* Compute the result.  */
1211   op0 = State.regs[OP[0]];
1212   op1 = State.regs[OP[1]];
1213   result = op0 & op1;
1214
1215   /* Compute the condition codes.  */
1216   z = (result == 0);
1217   s = (result & 0x80000000);
1218
1219   /* Store the result and condition codes.  */
1220   State.regs[OP[1]] = result;
1221   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1222   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1223 }
1224
1225 /* andi zero_extend(imm16), reg, reg */
1226 void
1227 OP_6C0 ()
1228 {
1229   unsigned int op0, op1, result, z, s, cy, ov;
1230
1231   op0 = OP[0] & 0xffff;
1232   op1 = State.regs[OP[1]];
1233   result = op0 & op1;
1234
1235   /* Compute the condition codes.  */
1236   z = (result == 0);
1237
1238   /* Store the result and condition codes.  */
1239   State.regs[OP[2]] = result;
1240   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1241   State.sregs[5] |= (z ? PSW_Z : 0);
1242 }
1243
1244 /* xor reg, reg */
1245 void
1246 OP_120 ()
1247 {
1248   unsigned int op0, op1, result, z, s, cy, ov;
1249
1250   /* Compute the result.  */
1251   op0 = State.regs[OP[0]];
1252   op1 = State.regs[OP[1]];
1253   result = op0 ^ op1;
1254
1255   /* Compute the condition codes.  */
1256   z = (result == 0);
1257   s = (result & 0x80000000);
1258
1259   /* Store the result and condition codes.  */
1260   State.regs[OP[1]] = result;
1261   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1262   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1263 }
1264
1265 /* xori zero_extend(imm16), reg, reg */
1266 void
1267 OP_6A0 ()
1268 {
1269   unsigned int op0, op1, result, z, s, cy, ov;
1270
1271   op0 = OP[0] & 0xffff;
1272   op1 = State.regs[OP[1]];
1273   result = op0 ^ op1;
1274
1275   /* Compute the condition codes.  */
1276   z = (result == 0);
1277   s = (result & 0x80000000);
1278
1279   /* Store the result and condition codes.  */
1280   State.regs[OP[2]] = result;
1281   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1282   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1283 }
1284
1285 /* not reg1, reg2 */
1286 void
1287 OP_20 ()
1288 {
1289   unsigned int op0, result, z, s, cy, ov;
1290
1291   /* Compute the result.  */
1292   op0 = State.regs[OP[0]];
1293   result = ~op0;
1294
1295   /* Compute the condition codes.  */
1296   z = (result == 0);
1297   s = (result & 0x80000000);
1298
1299   /* Store the result and condition codes.  */
1300   State.regs[OP[1]] = result;
1301   State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1302   State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1303 }
1304
1305 /* set1 */
1306 void
1307 OP_7C0 ()
1308 {
1309   unsigned int op0, op1, op2;
1310   int result, temp;
1311
1312   op0 = State.regs[OP[0]];
1313   op1 = OP[1] & 0x7;
1314   temp = OP[2];
1315   temp = (temp << 16) >> 16;
1316   op2 = temp;
1317   temp = get_byte (State.mem + op0 + op2);
1318   State.sregs[5] &= ~PSW_Z;
1319   if ((temp & (1 << op1)) == 0)
1320     State.sregs[5] |= PSW_Z;
1321   temp |= ~(1 << op1);
1322   put_byte (State.mem + op0 + op2, temp);
1323 }
1324
1325 /* not1 */
1326 void
1327 OP_47C0 ()
1328 {
1329   unsigned int op0, op1, op2;
1330   int result, temp;
1331
1332   op0 = State.regs[OP[0]];
1333   op1 = OP[1] & 0x7;
1334   temp = OP[2];
1335   temp = (temp << 16) >> 16;
1336   op2 = temp;
1337   temp = get_byte (State.mem + op0 + op2);
1338   State.sregs[5] &= ~PSW_Z;
1339   if ((temp & (1 << op1)) == 0)
1340     State.sregs[5] |= PSW_Z;
1341   temp ^= ~(1 << op1);
1342   put_byte (State.mem + op0 + op2, temp);
1343 }
1344
1345 /* clr1 */
1346 void
1347 OP_87C0 ()
1348 {
1349   unsigned int op0, op1, op2;
1350   int result, temp;
1351
1352   op0 = State.regs[OP[0]];
1353   op1 = OP[1] & 0x7;
1354   temp = OP[2];
1355   temp = (temp << 16) >> 16;
1356   op2 = temp;
1357   temp = get_byte (State.mem + op0 + op2);
1358   State.sregs[5] &= ~PSW_Z;
1359   if ((temp & (1 << op1)) == 0)
1360     State.sregs[5] |= PSW_Z;
1361   temp &= ~(1 << op1);
1362   put_byte (State.mem + op0 + op2, temp);
1363 }
1364
1365 /* tst1 */
1366 void
1367 OP_C7C0 ()
1368 {
1369   unsigned int op0, op1, op2;
1370   int result, temp;
1371
1372   op0 = State.regs[OP[0]];
1373   op1 = OP[1] & 0x7;
1374   temp = OP[2];
1375   temp = (temp << 16) >> 16;
1376   op2 = temp;
1377   temp = get_byte (State.mem + op0 + op2);
1378   State.sregs[5] &= ~PSW_Z;
1379   if ((temp & (1 << op1)) == 0)
1380     State.sregs[5] |= PSW_Z;
1381 }
1382
1383 /* di */
1384 void
1385 OP_16007E0 ()
1386 {
1387   State.sregs[5] |= PSW_ID;
1388 }
1389
1390 /* ei */
1391 void
1392 OP_16087E0 ()
1393 {
1394   State.sregs[5] &= ~PSW_ID;
1395 }
1396
1397 /* halt, not supported */
1398 void
1399 OP_12007E0 ()
1400 {
1401   abort ();
1402 }
1403
1404 /* reti, not supported */
1405 void
1406 OP_14007E0 ()
1407 {
1408   abort ();
1409 }
1410
1411 /* trap, not supportd */
1412 void
1413 OP_10007E0 ()
1414 {
1415   abort ();
1416 }
1417
1418 /* ldsr, reg,reg */
1419 void
1420 OP_2007E0 ()
1421 {
1422   unsigned int op0;
1423
1424   op0 = State.regs[OP[0]];
1425   State.sregs[OP[1]] = op0;
1426 }
1427
1428 /* stsr, not supported */
1429 void
1430 OP_4007E0 ()
1431 {
1432   unsigned int op0;
1433
1434   op0 = State.sregs[OP[1]];
1435   State.regs[OP[0]] = op0;
1436 }
1437