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Cleanups to compile under FreeBSD
[binutils-gdb.git] / sim / v850 / simops.c
1 #include <signal.h>
2 #include "v850_sim.h"
3 #include "simops.h"
4 #include "sys/syscall.h"
5 #include "bfd.h"
6 #include <errno.h>
7 #if !defined(__GO32__) && !defined(_WIN32)
8 #include <sys/stat.h>
9 #include <sys/times.h>
10 #include <sys/time.h>
11 #endif
12
13 enum op_types {
14 OP_UNKNOWN,
15 OP_NONE,
16 OP_TRAP,
17 OP_REG,
18 OP_REG_REG,
19 OP_REG_REG_CMP,
20 OP_REG_REG_MOVE,
21 OP_IMM_REG,
22 OP_IMM_REG_CMP,
23 OP_IMM_REG_MOVE,
24 OP_COND_BR,
25 OP_LOAD16,
26 OP_STORE16,
27 OP_LOAD32,
28 OP_STORE32,
29 OP_JUMP,
30 OP_IMM_REG_REG,
31 OP_UIMM_REG_REG,
32 OP_BIT,
33 OP_EX1,
34 OP_EX2,
35 OP_LDSR,
36 OP_STSR
37 };
38
39 #ifdef DEBUG
40 static void trace_input PARAMS ((char *name, enum op_types type, int size));
41 static void trace_output PARAMS ((enum op_types result));
42 static int init_text_p = 0;
43 static asection *text;
44 static bfd_vma text_start;
45 static bfd_vma text_end;
46 extern bfd *exec_bfd;
47
48 #ifndef SIZE_INSTRUCTION
49 #define SIZE_INSTRUCTION 6
50 #endif
51
52 #ifndef SIZE_OPERANDS
53 #define SIZE_OPERANDS 16
54 #endif
55
56 #ifndef SIZE_VALUES
57 #define SIZE_VALUES 11
58 #endif
59
60 #ifndef SIZE_LOCATION
61 #define SIZE_LOCATION 40
62 #endif
63
64 static void
65 trace_input (name, type, size)
66 char *name;
67 enum op_types type;
68 int size;
69 {
70 char buf[1024];
71 char *p;
72 uint32 values[3];
73 int num_values, i;
74 char *cond;
75 asection *s;
76 const char *filename;
77 const char *functionname;
78 unsigned int linenumber;
79
80 if ((v850_debug & DEBUG_TRACE) == 0)
81 return;
82
83 buf[0] = '\0';
84 if (!init_text_p)
85 {
86 init_text_p = 1;
87 for (s = exec_bfd->sections; s; s = s->next)
88 if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
89 {
90 text = s;
91 text_start = bfd_get_section_vma (exec_bfd, s);
92 text_end = text_start + bfd_section_size (exec_bfd, s);
93 break;
94 }
95 }
96
97 if (text && PC >= text_start && PC < text_end)
98 {
99 filename = (const char *)0;
100 functionname = (const char *)0;
101 linenumber = 0;
102 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
103 &filename, &functionname, &linenumber))
104 {
105 p = buf;
106 if (linenumber)
107 {
108 sprintf (p, "Line %5d ", linenumber);
109 p += strlen (p);
110 }
111
112 if (functionname)
113 {
114 sprintf (p, "Func %s ", functionname);
115 p += strlen (p);
116 }
117 else if (filename)
118 {
119 char *q = (char *) strrchr (filename, '/');
120 sprintf (p, "File %s ", (q) ? q+1 : filename);
121 p += strlen (p);
122 }
123
124 if (*p == ' ')
125 *p = '\0';
126 }
127 }
128
129 (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
130 (unsigned)PC,
131 SIZE_LOCATION, SIZE_LOCATION, buf,
132 SIZE_INSTRUCTION, name);
133
134 switch (type)
135 {
136 default:
137 case OP_UNKNOWN:
138 case OP_NONE:
139 strcpy (buf, "unknown");
140 break;
141
142 case OP_TRAP:
143 sprintf (buf, "%d", OP[0]);
144 break;
145
146 case OP_REG:
147 sprintf (buf, "r%d", OP[0]);
148 break;
149
150 case OP_REG_REG:
151 case OP_REG_REG_CMP:
152 case OP_REG_REG_MOVE:
153 sprintf (buf, "r%d,r%d", OP[0], OP[1]);
154 break;
155
156 case OP_IMM_REG:
157 case OP_IMM_REG_CMP:
158 case OP_IMM_REG_MOVE:
159 sprintf (buf, "%d,r%d", OP[0], OP[1]);
160 break;
161
162 case OP_COND_BR:
163 sprintf (buf, "%d", SEXT9 (OP[0]));
164 break;
165
166 case OP_LOAD16:
167 sprintf (buf, "%d[r30],r%d", OP[1] * size, OP[0]);
168 break;
169
170 case OP_STORE16:
171 sprintf (buf, "r%d,%d[r30]", OP[0], OP[1] * size);
172 break;
173
174 case OP_LOAD32:
175 sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
176 break;
177
178 case OP_STORE32:
179 sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
180 break;
181
182 case OP_JUMP:
183 sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
184 break;
185
186 case OP_IMM_REG_REG:
187 sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
188 break;
189
190 case OP_UIMM_REG_REG:
191 sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
192 break;
193
194 case OP_BIT:
195 sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
196 break;
197
198 case OP_EX1:
199 switch (OP[0] & 0xf)
200 {
201 default: cond = "?"; break;
202 case 0x0: cond = "v"; break;
203 case 0x1: cond = "c"; break;
204 case 0x2: cond = "z"; break;
205 case 0x3: cond = "nh"; break;
206 case 0x4: cond = "s"; break;
207 case 0x5: cond = "t"; break;
208 case 0x6: cond = "lt"; break;
209 case 0x7: cond = "le"; break;
210 case 0x8: cond = "nv"; break;
211 case 0x9: cond = "nc"; break;
212 case 0xa: cond = "nz"; break;
213 case 0xb: cond = "h"; break;
214 case 0xc: cond = "ns"; break;
215 case 0xd: cond = "sa"; break;
216 case 0xe: cond = "ge"; break;
217 case 0xf: cond = "gt"; break;
218 }
219
220 sprintf (buf, "%s,r%d", cond, OP[1]);
221 break;
222
223 case OP_EX2:
224 strcpy (buf, "EX2");
225 break;
226
227 case OP_LDSR:
228 case OP_STSR:
229 sprintf (buf, "r%d,s%d", OP[0], OP[1]);
230 break;
231 }
232
233 if ((v850_debug & DEBUG_VALUES) == 0)
234 {
235 (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
236 }
237 else
238 {
239 (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
240 switch (type)
241 {
242 default:
243 case OP_UNKNOWN:
244 case OP_NONE:
245 case OP_TRAP:
246 num_values = 0;
247 break;
248
249 case OP_REG:
250 case OP_REG_REG_MOVE:
251 values[0] = State.regs[OP[0]];
252 num_values = 1;
253 break;
254
255 case OP_REG_REG:
256 case OP_REG_REG_CMP:
257 values[0] = State.regs[OP[1]];
258 values[1] = State.regs[OP[0]];
259 num_values = 2;
260 break;
261
262 case OP_IMM_REG:
263 case OP_IMM_REG_CMP:
264 values[0] = SEXT5 (OP[0]);
265 values[1] = OP[1];
266 num_values = 2;
267 break;
268
269 case OP_IMM_REG_MOVE:
270 values[0] = SEXT5 (OP[0]);
271 num_values = 1;
272 break;
273
274 case OP_COND_BR:
275 values[0] = State.pc;
276 values[1] = SEXT9 (OP[0]);
277 values[2] = PSW;
278 num_values = 3;
279 break;
280
281 case OP_LOAD16:
282 values[0] = OP[1] * size;
283 values[1] = State.regs[30];
284 num_values = 2;
285 break;
286
287 case OP_STORE16:
288 values[0] = State.regs[OP[0]];
289 values[1] = OP[1] * size;
290 values[2] = State.regs[30];
291 num_values = 3;
292 break;
293
294 case OP_LOAD32:
295 values[0] = SEXT16 (OP[2]);
296 values[1] = State.regs[OP[0]];
297 num_values = 2;
298 break;
299
300 case OP_STORE32:
301 values[0] = State.regs[OP[1]];
302 values[1] = SEXT16 (OP[2]);
303 values[2] = State.regs[OP[0]];
304 num_values = 3;
305 break;
306
307 case OP_JUMP:
308 values[0] = SEXT22 (OP[0]);
309 values[1] = State.pc;
310 num_values = 2;
311 break;
312
313 case OP_IMM_REG_REG:
314 values[0] = SEXT16 (OP[0]) << size;
315 values[1] = State.regs[OP[1]];
316 num_values = 2;
317 break;
318
319 case OP_UIMM_REG_REG:
320 values[0] = (OP[0] & 0xffff) << size;
321 values[1] = State.regs[OP[1]];
322 num_values = 2;
323 break;
324
325 case OP_BIT:
326 num_values = 0;
327 break;
328
329 case OP_EX1:
330 values[0] = PSW;
331 num_values = 1;
332 break;
333
334 case OP_EX2:
335 num_values = 0;
336 break;
337
338 case OP_LDSR:
339 values[0] = State.regs[OP[0]];
340 num_values = 1;
341 break;
342
343 case OP_STSR:
344 values[0] = State.sregs[OP[1]];
345 num_values = 1;
346 }
347
348 for (i = 0; i < num_values; i++)
349 (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
350
351 while (i++ < 3)
352 (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
353 }
354 }
355
356 static void
357 trace_output (result)
358 enum op_types result;
359 {
360 if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
361 {
362 switch (result)
363 {
364 default:
365 case OP_UNKNOWN:
366 case OP_NONE:
367 case OP_TRAP:
368 case OP_REG:
369 case OP_REG_REG_CMP:
370 case OP_IMM_REG_CMP:
371 case OP_COND_BR:
372 case OP_STORE16:
373 case OP_STORE32:
374 case OP_BIT:
375 case OP_EX2:
376 break;
377
378 case OP_LOAD16:
379 case OP_STSR:
380 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
381 (unsigned long)State.regs[OP[0]]);
382 break;
383
384 case OP_REG_REG:
385 case OP_REG_REG_MOVE:
386 case OP_IMM_REG:
387 case OP_IMM_REG_MOVE:
388 case OP_LOAD32:
389 case OP_EX1:
390 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
391 (unsigned long)State.regs[OP[1]]);
392 break;
393
394 case OP_IMM_REG_REG:
395 case OP_UIMM_REG_REG:
396 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
397 (unsigned long)State.regs[OP[2]]);
398 break;
399
400 case OP_JUMP:
401 if (OP[1] != 0)
402 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
403 (unsigned long)State.regs[OP[1]]);
404 break;
405
406 case OP_LDSR:
407 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
408 (unsigned long)State.sregs[OP[1]]);
409 break;
410 }
411
412 (*v850_callback->printf_filtered) (v850_callback, "\n");
413 }
414 }
415
416 #else
417 #define trace_input(NAME, IN1, IN2)
418 #define trace_output(RESULT)
419 #endif
420
421 \f
422 /* sld.b */
423 void
424 OP_300 ()
425 {
426 unsigned int op2;
427 int result, temp;
428
429 trace_input ("sld.b", OP_LOAD16, 1);
430 temp = OP[1];
431 temp &= 0x7f;
432 op2 = temp;
433 result = load_mem (State.regs[30] + op2, 1);
434 State.regs[OP[0]] = SEXT8 (result);
435 trace_output (OP_LOAD16);
436 }
437
438 /* sld.h */
439 void
440 OP_400 ()
441 {
442 unsigned int op2;
443 int result, temp;
444
445 trace_input ("sld.h", OP_LOAD16, 2);
446 temp = OP[1];
447 temp &= 0x7f;
448 op2 = temp << 1;
449 result = load_mem (State.regs[30] + op2, 2);
450 State.regs[OP[0]] = SEXT16 (result);
451 trace_output (OP_LOAD16);
452 }
453
454 /* sld.w */
455 void
456 OP_500 ()
457 {
458 unsigned int op2;
459 int result, temp;
460
461 trace_input ("sld.w", OP_LOAD16, 4);
462 temp = OP[1];
463 temp &= 0x7e;
464 op2 = temp << 1;
465 result = load_mem (State.regs[30] + op2, 4);
466 State.regs[OP[0]] = result;
467 trace_output (OP_LOAD16);
468 }
469
470 /* sst.b */
471 void
472 OP_380 ()
473 {
474 unsigned int op0, op1;
475 int temp;
476
477 trace_input ("sst.b", OP_STORE16, 1);
478 op0 = State.regs[OP[0]];
479 temp = OP[1];
480 temp &= 0x7f;
481 op1 = temp;
482 store_mem (State.regs[30] + op1, 1, op0);
483 trace_output (OP_STORE16);
484 }
485
486 /* sst.h */
487 void
488 OP_480 ()
489 {
490 unsigned int op0, op1;
491 int temp;
492
493 trace_input ("sst.h", OP_STORE16, 2);
494 op0 = State.regs[OP[0]];
495 temp = OP[1];
496 temp &= 0x7f;
497 op1 = temp << 1;
498 store_mem (State.regs[30] + op1, 2, op0);
499 trace_output (OP_STORE16);
500 }
501
502 /* sst.w */
503 void
504 OP_501 ()
505 {
506 unsigned int op0, op1;
507 int temp;
508
509 trace_input ("sst.w", OP_STORE16, 4);
510 op0 = State.regs[OP[0]];
511 temp = OP[1];
512 temp &= 0x7e;
513 op1 = temp << 1;
514 store_mem (State.regs[30] + op1, 4, op0);
515 trace_output (OP_STORE16);
516 }
517
518 /* ld.b */
519 void
520 OP_700 ()
521 {
522 unsigned int op0, op2;
523 int result, temp;
524
525 trace_input ("ld.b", OP_LOAD32, 1);
526 op0 = State.regs[OP[0]];
527 temp = SEXT16 (OP[2]);
528 op2 = temp;
529 result = load_mem (op0 + op2, 1);
530 State.regs[OP[1]] = SEXT8 (result);
531 trace_output (OP_LOAD32);
532 }
533
534 /* ld.h */
535 void
536 OP_720 ()
537 {
538 unsigned int op0, op2;
539 int result, temp;
540
541 trace_input ("ld.h", OP_LOAD32, 2);
542 op0 = State.regs[OP[0]];
543 temp = SEXT16 (OP[2]);
544 temp &= ~0x1;
545 op2 = temp;
546 result = load_mem (op0 + op2, 2);
547 State.regs[OP[1]] = SEXT16 (result);
548 trace_output (OP_LOAD32);
549 }
550
551 /* ld.w */
552 void
553 OP_10720 ()
554 {
555 unsigned int op0, op2;
556 int result, temp;
557
558 trace_input ("ld.w", OP_LOAD32, 4);
559 op0 = State.regs[OP[0]];
560 temp = SEXT16 (OP[2]);
561 temp &= ~0x1;
562 op2 = temp;
563 result = load_mem (op0 + op2, 4);
564 State.regs[OP[1]] = result;
565 trace_output (OP_LOAD32);
566 }
567
568 /* st.b */
569 void
570 OP_740 ()
571 {
572 unsigned int op0, op1, op2;
573 int temp;
574
575 trace_input ("st.b", OP_STORE32, 1);
576 op0 = State.regs[OP[0]];
577 op1 = State.regs[OP[1]];
578 temp = SEXT16 (OP[2]);
579 op2 = temp;
580 store_mem (op0 + op2, 1, op1);
581 trace_output (OP_STORE32);
582 }
583
584 /* st.h */
585 void
586 OP_760 ()
587 {
588 unsigned int op0, op1, op2;
589 int temp;
590
591 trace_input ("st.h", OP_STORE32, 2);
592 op0 = State.regs[OP[0]];
593 op1 = State.regs[OP[1]];
594 temp = SEXT16 (OP[2] & ~0x1);
595 op2 = temp;
596 store_mem (op0 + op2, 2, op1);
597 trace_output (OP_STORE32);
598 }
599
600 /* st.w */
601 void
602 OP_10760 ()
603 {
604 unsigned int op0, op1, op2;
605 int temp;
606
607 trace_input ("st.w", OP_STORE32, 4);
608 op0 = State.regs[OP[0]];
609 op1 = State.regs[OP[1]];
610 temp = SEXT16 (OP[2] & ~0x1);
611 op2 = temp;
612 store_mem (op0 + op2, 4, op1);
613 trace_output (OP_STORE32);
614 }
615
616 /* bv disp9 */
617 void
618 OP_580 ()
619 {
620 unsigned int psw;
621 int op0;
622
623 trace_input ("bv", OP_COND_BR, 0);
624 op0 = SEXT9 (OP[0]);
625 psw = PSW;
626
627 if ((psw & PSW_OV) != 0)
628 State.pc += op0;
629 else
630 State.pc += 2;
631 trace_output (OP_COND_BR);
632 }
633
634 /* bl disp9 */
635 void
636 OP_581 ()
637 {
638 unsigned int psw;
639 int op0;
640
641 trace_input ("bl", OP_COND_BR, 0);
642 op0 = SEXT9 (OP[0]);
643 psw = PSW;
644
645 if ((psw & PSW_CY) != 0)
646 State.pc += op0;
647 else
648 State.pc += 2;
649 trace_output (OP_COND_BR);
650 }
651
652 /* be disp9 */
653 void
654 OP_582 ()
655 {
656 unsigned int psw;
657 int op0;
658
659 trace_input ("be", OP_COND_BR, 0);
660 op0 = SEXT9 (OP[0]);
661 psw = PSW;
662
663 if ((psw & PSW_Z) != 0)
664 State.pc += op0;
665 else
666 State.pc += 2;
667 trace_output (OP_COND_BR);
668 }
669
670 /* bnh disp 9*/
671 void
672 OP_583 ()
673 {
674 unsigned int psw;
675 int op0;
676
677 trace_input ("bnh", OP_COND_BR, 0);
678 op0 = SEXT9 (OP[0]);
679 psw = PSW;
680
681 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
682 State.pc += op0;
683 else
684 State.pc += 2;
685 trace_output (OP_COND_BR);
686 }
687
688 /* bn disp9 */
689 void
690 OP_584 ()
691 {
692 unsigned int psw;
693 int op0;
694
695 trace_input ("bn", OP_COND_BR, 0);
696 op0 = SEXT9 (OP[0]);
697 psw = PSW;
698
699 if ((psw & PSW_S) != 0)
700 State.pc += op0;
701 else
702 State.pc += 2;
703 trace_output (OP_COND_BR);
704 }
705
706 /* br disp9 */
707 void
708 OP_585 ()
709 {
710 unsigned int psw;
711 int op0;
712
713 trace_input ("br", OP_COND_BR, 0);
714 op0 = SEXT9 (OP[0]);
715 State.pc += op0;
716 trace_output (OP_COND_BR);
717 }
718
719 /* blt disp9 */
720 void
721 OP_586 ()
722 {
723 unsigned int psw;
724 int op0;
725
726 trace_input ("blt", OP_COND_BR, 0);
727 op0 = SEXT9 (OP[0]);
728 psw = PSW;
729
730 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
731 State.pc += op0;
732 else
733 State.pc += 2;
734 trace_output (OP_COND_BR);
735 }
736
737 /* ble disp9 */
738 void
739 OP_587 ()
740 {
741 unsigned int psw;
742 int op0;
743
744 trace_input ("ble", OP_COND_BR, 0);
745 op0 = SEXT9 (OP[0]);
746 psw = PSW;
747
748 if ((((psw & PSW_Z) != 0)
749 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
750 State.pc += op0;
751 else
752 State.pc += 2;
753 trace_output (OP_COND_BR);
754 }
755
756 /* bnv disp9 */
757 void
758 OP_588 ()
759 {
760 unsigned int psw;
761 int op0;
762
763 trace_input ("bnv", OP_COND_BR, 0);
764 op0 = SEXT9 (OP[0]);
765 psw = PSW;
766
767 if ((psw & PSW_OV) == 0)
768 State.pc += op0;
769 else
770 State.pc += 2;
771 trace_output (OP_COND_BR);
772 }
773
774 /* bnl disp9 */
775 void
776 OP_589 ()
777 {
778 unsigned int psw;
779 int op0;
780
781 trace_input ("bnl", OP_COND_BR, 0);
782 op0 = SEXT9 (OP[0]);
783 psw = PSW;
784
785 if ((psw & PSW_CY) == 0)
786 State.pc += op0;
787 else
788 State.pc += 2;
789 trace_output (OP_COND_BR);
790 }
791
792 /* bne disp9 */
793 void
794 OP_58A ()
795 {
796 unsigned int psw;
797 int op0;
798
799 trace_input ("bne", OP_COND_BR, 0);
800 op0 = SEXT9 (OP[0]);
801 psw = PSW;
802
803 if ((psw & PSW_Z) == 0)
804 State.pc += op0;
805 else
806 State.pc += 2;
807 trace_output (OP_COND_BR);
808 }
809
810 /* bh disp9 */
811 void
812 OP_58B ()
813 {
814 unsigned int psw;
815 int op0;
816
817 trace_input ("bh", OP_COND_BR, 0);
818 op0 = SEXT9 (OP[0]);
819 psw = PSW;
820
821 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
822 State.pc += op0;
823 else
824 State.pc += 2;
825 trace_output (OP_COND_BR);
826 }
827
828 /* bp disp9 */
829 void
830 OP_58C ()
831 {
832 unsigned int psw;
833 int op0;
834
835 trace_input ("bp", OP_COND_BR, 0);
836 op0 = SEXT9 (OP[0]);
837 psw = PSW;
838
839 if ((psw & PSW_S) == 0)
840 State.pc += op0;
841 else
842 State.pc += 2;
843 trace_output (OP_COND_BR);
844 }
845
846 /* bsa disp9 */
847 void
848 OP_58D ()
849 {
850 unsigned int psw;
851 int op0;
852
853 trace_input ("bsa", OP_COND_BR, 0);
854 op0 = SEXT9 (OP[0]);
855 psw = PSW;
856
857 if ((psw & PSW_SAT) != 0)
858 State.pc += op0;
859 else
860 State.pc += 2;
861 trace_output (OP_COND_BR);
862 }
863
864 /* bge disp9 */
865 void
866 OP_58E ()
867 {
868 unsigned int psw;
869 int op0;
870
871 trace_input ("bge", OP_COND_BR, 0);
872 op0 = SEXT9 (OP[0]);
873 psw = PSW;
874
875 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
876 State.pc += op0;
877 else
878 State.pc += 2;
879 trace_output (OP_COND_BR);
880 }
881
882 /* bgt disp9 */
883 void
884 OP_58F ()
885 {
886 unsigned int psw;
887 int op0;
888
889 trace_input ("bgt", OP_COND_BR, 0);
890 op0 = SEXT9 (OP[0]);
891 psw = PSW;
892
893 if ((((psw & PSW_Z) != 0)
894 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
895 State.pc += op0;
896 else
897 State.pc += 2;
898 trace_output (OP_COND_BR);
899 }
900
901 /* jmp [reg1] */
902 void
903 OP_60 ()
904 {
905 /* interp.c will bump this by +2, so correct for it here. */
906 trace_input ("jmp", OP_REG, 0);
907 State.pc = State.regs[OP[0]] - 2;
908 trace_output (OP_REG);
909 }
910
911 /* jarl disp22, reg */
912 void
913 OP_780 ()
914 {
915 unsigned int op0, opc;
916 int temp;
917
918 trace_input ("jarl", OP_JUMP, 0);
919 temp = SEXT22 (OP[0]);
920 op0 = temp;
921 opc = State.pc;
922
923 State.pc += temp;
924
925 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
926 if (OP[1] != 0)
927 State.regs[OP[1]] = opc + 4;
928 trace_output (OP_JUMP);
929 }
930
931 /* add reg, reg */
932 void
933 OP_1C0 ()
934 {
935 unsigned int op0, op1, result, z, s, cy, ov;
936
937 trace_input ("add", OP_REG_REG, 0);
938 /* Compute the result. */
939 op0 = State.regs[OP[0]];
940 op1 = State.regs[OP[1]];
941 result = op0 + op1;
942
943 /* Compute the condition codes. */
944 z = (result == 0);
945 s = (result & 0x80000000);
946 cy = (result < op0 || result < op1);
947 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
948 && (op0 & 0x80000000) != (result & 0x80000000));
949
950 /* Store the result and condition codes. */
951 State.regs[OP[1]] = result;
952 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
953 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
954 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
955 trace_output (OP_REG_REG);
956 }
957
958 /* add sign_extend(imm5), reg */
959 void
960 OP_240 ()
961 {
962 unsigned int op0, op1, result, z, s, cy, ov;
963 int temp;
964
965 trace_input ("add", OP_IMM_REG, 0);
966
967 /* Compute the result. */
968 temp = SEXT5 (OP[0]);
969 op0 = temp;
970 op1 = State.regs[OP[1]];
971 result = op0 + op1;
972
973 /* Compute the condition codes. */
974 z = (result == 0);
975 s = (result & 0x80000000);
976 cy = (result < op0 || result < op1);
977 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
978 && (op0 & 0x80000000) != (result & 0x80000000));
979
980 /* Store the result and condition codes. */
981 State.regs[OP[1]] = result;
982 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
983 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
984 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
985 trace_output (OP_IMM_REG);
986 }
987
988 /* addi sign_extend(imm16), reg, reg */
989 void
990 OP_600 ()
991 {
992 unsigned int op0, op1, result, z, s, cy, ov;
993 int temp;
994
995 trace_input ("addi", OP_IMM_REG_REG, 0);
996
997 /* Compute the result. */
998 temp = SEXT16 (OP[0]);
999 op0 = temp;
1000 op1 = State.regs[OP[1]];
1001 result = op0 + op1;
1002
1003 /* Compute the condition codes. */
1004 z = (result == 0);
1005 s = (result & 0x80000000);
1006 cy = (result < op0 || result < op1);
1007 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1008 && (op0 & 0x80000000) != (result & 0x80000000));
1009
1010 /* Store the result and condition codes. */
1011 State.regs[OP[2]] = result;
1012 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1013 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1014 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1015 trace_output (OP_IMM_REG_REG);
1016 }
1017
1018 /* sub reg1, reg2 */
1019 void
1020 OP_1A0 ()
1021 {
1022 unsigned int op0, op1, result, z, s, cy, ov;
1023
1024 trace_input ("sub", OP_REG_REG, 0);
1025 /* Compute the result. */
1026 op0 = State.regs[OP[0]];
1027 op1 = State.regs[OP[1]];
1028 result = op1 - op0;
1029
1030 /* Compute the condition codes. */
1031 z = (result == 0);
1032 s = (result & 0x80000000);
1033 cy = (op1 < op0);
1034 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1035 && (op1 & 0x80000000) != (result & 0x80000000));
1036
1037 /* Store the result and condition codes. */
1038 State.regs[OP[1]] = result;
1039 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1040 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1041 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1042 trace_output (OP_REG_REG);
1043 }
1044
1045 /* subr reg1, reg2 */
1046 void
1047 OP_180 ()
1048 {
1049 unsigned int op0, op1, result, z, s, cy, ov;
1050
1051 trace_input ("subr", OP_REG_REG, 0);
1052 /* Compute the result. */
1053 op0 = State.regs[OP[0]];
1054 op1 = State.regs[OP[1]];
1055 result = op0 - op1;
1056
1057 /* Compute the condition codes. */
1058 z = (result == 0);
1059 s = (result & 0x80000000);
1060 cy = (op0 < op1);
1061 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1062 && (op0 & 0x80000000) != (result & 0x80000000));
1063
1064 /* Store the result and condition codes. */
1065 State.regs[OP[1]] = result;
1066 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1067 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1068 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1069 trace_output (OP_REG_REG);
1070 }
1071
1072 /* mulh reg1, reg2 */
1073 void
1074 OP_E0 ()
1075 {
1076 trace_input ("mulh", OP_REG_REG, 0);
1077 State.regs[OP[1]] = (SEXT16 (State.regs[OP[1]])
1078 * SEXT16 (State.regs[OP[0]]));
1079 trace_output (OP_REG_REG);
1080 }
1081
1082 /* mulh sign_extend(imm5), reg2
1083
1084 Condition codes */
1085 void
1086 OP_2E0 ()
1087 {
1088 int value = SEXT5 (OP[0]);
1089
1090 trace_input ("mulh", OP_IMM_REG, 0);
1091 State.regs[OP[1]] = SEXT16 (State.regs[OP[1]]) * value;
1092 trace_output (OP_IMM_REG);
1093 }
1094
1095 /* mulhi imm16, reg1, reg2 */
1096 void
1097 OP_6E0 ()
1098 {
1099 int value = SEXT16 (OP[0]);
1100
1101 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1102 State.regs[OP[2]] = SEXT16 (State.regs[OP[1]]) * value;
1103 trace_output (OP_IMM_REG_REG);
1104 }
1105
1106 /* divh reg1, reg2 */
1107 void
1108 OP_40 ()
1109 {
1110 unsigned int op0, op1, result, ov, s, z;
1111 int temp;
1112
1113 trace_input ("divh", OP_REG_REG, 0);
1114
1115 /* Compute the result. */
1116 temp = SEXT16 (State.regs[OP[0]]);
1117 op0 = temp;
1118 op1 = State.regs[OP[1]];
1119
1120 if (op0 == 0xffffffff && op1 == 0x80000000)
1121 {
1122 result = 0x80000000;
1123 ov = 1;
1124 }
1125 else if (op0 != 0)
1126 {
1127 result = op1 / op0;
1128 ov = 0;
1129 }
1130 else
1131 {
1132 result = 0x0;
1133 ov = 1;
1134 }
1135
1136 /* Compute the condition codes. */
1137 z = (result == 0);
1138 s = (result & 0x80000000);
1139
1140 /* Store the result and condition codes. */
1141 State.regs[OP[1]] = result;
1142 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1143 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1144 | (ov ? PSW_OV : 0));
1145 trace_output (OP_REG_REG);
1146 }
1147
1148 /* cmp reg, reg */
1149 void
1150 OP_1E0 ()
1151 {
1152 unsigned int op0, op1, result, z, s, cy, ov;
1153
1154 trace_input ("cmp", OP_REG_REG_CMP, 0);
1155 /* Compute the result. */
1156 op0 = State.regs[OP[0]];
1157 op1 = State.regs[OP[1]];
1158 result = op1 - op0;
1159
1160 /* Compute the condition codes. */
1161 z = (result == 0);
1162 s = (result & 0x80000000);
1163 cy = (op1 < op0);
1164 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1165 && (op1 & 0x80000000) != (result & 0x80000000));
1166
1167 /* Set condition codes. */
1168 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1169 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1170 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1171 trace_output (OP_REG_REG_CMP);
1172 }
1173
1174 /* cmp sign_extend(imm5), reg */
1175 void
1176 OP_260 ()
1177 {
1178 unsigned int op0, op1, result, z, s, cy, ov;
1179 int temp;
1180
1181 /* Compute the result. */
1182 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1183 temp = SEXT5 (OP[0]);
1184 op0 = temp;
1185 op1 = State.regs[OP[1]];
1186 result = op1 - op0;
1187
1188 /* Compute the condition codes. */
1189 z = (result == 0);
1190 s = (result & 0x80000000);
1191 cy = (op1 < op0);
1192 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1193 && (op1 & 0x80000000) != (result & 0x80000000));
1194
1195 /* Set condition codes. */
1196 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1197 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1198 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1199 trace_output (OP_IMM_REG_CMP);
1200 }
1201
1202 /* setf cccc,reg2 */
1203 void
1204 OP_7E0 ()
1205 {
1206 /* Hack alert. We turn off a bit in op0 since we really only
1207 wanted 4 bits. */
1208 unsigned int op0, psw, result = 0;
1209
1210 trace_input ("setf", OP_EX1, 0);
1211 op0 = OP[0] & 0xf;
1212 psw = PSW;
1213
1214 switch (op0)
1215 {
1216 case 0x0:
1217 result = ((psw & PSW_OV) != 0);
1218 break;
1219 case 0x1:
1220 result = ((psw & PSW_CY) != 0);
1221 break;
1222 case 0x2:
1223 result = ((psw & PSW_Z) != 0);
1224 break;
1225 case 0x3:
1226 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
1227 break;
1228 case 0x4:
1229 result = ((psw & PSW_S) != 0);
1230 break;
1231 case 0x5:
1232 result = 1;
1233 break;
1234 case 0x6:
1235 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
1236 break;
1237 case 0x7:
1238 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
1239 || ((psw & PSW_Z) != 0)) != 0);
1240 break;
1241 case 0x8:
1242 result = ((psw & PSW_OV) == 0);
1243 break;
1244 case 0x9:
1245 result = ((psw & PSW_CY) == 0);
1246 break;
1247 case 0xa:
1248 result = ((psw & PSW_Z) == 0);
1249 break;
1250 case 0xb:
1251 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
1252 break;
1253 case 0xc:
1254 result = ((psw & PSW_S) == 0);
1255 break;
1256 case 0xd:
1257 result = ((psw & PSW_SAT) != 0);
1258 break;
1259 case 0xe:
1260 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
1261 break;
1262 case 0xf:
1263 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
1264 || ((psw & PSW_Z) != 0)) == 0);
1265 break;
1266 }
1267
1268 State.regs[OP[1]] = result;
1269 trace_output (OP_EX1);
1270 }
1271
1272 /* satadd reg,reg */
1273 void
1274 OP_C0 ()
1275 {
1276 unsigned int op0, op1, result, z, s, cy, ov, sat;
1277
1278 trace_input ("satadd", OP_REG_REG, 0);
1279 /* Compute the result. */
1280 op0 = State.regs[OP[0]];
1281 op1 = State.regs[OP[1]];
1282 result = op0 + op1;
1283
1284 /* Compute the condition codes. */
1285 z = (result == 0);
1286 s = (result & 0x80000000);
1287 cy = (result < op0 || result < op1);
1288 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1289 && (op0 & 0x80000000) != (result & 0x80000000));
1290 sat = ov;
1291
1292 /* Store the result and condition codes. */
1293 State.regs[OP[1]] = result;
1294 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1295 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1296 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1297 | (sat ? PSW_SAT : 0));
1298
1299 /* Handle saturated results. */
1300 if (sat && s)
1301 State.regs[OP[1]] = 0x80000000;
1302 else if (sat)
1303 State.regs[OP[1]] = 0x7fffffff;
1304 trace_output (OP_REG_REG);
1305 }
1306
1307 /* satadd sign_extend(imm5), reg */
1308 void
1309 OP_220 ()
1310 {
1311 unsigned int op0, op1, result, z, s, cy, ov, sat;
1312
1313 int temp;
1314
1315 trace_input ("satadd", OP_IMM_REG, 0);
1316
1317 /* Compute the result. */
1318 temp = SEXT5 (OP[0]);
1319 op0 = temp;
1320 op1 = State.regs[OP[1]];
1321 result = op0 + op1;
1322
1323 /* Compute the condition codes. */
1324 z = (result == 0);
1325 s = (result & 0x80000000);
1326 cy = (result < op0 || result < op1);
1327 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1328 && (op0 & 0x80000000) != (result & 0x80000000));
1329 sat = ov;
1330
1331 /* Store the result and condition codes. */
1332 State.regs[OP[1]] = result;
1333 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1334 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1335 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1336 | (sat ? PSW_SAT : 0));
1337
1338 /* Handle saturated results. */
1339 if (sat && s)
1340 State.regs[OP[1]] = 0x80000000;
1341 else if (sat)
1342 State.regs[OP[1]] = 0x7fffffff;
1343 trace_output (OP_IMM_REG);
1344 }
1345
1346 /* satsub reg1, reg2 */
1347 void
1348 OP_A0 ()
1349 {
1350 unsigned int op0, op1, result, z, s, cy, ov, sat;
1351
1352 trace_input ("satsub", OP_REG_REG, 0);
1353
1354 /* Compute the result. */
1355 op0 = State.regs[OP[0]];
1356 op1 = State.regs[OP[1]];
1357 result = op1 - op0;
1358
1359 /* Compute the condition codes. */
1360 z = (result == 0);
1361 s = (result & 0x80000000);
1362 cy = (op1 < op0);
1363 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1364 && (op1 & 0x80000000) != (result & 0x80000000));
1365 sat = ov;
1366
1367 /* Store the result and condition codes. */
1368 State.regs[OP[1]] = result;
1369 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1370 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1371 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1372 | (sat ? PSW_SAT : 0));
1373
1374 /* Handle saturated results. */
1375 if (sat && s)
1376 State.regs[OP[1]] = 0x80000000;
1377 else if (sat)
1378 State.regs[OP[1]] = 0x7fffffff;
1379 trace_output (OP_REG_REG);
1380 }
1381
1382 /* satsubi sign_extend(imm16), reg */
1383 void
1384 OP_660 ()
1385 {
1386 unsigned int op0, op1, result, z, s, cy, ov, sat;
1387 int temp;
1388
1389 trace_input ("satsubi", OP_IMM_REG, 0);
1390
1391 /* Compute the result. */
1392 temp = SEXT16 (OP[0]);
1393 op0 = temp;
1394 op1 = State.regs[OP[1]];
1395 result = op1 - op0;
1396
1397 /* Compute the condition codes. */
1398 z = (result == 0);
1399 s = (result & 0x80000000);
1400 cy = (op1 < op0);
1401 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1402 && (op1 & 0x80000000) != (result & 0x80000000));
1403 sat = ov;
1404
1405 /* Store the result and condition codes. */
1406 State.regs[OP[1]] = result;
1407 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1408 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1409 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1410 | (sat ? PSW_SAT : 0));
1411
1412 /* Handle saturated results. */
1413 if (sat && s)
1414 State.regs[OP[1]] = 0x80000000;
1415 else if (sat)
1416 State.regs[OP[1]] = 0x7fffffff;
1417 trace_output (OP_IMM_REG);
1418 }
1419
1420 /* satsubr reg,reg */
1421 void
1422 OP_80 ()
1423 {
1424 unsigned int op0, op1, result, z, s, cy, ov, sat;
1425
1426 trace_input ("satsubr", OP_REG_REG, 0);
1427
1428 /* Compute the result. */
1429 op0 = State.regs[OP[0]];
1430 op1 = State.regs[OP[1]];
1431 result = op0 - op1;
1432
1433 /* Compute the condition codes. */
1434 z = (result == 0);
1435 s = (result & 0x80000000);
1436 cy = (result < op0);
1437 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1438 && (op1 & 0x80000000) != (result & 0x80000000));
1439 sat = ov;
1440
1441 /* Store the result and condition codes. */
1442 State.regs[OP[1]] = result;
1443 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1444 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1445 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1446 | (sat ? PSW_SAT : 0));
1447
1448 /* Handle saturated results. */
1449 if (sat && s)
1450 State.regs[OP[1]] = 0x80000000;
1451 else if (sat)
1452 State.regs[OP[1]] = 0x7fffffff;
1453 trace_output (OP_REG_REG);
1454 }
1455
1456 /* tst reg,reg */
1457 void
1458 OP_160 ()
1459 {
1460 unsigned int op0, op1, result, z, s;
1461
1462 trace_input ("tst", OP_REG_REG_CMP, 0);
1463
1464 /* Compute the result. */
1465 op0 = State.regs[OP[0]];
1466 op1 = State.regs[OP[1]];
1467 result = op0 & op1;
1468
1469 /* Compute the condition codes. */
1470 z = (result == 0);
1471 s = (result & 0x80000000);
1472
1473 /* Store the condition codes. */
1474 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1475 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1476 trace_output (OP_REG_REG_CMP);
1477 }
1478
1479 /* mov reg, reg */
1480 void
1481 OP_0 ()
1482 {
1483 trace_input ("mov", OP_REG_REG_MOVE, 0);
1484 State.regs[OP[1]] = State.regs[OP[0]];
1485 trace_output (OP_REG_REG_MOVE);
1486 }
1487
1488 /* mov sign_extend(imm5), reg */
1489 void
1490 OP_200 ()
1491 {
1492 int value = SEXT5 (OP[0]);
1493
1494 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1495 State.regs[OP[1]] = value;
1496 trace_output (OP_IMM_REG_MOVE);
1497 }
1498
1499 /* movea sign_extend(imm16), reg, reg */
1500
1501 void
1502 OP_620 ()
1503 {
1504 int value = SEXT16 (OP[0]);
1505
1506 trace_input ("movea", OP_IMM_REG_REG, 0);
1507 State.regs[OP[2]] = State.regs[OP[1]] + value;
1508 trace_output (OP_IMM_REG_REG);
1509 }
1510
1511 /* movhi imm16, reg, reg */
1512 void
1513 OP_640 ()
1514 {
1515 uint32 value = (OP[0] & 0xffff) << 16;
1516
1517 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1518 State.regs[OP[2]] = State.regs[OP[1]] + value;
1519 trace_output (OP_UIMM_REG_REG);
1520 }
1521
1522 /* sar zero_extend(imm5),reg1 */
1523 void
1524 OP_2A0 ()
1525 {
1526 unsigned int op0, op1, result, z, s, cy;
1527
1528 trace_input ("sar", OP_IMM_REG, 0);
1529 op0 = OP[0] & 0x1f;
1530 op1 = State.regs[OP[1]];
1531 result = (signed)op1 >> op0;
1532
1533 /* Compute the condition codes. */
1534 z = (result == 0);
1535 s = (result & 0x80000000);
1536 cy = (op1 & (1 << (op0 - 1)));
1537
1538 /* Store the result and condition codes. */
1539 State.regs[OP[1]] = result;
1540 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1541 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1542 | (cy ? PSW_CY : 0));
1543 trace_output (OP_IMM_REG);
1544 }
1545
1546 /* sar reg1, reg2 */
1547 void
1548 OP_A007E0 ()
1549 {
1550 unsigned int op0, op1, result, z, s, cy;
1551
1552 trace_input ("sar", OP_REG_REG, 0);
1553 op0 = State.regs[OP[0]] & 0x1f;
1554 op1 = State.regs[OP[1]];
1555 result = (signed)op1 >> op0;
1556
1557 /* Compute the condition codes. */
1558 z = (result == 0);
1559 s = (result & 0x80000000);
1560 cy = (op1 & (1 << (op0 - 1)));
1561
1562 /* Store the result and condition codes. */
1563 State.regs[OP[1]] = result;
1564 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1565 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1566 | (cy ? PSW_CY : 0));
1567 trace_output (OP_REG_REG);
1568 }
1569
1570 /* shl zero_extend(imm5),reg1 */
1571 void
1572 OP_2C0 ()
1573 {
1574 unsigned int op0, op1, result, z, s, cy;
1575
1576 trace_input ("shl", OP_IMM_REG, 0);
1577 op0 = OP[0] & 0x1f;
1578 op1 = State.regs[OP[1]];
1579 result = op1 << op0;
1580
1581 /* Compute the condition codes. */
1582 z = (result == 0);
1583 s = (result & 0x80000000);
1584 cy = (op1 & (1 << (32 - op0)));
1585
1586 /* Store the result and condition codes. */
1587 State.regs[OP[1]] = result;
1588 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1589 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1590 | (cy ? PSW_CY : 0));
1591 trace_output (OP_IMM_REG);
1592 }
1593
1594 /* shl reg1, reg2 */
1595 void
1596 OP_C007E0 ()
1597 {
1598 unsigned int op0, op1, result, z, s, cy;
1599
1600 trace_input ("shl", OP_REG_REG, 0);
1601 op0 = State.regs[OP[0]] & 0x1f;
1602 op1 = State.regs[OP[1]];
1603 result = op1 << op0;
1604
1605 /* Compute the condition codes. */
1606 z = (result == 0);
1607 s = (result & 0x80000000);
1608 cy = (op1 & (1 << (32 - op0)));
1609
1610 /* Store the result and condition codes. */
1611 State.regs[OP[1]] = result;
1612 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1613 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1614 | (cy ? PSW_CY : 0));
1615 trace_output (OP_REG_REG);
1616 }
1617
1618 /* shr zero_extend(imm5),reg1 */
1619 void
1620 OP_280 ()
1621 {
1622 unsigned int op0, op1, result, z, s, cy;
1623
1624 trace_input ("shr", OP_IMM_REG, 0);
1625 op0 = OP[0] & 0x1f;
1626 op1 = State.regs[OP[1]];
1627 result = op1 >> op0;
1628
1629 /* Compute the condition codes. */
1630 z = (result == 0);
1631 s = (result & 0x80000000);
1632 cy = (op1 & (1 << (op0 - 1)));
1633
1634 /* Store the result and condition codes. */
1635 State.regs[OP[1]] = result;
1636 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1637 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1638 | (cy ? PSW_CY : 0));
1639 trace_output (OP_IMM_REG);
1640 }
1641
1642 /* shr reg1, reg2 */
1643 void
1644 OP_8007E0 ()
1645 {
1646 unsigned int op0, op1, result, z, s, cy;
1647
1648 trace_input ("shr", OP_REG_REG, 0);
1649 op0 = State.regs[OP[0]] & 0x1f;
1650 op1 = State.regs[OP[1]];
1651 result = op1 >> op0;
1652
1653 /* Compute the condition codes. */
1654 z = (result == 0);
1655 s = (result & 0x80000000);
1656 cy = (op1 & (1 << (op0 - 1)));
1657
1658 /* Store the result and condition codes. */
1659 State.regs[OP[1]] = result;
1660 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1661 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1662 | (cy ? PSW_CY : 0));
1663 trace_output (OP_REG_REG);
1664 }
1665
1666 /* or reg, reg */
1667 void
1668 OP_100 ()
1669 {
1670 unsigned int op0, op1, result, z, s;
1671
1672 trace_input ("or", OP_REG_REG, 0);
1673
1674 /* Compute the result. */
1675 op0 = State.regs[OP[0]];
1676 op1 = State.regs[OP[1]];
1677 result = op0 | op1;
1678
1679 /* Compute the condition codes. */
1680 z = (result == 0);
1681 s = (result & 0x80000000);
1682
1683 /* Store the result and condition codes. */
1684 State.regs[OP[1]] = result;
1685 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1686 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1687 trace_output (OP_REG_REG);
1688 }
1689
1690 /* ori zero_extend(imm16), reg, reg */
1691 void
1692 OP_680 ()
1693 {
1694 unsigned int op0, op1, result, z, s;
1695
1696 trace_input ("ori", OP_UIMM_REG_REG, 0);
1697 op0 = OP[0] & 0xffff;
1698 op1 = State.regs[OP[1]];
1699 result = op0 | op1;
1700
1701 /* Compute the condition codes. */
1702 z = (result == 0);
1703 s = (result & 0x80000000);
1704
1705 /* Store the result and condition codes. */
1706 State.regs[OP[2]] = result;
1707 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1708 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1709 trace_output (OP_UIMM_REG_REG);
1710 }
1711
1712 /* and reg, reg */
1713 void
1714 OP_140 ()
1715 {
1716 unsigned int op0, op1, result, z, s;
1717
1718 trace_input ("and", OP_REG_REG, 0);
1719
1720 /* Compute the result. */
1721 op0 = State.regs[OP[0]];
1722 op1 = State.regs[OP[1]];
1723 result = op0 & op1;
1724
1725 /* Compute the condition codes. */
1726 z = (result == 0);
1727 s = (result & 0x80000000);
1728
1729 /* Store the result and condition codes. */
1730 State.regs[OP[1]] = result;
1731 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1732 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1733 trace_output (OP_REG_REG);
1734 }
1735
1736 /* andi zero_extend(imm16), reg, reg */
1737 void
1738 OP_6C0 ()
1739 {
1740 unsigned int op0, op1, result, z;
1741
1742 trace_input ("andi", OP_UIMM_REG_REG, 0);
1743 op0 = OP[0] & 0xffff;
1744 op1 = State.regs[OP[1]];
1745 result = op0 & op1;
1746
1747 /* Compute the condition codes. */
1748 z = (result == 0);
1749
1750 /* Store the result and condition codes. */
1751 State.regs[OP[2]] = result;
1752 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1753 PSW |= (z ? PSW_Z : 0);
1754 trace_output (OP_UIMM_REG_REG);
1755 }
1756
1757 /* xor reg, reg */
1758 void
1759 OP_120 ()
1760 {
1761 unsigned int op0, op1, result, z, s;
1762
1763 trace_input ("xor", OP_REG_REG, 0);
1764
1765 /* Compute the result. */
1766 op0 = State.regs[OP[0]];
1767 op1 = State.regs[OP[1]];
1768 result = op0 ^ op1;
1769
1770 /* Compute the condition codes. */
1771 z = (result == 0);
1772 s = (result & 0x80000000);
1773
1774 /* Store the result and condition codes. */
1775 State.regs[OP[1]] = result;
1776 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1777 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1778 trace_output (OP_REG_REG);
1779 }
1780
1781 /* xori zero_extend(imm16), reg, reg */
1782 void
1783 OP_6A0 ()
1784 {
1785 unsigned int op0, op1, result, z, s;
1786
1787 trace_input ("xori", OP_UIMM_REG_REG, 0);
1788 op0 = OP[0] & 0xffff;
1789 op1 = State.regs[OP[1]];
1790 result = op0 ^ op1;
1791
1792 /* Compute the condition codes. */
1793 z = (result == 0);
1794 s = (result & 0x80000000);
1795
1796 /* Store the result and condition codes. */
1797 State.regs[OP[2]] = result;
1798 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1799 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1800 trace_output (OP_UIMM_REG_REG);
1801 }
1802
1803 /* not reg1, reg2 */
1804 void
1805 OP_20 ()
1806 {
1807 unsigned int op0, result, z, s;
1808
1809 trace_input ("not", OP_REG_REG_MOVE, 0);
1810 /* Compute the result. */
1811 op0 = State.regs[OP[0]];
1812 result = ~op0;
1813
1814 /* Compute the condition codes. */
1815 z = (result == 0);
1816 s = (result & 0x80000000);
1817
1818 /* Store the result and condition codes. */
1819 State.regs[OP[1]] = result;
1820 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1821 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1822 trace_output (OP_REG_REG_MOVE);
1823 }
1824
1825 /* set1 */
1826 void
1827 OP_7C0 ()
1828 {
1829 unsigned int op0, op1, op2;
1830 int temp;
1831
1832 trace_input ("set1", OP_BIT, 0);
1833 op0 = State.regs[OP[0]];
1834 op1 = OP[1] & 0x7;
1835 temp = SEXT16 (OP[2]);
1836 op2 = temp;
1837 temp = load_mem (op0 + op2, 1);
1838 PSW &= ~PSW_Z;
1839 if ((temp & (1 << op1)) == 0)
1840 PSW |= PSW_Z;
1841 temp |= (1 << op1);
1842 store_mem (op0 + op2, 1, temp);
1843 trace_output (OP_BIT);
1844 }
1845
1846 /* not1 */
1847 void
1848 OP_47C0 ()
1849 {
1850 unsigned int op0, op1, op2;
1851 int temp;
1852
1853 trace_input ("not1", OP_BIT, 0);
1854 op0 = State.regs[OP[0]];
1855 op1 = OP[1] & 0x7;
1856 temp = SEXT16 (OP[2]);
1857 op2 = temp;
1858 temp = load_mem (op0 + op2, 1);
1859 PSW &= ~PSW_Z;
1860 if ((temp & (1 << op1)) == 0)
1861 PSW |= PSW_Z;
1862 temp ^= (1 << op1);
1863 store_mem (op0 + op2, 1, temp);
1864 trace_output (OP_BIT);
1865 }
1866
1867 /* clr1 */
1868 void
1869 OP_87C0 ()
1870 {
1871 unsigned int op0, op1, op2;
1872 int temp;
1873
1874 trace_input ("clr1", OP_BIT, 0);
1875 op0 = State.regs[OP[0]];
1876 op1 = OP[1] & 0x7;
1877 temp = SEXT16 (OP[2]);
1878 op2 = temp;
1879 temp = load_mem (op0 + op2, 1);
1880 PSW &= ~PSW_Z;
1881 if ((temp & (1 << op1)) == 0)
1882 PSW |= PSW_Z;
1883 temp &= ~(1 << op1);
1884 store_mem (op0 + op2, 1, temp);
1885 trace_output (OP_BIT);
1886 }
1887
1888 /* tst1 */
1889 void
1890 OP_C7C0 ()
1891 {
1892 unsigned int op0, op1, op2;
1893 int temp;
1894
1895 trace_input ("tst1", OP_BIT, 0);
1896 op0 = State.regs[OP[0]];
1897 op1 = OP[1] & 0x7;
1898 temp = SEXT16 (OP[2]);
1899 op2 = temp;
1900 temp = load_mem (op0 + op2, 1);
1901 PSW &= ~PSW_Z;
1902 if ((temp & (1 << op1)) == 0)
1903 PSW |= PSW_Z;
1904 trace_output (OP_BIT);
1905 }
1906
1907 /* breakpoint */
1908 void
1909 OP_FFFF ()
1910 {
1911 State.exception = SIGTRAP;
1912 PC -= 4;
1913 }
1914
1915 /* di */
1916 void
1917 OP_16007E0 ()
1918 {
1919 trace_input ("di", OP_NONE, 0);
1920 PSW |= PSW_ID;
1921 trace_output (OP_NONE);
1922 }
1923
1924 /* ei */
1925 void
1926 OP_16087E0 ()
1927 {
1928 trace_input ("ei", OP_NONE, 0);
1929 PSW &= ~PSW_ID;
1930 trace_output (OP_NONE);
1931 }
1932
1933 /* halt */
1934 void
1935 OP_12007E0 ()
1936 {
1937 trace_input ("halt", OP_NONE, 0);
1938 /* FIXME this should put processor into a mode where NMI still handled */
1939 State.exception = SIGQUIT;
1940 trace_output (OP_NONE);
1941 }
1942
1943 /* reti */
1944 void
1945 OP_14007E0 ()
1946 {
1947 trace_input ("reti", OP_NONE, 0);
1948 trace_output (OP_NONE);
1949
1950 /* Restore for NMI if only NP on, otherwise is interrupt or exception. */
1951 if ((PSW & (PSW_NP | PSW_EP)) == PSW_NP)
1952 {
1953 PC = FEPC - 4;
1954 PSW = FEPSW;
1955 }
1956 else
1957 {
1958 PC = EIPC - 4;
1959 PSW = EIPSW;
1960 }
1961 }
1962
1963 /* trap */
1964 void
1965 OP_10007E0 ()
1966 {
1967 trace_input ("trap", OP_TRAP, 0);
1968 trace_output (OP_TRAP);
1969
1970 /* Trap 31 is used for simulating OS I/O functions */
1971
1972 if (OP[0] == 31)
1973 {
1974 int save_errno = errno;
1975 errno = 0;
1976
1977 /* Registers passed to trap 0 */
1978
1979 #define FUNC State.regs[6] /* function number, return value */
1980 #define PARM1 State.regs[7] /* optional parm 1 */
1981 #define PARM2 State.regs[8] /* optional parm 2 */
1982 #define PARM3 State.regs[9] /* optional parm 3 */
1983
1984 /* Registers set by trap 0 */
1985
1986 #define RETVAL State.regs[10] /* return value */
1987 #define RETERR State.regs[11] /* return error code */
1988
1989 /* Turn a pointer in a register into a pointer into real memory. */
1990
1991 #define MEMPTR(x) (map (x))
1992
1993 switch (FUNC)
1994 {
1995 #if !defined(__GO32__) && !defined(_WIN32)
1996 case SYS_fork:
1997 RETVAL = fork ();
1998 break;
1999 case SYS_execve:
2000 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2001 (char **)MEMPTR (PARM3));
2002 break;
2003 #ifdef SYS_execv
2004 case SYS_execv:
2005 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2006 break;
2007 #endif
2008 #if 0
2009 case SYS_pipe:
2010 {
2011 reg_t buf;
2012 int host_fd[2];
2013
2014 buf = PARM1;
2015 RETVAL = pipe (host_fd);
2016 SW (buf, host_fd[0]);
2017 buf += sizeof(uint16);
2018 SW (buf, host_fd[1]);
2019 }
2020 break;
2021
2022 case SYS_wait:
2023 {
2024 int status;
2025
2026 RETVAL = wait (&status);
2027 SW (PARM1, status);
2028 }
2029 break;
2030 #endif
2031 #endif
2032
2033 case SYS_read:
2034 RETVAL = v850_callback->read (v850_callback, PARM1, MEMPTR (PARM2),
2035 PARM3);
2036 break;
2037 case SYS_write:
2038 if (PARM1 == 1)
2039 RETVAL = (int)v850_callback->write_stdout (v850_callback,
2040 MEMPTR (PARM2), PARM3);
2041 else
2042 RETVAL = (int)v850_callback->write (v850_callback, PARM1,
2043 MEMPTR (PARM2), PARM3);
2044 break;
2045 case SYS_lseek:
2046 RETVAL = v850_callback->lseek (v850_callback, PARM1, PARM2, PARM3);
2047 break;
2048 case SYS_close:
2049 RETVAL = v850_callback->close (v850_callback, PARM1);
2050 break;
2051 case SYS_open:
2052 RETVAL = v850_callback->open (v850_callback, MEMPTR (PARM1), PARM2);
2053 break;
2054 case SYS_exit:
2055 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
2056 State.exception = PARM1 & 0xffff; /* get signal encoded by kill */
2057 else if (PARM1 == 0xdead)
2058 State.exception = SIGABRT; /* old libraries */
2059 else
2060 State.exception = SIG_V850_EXIT; /* PARM1 has exit status encoded */
2061 break;
2062
2063 #if !defined(__GO32__) && !defined(_WIN32)
2064 case SYS_stat: /* added at hmsi */
2065 /* stat system call */
2066 {
2067 struct stat host_stat;
2068 reg_t buf;
2069
2070 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2071
2072 buf = PARM2;
2073
2074 /* Just wild-assed guesses. */
2075 store_mem (buf, 2, host_stat.st_dev);
2076 store_mem (buf + 2, 2, host_stat.st_ino);
2077 store_mem (buf + 4, 4, host_stat.st_mode);
2078 store_mem (buf + 8, 2, host_stat.st_nlink);
2079 store_mem (buf + 10, 2, host_stat.st_uid);
2080 store_mem (buf + 12, 2, host_stat.st_gid);
2081 store_mem (buf + 14, 2, host_stat.st_rdev);
2082 store_mem (buf + 16, 4, host_stat.st_size);
2083 store_mem (buf + 20, 4, host_stat.st_atime);
2084 store_mem (buf + 28, 4, host_stat.st_mtime);
2085 store_mem (buf + 36, 4, host_stat.st_ctime);
2086 }
2087 break;
2088
2089 case SYS_chown:
2090 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2091 break;
2092 case SYS_chmod:
2093 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2094 break;
2095 #ifdef SYS_time
2096 case SYS_time:
2097 {
2098 time_t now;
2099 RETVAL = time (&now);
2100 store_mem (PARM1, 4, now);
2101 }
2102 break;
2103 #endif
2104 #ifdef SYS_times
2105 case SYS_times:
2106 {
2107 struct tms tms;
2108 RETVAL = times (&tms);
2109 store_mem (PARM1, 4, tms.tms_utime);
2110 store_mem (PARM1 + 4, 4, tms.tms_stime);
2111 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2112 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2113 break;
2114 }
2115 #endif
2116 case SYS_gettimeofday:
2117 {
2118 struct timeval t;
2119 struct timezone tz;
2120 RETVAL = gettimeofday (&t, &tz);
2121 store_mem (PARM1, 4, t.tv_sec);
2122 store_mem (PARM1 + 4, 4, t.tv_usec);
2123 store_mem (PARM2, 4, tz.tz_minuteswest);
2124 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2125 break;
2126 }
2127 #ifdef SYS_utime
2128 case SYS_utime:
2129 /* Cast the second argument to void *, to avoid type mismatch
2130 if a prototype is present. */
2131 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2132 break;
2133 #endif
2134 #endif
2135 default:
2136 abort ();
2137 }
2138 RETERR = errno;
2139 errno = save_errno;
2140 }
2141 else
2142 { /* Trap 0 -> 30 */
2143 EIPC = PC + 4;
2144 EIPSW = PSW;
2145 /* Mask out EICC */
2146 ECR &= 0xffff0000;
2147 ECR |= 0x40 + OP[0];
2148 /* Flag that we are now doing exception processing. */
2149 PSW |= PSW_EP | PSW_ID;
2150 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
2151 }
2152 }
2153
2154 /* ldsr, reg,reg */
2155 void
2156 OP_2007E0 ()
2157 {
2158 unsigned int op0;
2159
2160 trace_input ("ldsr", OP_LDSR, 0);
2161 op0 = State.regs[OP[0]];
2162 State.sregs[OP[1]] = op0;
2163 trace_output (OP_LDSR);
2164 }
2165
2166 /* stsr */
2167 void
2168 OP_4007E0 ()
2169 {
2170 unsigned int op0;
2171
2172 trace_input ("stsr", OP_STSR, 0);
2173 op0 = State.sregs[OP[1]];
2174 State.regs[OP[0]] = op0;
2175 trace_output (OP_STSR);
2176 }