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Add real SIM_DESC arg to v850 simulator.
[binutils-gdb.git] / sim / v850 / simops.c
1 #include <signal.h>
2 #include "sim-main.h"
3 #include "v850_sim.h"
4 #include "simops.h"
5
6 #ifdef HAVE_UTIME_H
7 #include <utime.h>
8 #endif
9
10 /* FIXME - should be including a version of syscall.h that does not
11 pollute the name space */
12 #include "../../libgloss/v850/sys/syscall.h"
13
14 #include "bfd.h"
15 #include <errno.h>
16 #if !defined(__GO32__) && !defined(_WIN32)
17 #include <sys/stat.h>
18 #include <sys/times.h>
19 #include <sys/time.h>
20 #endif
21
22 enum op_types
23 {
24 OP_UNKNOWN,
25 OP_NONE,
26 OP_TRAP,
27 OP_REG,
28 OP_REG_REG,
29 OP_REG_REG_CMP,
30 OP_REG_REG_MOVE,
31 OP_IMM_REG,
32 OP_IMM_REG_CMP,
33 OP_IMM_REG_MOVE,
34 OP_COND_BR,
35 OP_LOAD16,
36 OP_STORE16,
37 OP_LOAD32,
38 OP_STORE32,
39 OP_JUMP,
40 OP_IMM_REG_REG,
41 OP_UIMM_REG_REG,
42 OP_BIT,
43 OP_EX1,
44 OP_EX2,
45 OP_LDSR,
46 OP_STSR,
47 /* start-sanitize-v850e */
48 OP_BIT_CHANGE,
49 OP_REG_REG_REG,
50 OP_REG_REG3,
51 /* end-sanitize-v850e */
52 /* start-sanitize-v850eq */
53 OP_IMM_REG_REG_REG,
54 OP_PUSHPOP1,
55 OP_PUSHPOP2,
56 OP_PUSHPOP3,
57 /* end-sanitize-v850eq */
58 };
59
60 /* start-sanitize-v850e */
61 /* This is an array of the bit positions of registers r20 .. r31 in that order in a prepare/dispose instruction. */
62 static int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
63 /* end-sanitize-v850e */
64 /* start-sanitize-v850eq */
65 /* This is an array of the bit positions of registers r16 .. r31 in that order in a push/pop instruction. */
66 static int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
67 /* This is an array of the bit positions of registers r1 .. r15 in that order in a push/pop instruction. */
68 static int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
69 /* end-sanitize-v850eq */
70
71 #ifdef DEBUG
72 static void trace_input PARAMS ((char *name, enum op_types type, int size));
73 static void trace_output PARAMS ((enum op_types result));
74 static int init_text_p = 0;
75 static asection *text;
76 static bfd_vma text_start;
77 static bfd_vma text_end;
78 extern bfd *prog_bfd;
79
80 #ifndef SIZE_INSTRUCTION
81 #define SIZE_INSTRUCTION 6
82 #endif
83
84 #ifndef SIZE_OPERANDS
85 #define SIZE_OPERANDS 16
86 #endif
87
88 #ifndef SIZE_VALUES
89 #define SIZE_VALUES 11
90 #endif
91
92 #ifndef SIZE_LOCATION
93 #define SIZE_LOCATION 40
94 #endif
95
96
97 static void
98 trace_input (name, type, size)
99 char *name;
100 enum op_types type;
101 int size;
102 {
103 char buf[1024];
104 char *p;
105 uint32 values[3];
106 int num_values, i;
107 char *cond;
108 asection *s;
109 const char *filename;
110 const char *functionname;
111 unsigned int linenumber;
112
113 if ((v850_debug & DEBUG_TRACE) == 0)
114 return;
115
116 buf[0] = '\0';
117 if (!init_text_p)
118 {
119 init_text_p = 1;
120 for (s = prog_bfd->sections; s; s = s->next)
121 if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
122 {
123 text = s;
124 text_start = bfd_get_section_vma (prog_bfd, s);
125 text_end = text_start + bfd_section_size (prog_bfd, s);
126 break;
127 }
128 }
129
130 if (text && PC >= text_start && PC < text_end)
131 {
132 filename = (const char *)0;
133 functionname = (const char *)0;
134 linenumber = 0;
135 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
136 &filename, &functionname, &linenumber))
137 {
138 p = buf;
139 if (linenumber)
140 {
141 sprintf (p, "Line %5d ", linenumber);
142 p += strlen (p);
143 }
144
145 if (functionname)
146 {
147 sprintf (p, "Func %s ", functionname);
148 p += strlen (p);
149 }
150 else if (filename)
151 {
152 char *q = (char *) strrchr (filename, '/');
153 sprintf (p, "File %s ", (q) ? q+1 : filename);
154 p += strlen (p);
155 }
156
157 if (*p == ' ')
158 *p = '\0';
159 }
160 }
161
162 (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
163 (unsigned)PC,
164 SIZE_LOCATION, SIZE_LOCATION, buf,
165 SIZE_INSTRUCTION, name);
166
167 switch (type)
168 {
169 default:
170 case OP_UNKNOWN:
171 case OP_NONE:
172 strcpy (buf, "unknown");
173 break;
174
175 case OP_TRAP:
176 sprintf (buf, "%d", OP[0]);
177 break;
178
179 case OP_REG:
180 sprintf (buf, "r%d", OP[0]);
181 break;
182
183 case OP_REG_REG:
184 case OP_REG_REG_CMP:
185 case OP_REG_REG_MOVE:
186 sprintf (buf, "r%d,r%d", OP[0], OP[1]);
187 break;
188
189 case OP_IMM_REG:
190 case OP_IMM_REG_CMP:
191 case OP_IMM_REG_MOVE:
192 sprintf (buf, "%d,r%d", OP[0], OP[1]);
193 break;
194
195 case OP_COND_BR:
196 sprintf (buf, "%d", SEXT9 (OP[0]));
197 break;
198
199 case OP_LOAD16:
200 sprintf (buf, "%d[r30],r%d", OP[1] * size, OP[0]);
201 break;
202
203 case OP_STORE16:
204 sprintf (buf, "r%d,%d[r30]", OP[0], OP[1] * size);
205 break;
206
207 case OP_LOAD32:
208 sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
209 break;
210
211 case OP_STORE32:
212 sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
213 break;
214
215 case OP_JUMP:
216 sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
217 break;
218
219 case OP_IMM_REG_REG:
220 sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
221 break;
222
223 case OP_UIMM_REG_REG:
224 sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
225 break;
226
227 case OP_BIT:
228 sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
229 break;
230
231 case OP_EX1:
232 switch (OP[0] & 0xf)
233 {
234 default: cond = "?"; break;
235 case 0x0: cond = "v"; break;
236 case 0x1: cond = "c"; break;
237 case 0x2: cond = "z"; break;
238 case 0x3: cond = "nh"; break;
239 case 0x4: cond = "s"; break;
240 case 0x5: cond = "t"; break;
241 case 0x6: cond = "lt"; break;
242 case 0x7: cond = "le"; break;
243 case 0x8: cond = "nv"; break;
244 case 0x9: cond = "nc"; break;
245 case 0xa: cond = "nz"; break;
246 case 0xb: cond = "h"; break;
247 case 0xc: cond = "ns"; break;
248 case 0xd: cond = "sa"; break;
249 case 0xe: cond = "ge"; break;
250 case 0xf: cond = "gt"; break;
251 }
252
253 sprintf (buf, "%s,r%d", cond, OP[1]);
254 break;
255
256 case OP_EX2:
257 strcpy (buf, "EX2");
258 break;
259
260 case OP_LDSR:
261 case OP_STSR:
262 sprintf (buf, "r%d,s%d", OP[0], OP[1]);
263 break;
264
265 case OP_PUSHPOP1:
266 for (i = 0; i < 12; i++)
267 if (OP[3] & (1 << type1_regs[i]))
268 strcat (buf, "r%d ", i + 20);
269 break;
270
271 case OP_PUSHPOP2:
272 for (i = 0; i < 16; i++)
273 if (OP[3] & (1 << type2_regs[i]))
274 strcat (buf, "r%d ", i + 16);
275 if (OP[3] & (1 << 19))
276 strcat (buf, "F/EIPC, F/EIPSW " );
277 break;
278
279 case OP_PUSHPOP3:
280 for (i = 0; i < 15; i++)
281 if (OP[3] & (1 << type3_regs[i]))
282 strcat (buf, "r%d ", i + 1);
283 if (OP[3] & (1 << 3))
284 strcat (buf, "PSW " );
285 if (OP[3] & (1 << 19))
286 strcat (buf, "F/EIPC, F/EIPSW " );
287 break;
288
289 case OP_BIT_CHANGE:
290 sprintf (buf, "r%d, [r%d]", OP[1], OP[0] );
291 break;
292 }
293
294 if ((v850_debug & DEBUG_VALUES) == 0)
295 {
296 (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
297 }
298 else
299 {
300 (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
301 switch (type)
302 {
303 default:
304 case OP_UNKNOWN:
305 case OP_NONE:
306 case OP_TRAP:
307 num_values = 0;
308 break;
309
310 case OP_REG:
311 case OP_REG_REG_MOVE:
312 values[0] = State.regs[OP[0]];
313 num_values = 1;
314 break;
315
316 case OP_BIT_CHANGE:
317 case OP_REG_REG:
318 case OP_REG_REG_CMP:
319 values[0] = State.regs[OP[1]];
320 values[1] = State.regs[OP[0]];
321 num_values = 2;
322 break;
323
324 case OP_IMM_REG:
325 case OP_IMM_REG_CMP:
326 values[0] = SEXT5 (OP[0]);
327 values[1] = OP[1];
328 num_values = 2;
329 break;
330
331 case OP_IMM_REG_MOVE:
332 values[0] = SEXT5 (OP[0]);
333 num_values = 1;
334 break;
335
336 case OP_COND_BR:
337 values[0] = State.pc;
338 values[1] = SEXT9 (OP[0]);
339 values[2] = PSW;
340 num_values = 3;
341 break;
342
343 case OP_LOAD16:
344 values[0] = OP[1] * size;
345 values[1] = State.regs[30];
346 num_values = 2;
347 break;
348
349 case OP_STORE16:
350 values[0] = State.regs[OP[0]];
351 values[1] = OP[1] * size;
352 values[2] = State.regs[30];
353 num_values = 3;
354 break;
355
356 case OP_LOAD32:
357 values[0] = SEXT16 (OP[2]);
358 values[1] = State.regs[OP[0]];
359 num_values = 2;
360 break;
361
362 case OP_STORE32:
363 values[0] = State.regs[OP[1]];
364 values[1] = SEXT16 (OP[2]);
365 values[2] = State.regs[OP[0]];
366 num_values = 3;
367 break;
368
369 case OP_JUMP:
370 values[0] = SEXT22 (OP[0]);
371 values[1] = State.pc;
372 num_values = 2;
373 break;
374
375 case OP_IMM_REG_REG:
376 values[0] = SEXT16 (OP[0]) << size;
377 values[1] = State.regs[OP[1]];
378 num_values = 2;
379 break;
380
381 case OP_UIMM_REG_REG:
382 values[0] = (OP[0] & 0xffff) << size;
383 values[1] = State.regs[OP[1]];
384 num_values = 2;
385 break;
386
387 case OP_BIT:
388 num_values = 0;
389 break;
390
391 case OP_EX1:
392 values[0] = PSW;
393 num_values = 1;
394 break;
395
396 case OP_EX2:
397 num_values = 0;
398 break;
399
400 case OP_LDSR:
401 values[0] = State.regs[OP[0]];
402 num_values = 1;
403 break;
404
405 case OP_STSR:
406 values[0] = State.sregs[OP[1]];
407 num_values = 1;
408 }
409
410 for (i = 0; i < num_values; i++)
411 (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
412
413 while (i++ < 3)
414 (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
415 }
416 }
417
418 static void
419 trace_output (result)
420 enum op_types result;
421 {
422 if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
423 {
424 switch (result)
425 {
426 default:
427 case OP_UNKNOWN:
428 case OP_NONE:
429 case OP_TRAP:
430 case OP_REG:
431 case OP_REG_REG_CMP:
432 case OP_IMM_REG_CMP:
433 case OP_COND_BR:
434 case OP_STORE16:
435 case OP_STORE32:
436 case OP_BIT:
437 case OP_EX2:
438 break;
439
440 case OP_LOAD16:
441 case OP_STSR:
442 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
443 (unsigned long)State.regs[OP[0]]);
444 break;
445
446 case OP_REG_REG:
447 case OP_REG_REG_MOVE:
448 case OP_IMM_REG:
449 case OP_IMM_REG_MOVE:
450 case OP_LOAD32:
451 case OP_EX1:
452 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
453 (unsigned long)State.regs[OP[1]]);
454 break;
455
456 case OP_IMM_REG_REG:
457 case OP_UIMM_REG_REG:
458 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
459 (unsigned long)State.regs[OP[2]]);
460 break;
461
462 case OP_JUMP:
463 if (OP[1] != 0)
464 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
465 (unsigned long)State.regs[OP[1]]);
466 break;
467
468 case OP_LDSR:
469 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
470 (unsigned long)State.sregs[OP[1]]);
471 break;
472 }
473
474 (*v850_callback->printf_filtered) (v850_callback, "\n");
475 }
476 }
477
478 #else
479 #define trace_input(NAME, IN1, IN2)
480 #define trace_output(RESULT)
481
482 //#define trace_input(NAME, IN1, IN2) fprintf (stderr, NAME "\n" );
483
484 #endif
485
486 \f
487 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
488 static unsigned int
489 condition_met (unsigned code)
490 {
491 unsigned int psw = PSW;
492
493 switch (code & 0xf)
494 {
495 case 0x0: return ((psw & PSW_OV) != 0);
496 case 0x1: return ((psw & PSW_CY) != 0);
497 case 0x2: return ((psw & PSW_Z) != 0);
498 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
499 case 0x4: return ((psw & PSW_S) != 0);
500 /*case 0x5: return 1;*/
501 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
502 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
503 case 0x8: return ((psw & PSW_OV) == 0);
504 case 0x9: return ((psw & PSW_CY) == 0);
505 case 0xa: return ((psw & PSW_Z) == 0);
506 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
507 case 0xc: return ((psw & PSW_S) == 0);
508 case 0xd: return ((psw & PSW_SAT) != 0);
509 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
510 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
511 }
512
513 return 1;
514 }
515
516 static unsigned long
517 Add32 (unsigned long a1, unsigned long a2, int * carry)
518 {
519 unsigned long result = (a1 + a2);
520
521 * carry = (result < a1);
522
523 return result;
524 }
525
526 static void
527 Multiply64 (boolean sign, unsigned long op0)
528 {
529 unsigned long op1;
530 unsigned long lo;
531 unsigned long mid1;
532 unsigned long mid2;
533 unsigned long hi;
534 unsigned long RdLo;
535 unsigned long RdHi;
536 int carry;
537
538 op1 = State.regs[ OP[1] ];
539
540 if (sign)
541 {
542 /* Compute sign of result and adjust operands if necessary. */
543
544 sign = (op0 ^ op1) & 0x80000000;
545
546 if (((signed long) op0) < 0)
547 op0 = - op0;
548
549 if (((signed long) op1) < 0)
550 op1 = - op1;
551 }
552
553 /* We can split the 32x32 into four 16x16 operations. This ensures
554 that we do not lose precision on 32bit only hosts: */
555 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
556 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
557 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
558 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
559
560 /* We now need to add all of these results together, taking care
561 to propogate the carries from the additions: */
562 RdLo = Add32 (lo, (mid1 << 16), & carry);
563 RdHi = carry;
564 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
565 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
566
567 if (sign)
568 {
569 /* Negate result if necessary. */
570
571 RdLo = ~ RdLo;
572 RdHi = ~ RdHi;
573 if (RdLo == 0xFFFFFFFF)
574 {
575 RdLo = 0;
576 RdHi += 1;
577 }
578 else
579 RdLo += 1;
580 }
581
582 State.regs[ OP[1] ] = RdLo;
583 State.regs[ OP[2] >> 11 ] = RdHi;
584
585 return;
586 }
587
588 \f
589 /* sld.b */
590 int
591 OP_300 ()
592 {
593 unsigned long result;
594
595 result = load_mem (State.regs[30] + (OP[3] & 0x7f), 1);
596
597 /* start-sanitize-v850eq */
598 #ifdef ARCH_v850eq
599 trace_input ("sld.bu", OP_LOAD16, 1);
600
601 State.regs[ OP[1] ] = result;
602 #else
603 /* end-sanitize-v850eq */
604 trace_input ("sld.b", OP_LOAD16, 1);
605
606 State.regs[ OP[1] ] = SEXT8 (result);
607 /* start-sanitize-v850eq */
608 #endif
609 /* end-sanitize-v850eq */
610
611 trace_output (OP_LOAD16);
612
613 return 2;
614 }
615
616 /* sld.h */
617 int
618 OP_400 ()
619 {
620 unsigned long result;
621
622 result = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2);
623
624 /* start-sanitize-v850eq */
625 #ifdef ARCH_v850eq
626 trace_input ("sld.hu", OP_LOAD16, 2);
627
628 State.regs[ OP[1] ] = result;
629 #else
630 /* end-sanitize-v850eq */
631 trace_input ("sld.h", OP_LOAD16, 2);
632
633 State.regs[ OP[1] ] = SEXT16 (result);
634 /* start-sanitize-v850eq */
635 #endif
636 /* end-sanitize-v850eq */
637
638 trace_output (OP_LOAD16);
639
640 return 2;
641 }
642
643 /* sld.w */
644 int
645 OP_500 ()
646 {
647 trace_input ("sld.w", OP_LOAD16, 4);
648
649 State.regs[ OP[1] ] = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 4);
650
651 trace_output (OP_LOAD16);
652
653 return 2;
654 }
655
656 /* sst.b */
657 int
658 OP_380 ()
659 {
660 trace_input ("sst.b", OP_STORE16, 1);
661
662 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
663
664 trace_output (OP_STORE16);
665
666 return 2;
667 }
668
669 /* sst.h */
670 int
671 OP_480 ()
672 {
673 trace_input ("sst.h", OP_STORE16, 2);
674
675 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
676
677 trace_output (OP_STORE16);
678
679 return 2;
680 }
681
682 /* sst.w */
683 int
684 OP_501 ()
685 {
686 trace_input ("sst.w", OP_STORE16, 4);
687
688 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
689
690 trace_output (OP_STORE16);
691
692 return 2;
693 }
694
695 /* ld.b */
696 int
697 OP_700 ()
698 {
699 int adr;
700
701 trace_input ("ld.b", OP_LOAD32, 1);
702
703 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
704
705 State.regs[ OP[1] ] = SEXT8 (load_mem (adr, 1));
706
707 trace_output (OP_LOAD32);
708
709 return 4;
710 }
711
712 /* ld.h */
713 int
714 OP_720 ()
715 {
716 int adr;
717
718 trace_input ("ld.h", OP_LOAD32, 2);
719
720 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
721 adr &= ~0x1;
722
723 State.regs[ OP[1] ] = SEXT16 (load_mem (adr, 2));
724
725 trace_output (OP_LOAD32);
726
727 return 4;
728 }
729
730 /* ld.w */
731 int
732 OP_10720 ()
733 {
734 int adr;
735
736 trace_input ("ld.w", OP_LOAD32, 4);
737
738 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
739 adr &= ~0x3;
740
741 State.regs[ OP[1] ] = load_mem (adr, 4);
742
743 trace_output (OP_LOAD32);
744
745 return 4;
746 }
747
748 /* st.b */
749 int
750 OP_740 ()
751 {
752 trace_input ("st.b", OP_STORE32, 1);
753
754 store_mem (State.regs[ OP[0] ] + SEXT16 (OP[2]), 1, State.regs[ OP[1] ]);
755
756 trace_output (OP_STORE32);
757
758 return 4;
759 }
760
761 /* st.h */
762 int
763 OP_760 ()
764 {
765 int adr;
766
767 trace_input ("st.h", OP_STORE32, 2);
768
769 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
770 adr &= ~1;
771
772 store_mem (adr, 2, State.regs[ OP[1] ]);
773
774 trace_output (OP_STORE32);
775
776 return 4;
777 }
778
779 /* st.w */
780 int
781 OP_10760 ()
782 {
783 int adr;
784
785 trace_input ("st.w", OP_STORE32, 4);
786
787 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
788 adr &= ~3;
789
790 store_mem (adr, 4, State.regs[ OP[1] ]);
791
792 trace_output (OP_STORE32);
793
794 return 4;
795 }
796
797 static int
798 branch (int code)
799 {
800 trace_input ("Bcond", OP_COND_BR, 0);
801 trace_output (OP_COND_BR);
802
803 if (condition_met (code))
804 return SEXT9 (((OP[3] & 0x70) >> 3) | ((OP[3] & 0xf800) >> 7));
805 else
806 return 2;
807 }
808
809 /* bv disp9 */
810 int
811 OP_580 ()
812 {
813 return branch (0);
814 }
815
816 /* bl disp9 */
817 int
818 OP_581 ()
819 {
820 return branch (1);
821 }
822
823 /* be disp9 */
824 int
825 OP_582 ()
826 {
827 return branch (2);
828 }
829
830 /* bnh disp 9*/
831 int
832 OP_583 ()
833 {
834 return branch (3);
835 }
836
837 /* bn disp9 */
838 int
839 OP_584 ()
840 {
841 return branch (4);
842 }
843
844 /* br disp9 */
845 int
846 OP_585 ()
847 {
848 return branch (5);
849 }
850
851 /* blt disp9 */
852 int
853 OP_586 ()
854 {
855 return branch (6);
856 }
857
858 /* ble disp9 */
859 int
860 OP_587 ()
861 {
862 return branch (7);
863 }
864
865 /* bnv disp9 */
866 int
867 OP_588 ()
868 {
869 return branch (8);
870 }
871
872 /* bnl disp9 */
873 int
874 OP_589 ()
875 {
876 return branch (9);
877 }
878
879 /* bne disp9 */
880 int
881 OP_58A ()
882 {
883 return branch (10);
884 }
885
886 /* bh disp9 */
887 int
888 OP_58B ()
889 {
890 return branch (11);
891 }
892
893 /* bp disp9 */
894 int
895 OP_58C ()
896 {
897 return branch (12);
898 }
899
900 /* bsa disp9 */
901 int
902 OP_58D ()
903 {
904 return branch (13);
905 }
906
907 /* bge disp9 */
908 int
909 OP_58E ()
910 {
911 return branch (14);
912 }
913
914 /* bgt disp9 */
915 int
916 OP_58F ()
917 {
918 return branch (15);
919 }
920
921 /* jmp [reg1] */
922 /* sld.bu disp4[ep], reg2 */
923 int
924 OP_60 ()
925 {
926 if (OP[1] == 0)
927 {
928 trace_input ("jmp", OP_REG, 0);
929
930 PC = State.regs[ OP[0] ];
931
932 trace_output (OP_REG);
933
934 return 0; /* Add nothing to the PC, we have already done it. */
935 }
936 /* start-sanitize-v850e */
937 else
938 {
939 unsigned long result;
940
941 result = load_mem (State.regs[30] + (OP[3] & 0xf), 1);
942
943 /* start-sanitize-v850eq */
944 #ifdef ARCH_v850eq
945 trace_input ("sld.b", OP_LOAD16, 1);
946
947 State.regs[ OP[1] ] = SEXT8 (result);
948 #else
949 /* end-sanitize-v850eq */
950 trace_input ("sld.bu", OP_LOAD16, 1);
951
952 State.regs[ OP[1] ] = result;
953 /* start-sanitize-v850eq */
954 #endif
955 /* end-sanitize-v850eq */
956
957 trace_output (OP_LOAD16);
958
959 return 2;
960 }
961 /* end-sanitize-v850e */
962 }
963
964 /* jarl/jr disp22, reg */
965 int
966 OP_780 ()
967 {
968 trace_input ("jarl/jr", OP_JUMP, 0);
969
970 if (OP[ 1 ] != 0)
971 State.regs[ OP[1] ] = PC + 4;
972
973 trace_output (OP_JUMP);
974
975 return SEXT22 (((OP[3] & 0x3f) << 16) | OP[2]);
976 }
977
978 /* add reg, reg */
979 int
980 OP_1C0 ()
981 {
982 unsigned int op0, op1, result, z, s, cy, ov;
983
984 trace_input ("add", OP_REG_REG, 0);
985
986 /* Compute the result. */
987
988 op0 = State.regs[ OP[0] ];
989 op1 = State.regs[ OP[1] ];
990
991 result = op0 + op1;
992
993 /* Compute the condition codes. */
994 z = (result == 0);
995 s = (result & 0x80000000);
996 cy = (result < op0 || result < op1);
997 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
998 && (op0 & 0x80000000) != (result & 0x80000000));
999
1000 /* Store the result and condition codes. */
1001 State.regs[OP[1]] = result;
1002 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1003 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1004 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1005 trace_output (OP_REG_REG);
1006
1007 return 2;
1008 }
1009
1010 /* add sign_extend(imm5), reg */
1011 int
1012 OP_240 ()
1013 {
1014 unsigned int op0, op1, result, z, s, cy, ov;
1015 int temp;
1016
1017 trace_input ("add", OP_IMM_REG, 0);
1018
1019 /* Compute the result. */
1020 temp = SEXT5 (OP[0]);
1021 op0 = temp;
1022 op1 = State.regs[OP[1]];
1023 result = op0 + op1;
1024
1025 /* Compute the condition codes. */
1026 z = (result == 0);
1027 s = (result & 0x80000000);
1028 cy = (result < op0 || result < op1);
1029 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1030 && (op0 & 0x80000000) != (result & 0x80000000));
1031
1032 /* Store the result and condition codes. */
1033 State.regs[OP[1]] = result;
1034 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1035 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1036 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1037 trace_output (OP_IMM_REG);
1038
1039 return 2;
1040 }
1041
1042 /* addi sign_extend(imm16), reg, reg */
1043 int
1044 OP_600 ()
1045 {
1046 unsigned int op0, op1, result, z, s, cy, ov;
1047
1048 trace_input ("addi", OP_IMM_REG_REG, 0);
1049
1050 /* Compute the result. */
1051
1052 op0 = SEXT16 (OP[2]);
1053 op1 = State.regs[ OP[0] ];
1054 result = op0 + op1;
1055
1056 /* Compute the condition codes. */
1057 z = (result == 0);
1058 s = (result & 0x80000000);
1059 cy = (result < op0 || result < op1);
1060 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1061 && (op0 & 0x80000000) != (result & 0x80000000));
1062
1063 /* Store the result and condition codes. */
1064 State.regs[OP[1]] = result;
1065 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1066 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1067 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1068 trace_output (OP_IMM_REG_REG);
1069
1070 return 4;
1071 }
1072
1073 /* sub reg1, reg2 */
1074 int
1075 OP_1A0 ()
1076 {
1077 unsigned int op0, op1, result, z, s, cy, ov;
1078
1079 trace_input ("sub", OP_REG_REG, 0);
1080 /* Compute the result. */
1081 op0 = State.regs[ OP[0] ];
1082 op1 = State.regs[ OP[1] ];
1083 result = op1 - op0;
1084
1085 /* Compute the condition codes. */
1086 z = (result == 0);
1087 s = (result & 0x80000000);
1088 cy = (op1 < op0);
1089 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1090 && (op1 & 0x80000000) != (result & 0x80000000));
1091
1092 /* Store the result and condition codes. */
1093 State.regs[OP[1]] = result;
1094 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1095 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1096 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1097 trace_output (OP_REG_REG);
1098
1099 return 2;
1100 }
1101
1102 /* subr reg1, reg2 */
1103 int
1104 OP_180 ()
1105 {
1106 unsigned int op0, op1, result, z, s, cy, ov;
1107
1108 trace_input ("subr", OP_REG_REG, 0);
1109 /* Compute the result. */
1110 op0 = State.regs[ OP[0] ];
1111 op1 = State.regs[ OP[1] ];
1112 result = op0 - op1;
1113
1114 /* Compute the condition codes. */
1115 z = (result == 0);
1116 s = (result & 0x80000000);
1117 cy = (op0 < op1);
1118 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1119 && (op0 & 0x80000000) != (result & 0x80000000));
1120
1121 /* Store the result and condition codes. */
1122 State.regs[OP[1]] = result;
1123 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1124 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1125 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1126 trace_output (OP_REG_REG);
1127
1128 return 2;
1129 }
1130
1131 /* sxh reg1 */
1132 /* mulh reg1, reg2 */
1133 int
1134 OP_E0 ()
1135 {
1136 /* start-sanitize-v850e */
1137 if (OP[1] == 0)
1138 {
1139 trace_input ("sxh", OP_REG, 0);
1140
1141 State.regs[ OP[0] ] = SEXT16 (State.regs[ OP[0] ]);
1142
1143 trace_output (OP_REG);
1144 }
1145 else
1146 /* end-sanitize-v850e */
1147 {
1148 trace_input ("mulh", OP_REG_REG, 0);
1149
1150 State.regs[ OP[1] ] = (SEXT16 (State.regs[ OP[1] ]) * SEXT16 (State.regs[ OP[0] ]));
1151
1152 trace_output (OP_REG_REG);
1153 }
1154
1155 return 2;
1156 }
1157
1158 /* mulh sign_extend(imm5), reg2 */
1159 int
1160 OP_2E0 ()
1161 {
1162 trace_input ("mulh", OP_IMM_REG, 0);
1163
1164 State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
1165
1166 trace_output (OP_IMM_REG);
1167
1168 return 2;
1169 }
1170
1171 /* mulhi imm16, reg1, reg2 */
1172 int
1173 OP_6E0 ()
1174 {
1175 if (OP[1] == 0)
1176 {
1177 }
1178 else
1179 {
1180 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1181
1182 State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[0] ]) * SEXT16 (OP[2]);
1183
1184 trace_output (OP_IMM_REG_REG);
1185 }
1186
1187 return 4;
1188 }
1189
1190 /* divh reg1, reg2 */
1191 /* switch reg1 */
1192 int
1193 OP_40 ()
1194 {
1195 /* start-sanitize-v850e */
1196 if (OP[1] == 0)
1197 {
1198 unsigned long adr;
1199
1200 trace_input ("switch", OP_REG, 0);
1201
1202 adr = State.pc + 2 + (State.regs[ OP[0] ] << 1);
1203 State.pc = State.pc + 2 + (SEXT16 (load_mem (adr, 2)) << 1);
1204
1205 trace_output (OP_REG);
1206 }
1207 else
1208 /* end-sanitize-v850e */
1209 {
1210 unsigned int op0, op1, result, ov, s, z;
1211 int temp;
1212
1213 trace_input ("divh", OP_REG_REG, 0);
1214
1215 /* Compute the result. */
1216 temp = SEXT16 (State.regs[ OP[0] ]);
1217 op0 = temp;
1218 op1 = State.regs[OP[1]];
1219
1220 if (op0 == 0xffffffff && op1 == 0x80000000)
1221 {
1222 result = 0x80000000;
1223 ov = 1;
1224 }
1225 else if (op0 != 0)
1226 {
1227 result = op1 / op0;
1228 ov = 0;
1229 }
1230 else
1231 {
1232 result = 0x0;
1233 ov = 1;
1234 }
1235
1236 /* Compute the condition codes. */
1237 z = (result == 0);
1238 s = (result & 0x80000000);
1239
1240 /* Store the result and condition codes. */
1241 State.regs[OP[1]] = result;
1242 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1243 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1244 | (ov ? PSW_OV : 0));
1245 trace_output (OP_REG_REG);
1246 }
1247
1248 return 2;
1249 }
1250
1251 /* cmp reg, reg */
1252 int
1253 OP_1E0 ()
1254 {
1255 unsigned int op0, op1, result, z, s, cy, ov;
1256
1257 trace_input ("cmp", OP_REG_REG_CMP, 0);
1258 /* Compute the result. */
1259 op0 = State.regs[ OP[0] ];
1260 op1 = State.regs[ OP[1] ];
1261 result = op1 - op0;
1262
1263 /* Compute the condition codes. */
1264 z = (result == 0);
1265 s = (result & 0x80000000);
1266 cy = (op1 < op0);
1267 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1268 && (op1 & 0x80000000) != (result & 0x80000000));
1269
1270 /* Set condition codes. */
1271 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1272 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1273 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1274 trace_output (OP_REG_REG_CMP);
1275
1276 return 2;
1277 }
1278
1279 /* cmp sign_extend(imm5), reg */
1280 int
1281 OP_260 ()
1282 {
1283 unsigned int op0, op1, result, z, s, cy, ov;
1284 int temp;
1285
1286 /* Compute the result. */
1287 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1288 temp = SEXT5 (OP[0]);
1289 op0 = temp;
1290 op1 = State.regs[OP[1]];
1291 result = op1 - op0;
1292
1293 /* Compute the condition codes. */
1294 z = (result == 0);
1295 s = (result & 0x80000000);
1296 cy = (op1 < op0);
1297 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1298 && (op1 & 0x80000000) != (result & 0x80000000));
1299
1300 /* Set condition codes. */
1301 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1302 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1303 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1304 trace_output (OP_IMM_REG_CMP);
1305
1306 return 2;
1307 }
1308
1309 /* setf cccc,reg2 */
1310 int
1311 OP_7E0 ()
1312 {
1313 trace_input ("setf", OP_EX1, 0);
1314
1315 State.regs[ OP[1] ] = condition_met (OP[0]);
1316
1317 trace_output (OP_EX1);
1318
1319 return 4;
1320 }
1321
1322 /* zxh reg1 */
1323 /* satadd reg,reg */
1324 int
1325 OP_C0 ()
1326 {
1327 /* start-sanitize-v850e */
1328 if (OP[1] == 0)
1329 {
1330 trace_input ("zxh", OP_REG, 0);
1331
1332 State.regs[ OP[0] ] &= 0xffff;
1333
1334 trace_output (OP_REG);
1335 }
1336 else
1337 /* end-sanitize-v850e */
1338 {
1339 unsigned int op0, op1, result, z, s, cy, ov, sat;
1340
1341 trace_input ("satadd", OP_REG_REG, 0);
1342 /* Compute the result. */
1343 op0 = State.regs[ OP[0] ];
1344 op1 = State.regs[ OP[1] ];
1345 result = op0 + op1;
1346
1347 /* Compute the condition codes. */
1348 z = (result == 0);
1349 s = (result & 0x80000000);
1350 cy = (result < op0 || result < op1);
1351 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1352 && (op0 & 0x80000000) != (result & 0x80000000));
1353 sat = ov;
1354
1355 /* Store the result and condition codes. */
1356 State.regs[OP[1]] = result;
1357 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1358 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1359 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1360 | (sat ? PSW_SAT : 0));
1361
1362 /* Handle saturated results. */
1363 if (sat && s)
1364 State.regs[OP[1]] = 0x80000000;
1365 else if (sat)
1366 State.regs[OP[1]] = 0x7fffffff;
1367 trace_output (OP_REG_REG);
1368 }
1369
1370 return 2;
1371 }
1372
1373 /* satadd sign_extend(imm5), reg */
1374 int
1375 OP_220 ()
1376 {
1377 unsigned int op0, op1, result, z, s, cy, ov, sat;
1378
1379 int temp;
1380
1381 trace_input ("satadd", OP_IMM_REG, 0);
1382
1383 /* Compute the result. */
1384 temp = SEXT5 (OP[0]);
1385 op0 = temp;
1386 op1 = State.regs[OP[1]];
1387 result = op0 + op1;
1388
1389 /* Compute the condition codes. */
1390 z = (result == 0);
1391 s = (result & 0x80000000);
1392 cy = (result < op0 || result < op1);
1393 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1394 && (op0 & 0x80000000) != (result & 0x80000000));
1395 sat = ov;
1396
1397 /* Store the result and condition codes. */
1398 State.regs[OP[1]] = result;
1399 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1400 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1401 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1402 | (sat ? PSW_SAT : 0));
1403
1404 /* Handle saturated results. */
1405 if (sat && s)
1406 State.regs[OP[1]] = 0x80000000;
1407 else if (sat)
1408 State.regs[OP[1]] = 0x7fffffff;
1409 trace_output (OP_IMM_REG);
1410
1411 return 2;
1412 }
1413
1414 /* satsub reg1, reg2 */
1415 /* sxb reg1 */
1416 int
1417 OP_A0 ()
1418 {
1419 /* start-sanitize-v850e */
1420 if (OP[1] == 0)
1421 {
1422 trace_input ("sxb", OP_REG, 0);
1423
1424 State.regs[ OP[0] ] = SEXT8 (State.regs[ OP[0] ]);
1425
1426 trace_output (OP_REG);
1427 }
1428 else
1429 /* end-sanitize-v850e */
1430 {
1431 unsigned int op0, op1, result, z, s, cy, ov, sat;
1432
1433 trace_input ("satsub", OP_REG_REG, 0);
1434
1435 /* Compute the result. */
1436 op0 = State.regs[ OP[0] ];
1437 op1 = State.regs[ OP[1] ];
1438 result = op1 - op0;
1439
1440 /* Compute the condition codes. */
1441 z = (result == 0);
1442 s = (result & 0x80000000);
1443 cy = (op1 < op0);
1444 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1445 && (op1 & 0x80000000) != (result & 0x80000000));
1446 sat = ov;
1447
1448 /* Store the result and condition codes. */
1449 State.regs[OP[1]] = result;
1450 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1451 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1452 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1453 | (sat ? PSW_SAT : 0));
1454
1455 /* Handle saturated results. */
1456 if (sat && s)
1457 State.regs[OP[1]] = 0x80000000;
1458 else if (sat)
1459 State.regs[OP[1]] = 0x7fffffff;
1460 trace_output (OP_REG_REG);
1461 }
1462
1463 return 2;
1464 }
1465
1466 /* satsubi sign_extend(imm16), reg */
1467 int
1468 OP_660 ()
1469 {
1470 unsigned int op0, op1, result, z, s, cy, ov, sat;
1471 int temp;
1472
1473 trace_input ("satsubi", OP_IMM_REG, 0);
1474
1475 /* Compute the result. */
1476 temp = SEXT16 (OP[2]);
1477 op0 = temp;
1478 op1 = State.regs[ OP[0] ];
1479 result = op1 - op0;
1480
1481 /* Compute the condition codes. */
1482 z = (result == 0);
1483 s = (result & 0x80000000);
1484 cy = (op1 < op0);
1485 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1486 && (op1 & 0x80000000) != (result & 0x80000000));
1487 sat = ov;
1488
1489 /* Store the result and condition codes. */
1490 State.regs[OP[1]] = result;
1491 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1492 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1493 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1494 | (sat ? PSW_SAT : 0));
1495
1496 /* Handle saturated results. */
1497 if (sat && s)
1498 State.regs[OP[1]] = 0x80000000;
1499 else if (sat)
1500 State.regs[OP[1]] = 0x7fffffff;
1501 trace_output (OP_IMM_REG);
1502
1503 return 4;
1504 }
1505
1506 /* satsubr reg,reg */
1507 /* zxb reg1 */
1508 int
1509 OP_80 ()
1510 {
1511 /* start-sanitize-v850e */
1512 if (OP[1] == 0)
1513 {
1514 trace_input ("zxb", OP_REG, 0);
1515
1516 State.regs[ OP[0] ] &= 0xff;
1517
1518 trace_output (OP_REG);
1519 }
1520 else
1521 /* end-sanitize-v850e */
1522 {
1523 unsigned int op0, op1, result, z, s, cy, ov, sat;
1524
1525 trace_input ("satsubr", OP_REG_REG, 0);
1526
1527 /* Compute the result. */
1528 op0 = State.regs[ OP[0] ];
1529 op1 = State.regs[ OP[1] ];
1530 result = op0 - op1;
1531
1532 /* Compute the condition codes. */
1533 z = (result == 0);
1534 s = (result & 0x80000000);
1535 cy = (result < op0);
1536 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1537 && (op1 & 0x80000000) != (result & 0x80000000));
1538 sat = ov;
1539
1540 /* Store the result and condition codes. */
1541 State.regs[OP[1]] = result;
1542 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1543 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1544 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1545 | (sat ? PSW_SAT : 0));
1546
1547 /* Handle saturated results. */
1548 if (sat && s)
1549 State.regs[OP[1]] = 0x80000000;
1550 else if (sat)
1551 State.regs[OP[1]] = 0x7fffffff;
1552 trace_output (OP_REG_REG);
1553 }
1554
1555 return 2;
1556 }
1557
1558 /* tst reg,reg */
1559 int
1560 OP_160 ()
1561 {
1562 unsigned int op0, op1, result, z, s;
1563
1564 trace_input ("tst", OP_REG_REG_CMP, 0);
1565
1566 /* Compute the result. */
1567 op0 = State.regs[ OP[0] ];
1568 op1 = State.regs[ OP[1] ];
1569 result = op0 & op1;
1570
1571 /* Compute the condition codes. */
1572 z = (result == 0);
1573 s = (result & 0x80000000);
1574
1575 /* Store the condition codes. */
1576 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1577 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1578 trace_output (OP_REG_REG_CMP);
1579
1580 return 2;
1581 }
1582
1583 /* mov reg, reg */
1584 int
1585 OP_0 ()
1586 {
1587 trace_input ("mov", OP_REG_REG_MOVE, 0);
1588
1589 State.regs[ OP[1] ] = State.regs[ OP[0] ];
1590
1591 trace_output (OP_REG_REG_MOVE);
1592
1593 return 2;
1594 }
1595
1596 /* mov sign_extend(imm5), reg */
1597 /* callt imm6 */
1598 int
1599 OP_200 ()
1600 {
1601 /* start-sanitize-v850e */
1602 if (OP[1] == 0)
1603 {
1604 unsigned long adr;
1605
1606 trace_input ("callt", OP_LOAD16, 1);
1607
1608 CTPC = PC + 2;
1609 CTPSW = PSW;
1610
1611 adr = CTBP + ((OP[3] & 0x3f) << 1);
1612
1613 PC = CTBP + load_mem (adr, 1);
1614
1615 trace_output (OP_LOAD16);
1616
1617 return 0;
1618 }
1619 else
1620 /* end-sanitize-v850e */
1621 {
1622 int value = SEXT5 (OP[0]);
1623
1624 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1625
1626 State.regs[ OP[1] ] = value;
1627
1628 trace_output (OP_IMM_REG_MOVE);
1629
1630 return 2;
1631 }
1632 }
1633
1634 /* mov imm32, reg1 */
1635 /* movea sign_extend(imm16), reg, reg */
1636 int
1637 OP_620 ()
1638 {
1639 /* start-sanitize-v850e */
1640 if (OP[1] == 0)
1641 {
1642 trace_input ("mov", OP_IMM32_REG, 4);
1643
1644 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
1645
1646 trace_output (OP_IMM32_REG);
1647
1648 return 6;
1649 }
1650 else
1651 /* end-sanitize-v850e */
1652 {
1653 trace_input ("movea", OP_IMM_REG_REG, 0);
1654
1655 State.regs[ OP[1] ] = State.regs[ OP[0] ] + SEXT16 (OP[2]);
1656
1657 trace_output (OP_IMM_REG_REG);
1658
1659 return 4;
1660 }
1661 }
1662
1663 /* dispose imm5, list12 [, reg1] */
1664 /* movhi imm16, reg, reg */
1665 int
1666 OP_640 ()
1667 {
1668 /* start-sanitize-v850e */
1669
1670 if (OP[1] == 0)
1671 {
1672 int i;
1673
1674 trace_input ("dispose", OP_PUSHPOP1, 0);
1675
1676 SP += (OP[3] & 0x3e) << 1;
1677
1678 /* Load the registers with lower number registers being retrieved from higher addresses. */
1679 for (i = 12; i--;)
1680 if ((OP[3] & (1 << type1_regs[ i ])))
1681 {
1682 State.regs[ 20 + i ] = load_mem (SP, 4);
1683 SP += 4;
1684 }
1685
1686 if ((OP[3] & 0x1f0000) != 0)
1687 {
1688 PC = State.regs[ (OP[3] >> 16) & 0x1f];
1689 return 0;
1690 }
1691
1692 trace_output (OP_PUSHPOP1);
1693 }
1694 else
1695 /* end-sanitize-v850e */
1696 {
1697 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1698
1699 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1700
1701 trace_output (OP_UIMM_REG_REG);
1702 }
1703
1704 return 4;
1705 }
1706
1707 /* sar zero_extend(imm5),reg1 */
1708 int
1709 OP_2A0 ()
1710 {
1711 unsigned int op0, op1, result, z, s, cy;
1712
1713 trace_input ("sar", OP_IMM_REG, 0);
1714 op0 = OP[0];
1715 op1 = State.regs[ OP[1] ];
1716 result = (signed)op1 >> op0;
1717
1718 /* Compute the condition codes. */
1719 z = (result == 0);
1720 s = (result & 0x80000000);
1721 cy = (op1 & (1 << (op0 - 1)));
1722
1723 /* Store the result and condition codes. */
1724 State.regs[ OP[1] ] = result;
1725 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1726 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1727 | (cy ? PSW_CY : 0));
1728 trace_output (OP_IMM_REG);
1729
1730 return 2;
1731 }
1732
1733 /* sar reg1, reg2 */
1734 int
1735 OP_A007E0 ()
1736 {
1737 unsigned int op0, op1, result, z, s, cy;
1738
1739 trace_input ("sar", OP_REG_REG, 0);
1740
1741 op0 = State.regs[ OP[0] ] & 0x1f;
1742 op1 = State.regs[ OP[1] ];
1743 result = (signed)op1 >> op0;
1744
1745 /* Compute the condition codes. */
1746 z = (result == 0);
1747 s = (result & 0x80000000);
1748 cy = (op1 & (1 << (op0 - 1)));
1749
1750 /* Store the result and condition codes. */
1751 State.regs[OP[1]] = result;
1752 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1753 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1754 | (cy ? PSW_CY : 0));
1755 trace_output (OP_REG_REG);
1756
1757 return 4;
1758 }
1759
1760 /* shl zero_extend(imm5),reg1 */
1761 int
1762 OP_2C0 ()
1763 {
1764 unsigned int op0, op1, result, z, s, cy;
1765
1766 trace_input ("shl", OP_IMM_REG, 0);
1767 op0 = OP[0];
1768 op1 = State.regs[ OP[1] ];
1769 result = op1 << op0;
1770
1771 /* Compute the condition codes. */
1772 z = (result == 0);
1773 s = (result & 0x80000000);
1774 cy = (op1 & (1 << (32 - op0)));
1775
1776 /* Store the result and condition codes. */
1777 State.regs[OP[1]] = result;
1778 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1779 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1780 | (cy ? PSW_CY : 0));
1781 trace_output (OP_IMM_REG);
1782
1783 return 2;
1784 }
1785
1786 /* shl reg1, reg2 */
1787 int
1788 OP_C007E0 ()
1789 {
1790 unsigned int op0, op1, result, z, s, cy;
1791
1792 trace_input ("shl", OP_REG_REG, 0);
1793 op0 = State.regs[ OP[0] ] & 0x1f;
1794 op1 = State.regs[ OP[1] ];
1795 result = op1 << op0;
1796
1797 /* Compute the condition codes. */
1798 z = (result == 0);
1799 s = (result & 0x80000000);
1800 cy = (op1 & (1 << (32 - op0)));
1801
1802 /* Store the result and condition codes. */
1803 State.regs[OP[1]] = result;
1804 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1805 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1806 | (cy ? PSW_CY : 0));
1807 trace_output (OP_REG_REG);
1808
1809 return 4;
1810 }
1811
1812 /* shr zero_extend(imm5),reg1 */
1813 int
1814 OP_280 ()
1815 {
1816 unsigned int op0, op1, result, z, s, cy;
1817
1818 trace_input ("shr", OP_IMM_REG, 0);
1819 op0 = OP[0];
1820 op1 = State.regs[ OP[1] ];
1821 result = op1 >> op0;
1822
1823 /* Compute the condition codes. */
1824 z = (result == 0);
1825 s = (result & 0x80000000);
1826 cy = (op1 & (1 << (op0 - 1)));
1827
1828 /* Store the result and condition codes. */
1829 State.regs[OP[1]] = result;
1830 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1831 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1832 | (cy ? PSW_CY : 0));
1833 trace_output (OP_IMM_REG);
1834
1835 return 2;
1836 }
1837
1838 /* shr reg1, reg2 */
1839 int
1840 OP_8007E0 ()
1841 {
1842 unsigned int op0, op1, result, z, s, cy;
1843
1844 trace_input ("shr", OP_REG_REG, 0);
1845 op0 = State.regs[ OP[0] ] & 0x1f;
1846 op1 = State.regs[ OP[1] ];
1847 result = op1 >> op0;
1848
1849 /* Compute the condition codes. */
1850 z = (result == 0);
1851 s = (result & 0x80000000);
1852 cy = (op1 & (1 << (op0 - 1)));
1853
1854 /* Store the result and condition codes. */
1855 State.regs[OP[1]] = result;
1856 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1857 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1858 | (cy ? PSW_CY : 0));
1859 trace_output (OP_REG_REG);
1860
1861 return 4;
1862 }
1863
1864 /* or reg, reg */
1865 int
1866 OP_100 ()
1867 {
1868 unsigned int op0, op1, result, z, s;
1869
1870 trace_input ("or", OP_REG_REG, 0);
1871
1872 /* Compute the result. */
1873 op0 = State.regs[ OP[0] ];
1874 op1 = State.regs[ OP[1] ];
1875 result = op0 | op1;
1876
1877 /* Compute the condition codes. */
1878 z = (result == 0);
1879 s = (result & 0x80000000);
1880
1881 /* Store the result and condition codes. */
1882 State.regs[OP[1]] = result;
1883 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1884 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1885 trace_output (OP_REG_REG);
1886
1887 return 2;
1888 }
1889
1890 /* ori zero_extend(imm16), reg, reg */
1891 int
1892 OP_680 ()
1893 {
1894 unsigned int op0, op1, result, z, s;
1895
1896 trace_input ("ori", OP_UIMM_REG_REG, 0);
1897 op0 = OP[2];
1898 op1 = State.regs[ OP[0] ];
1899 result = op0 | op1;
1900
1901 /* Compute the condition codes. */
1902 z = (result == 0);
1903 s = (result & 0x80000000);
1904
1905 /* Store the result and condition codes. */
1906 State.regs[OP[1]] = result;
1907 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1908 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1909 trace_output (OP_UIMM_REG_REG);
1910
1911 return 4;
1912 }
1913
1914 /* and reg, reg */
1915 int
1916 OP_140 ()
1917 {
1918 unsigned int op0, op1, result, z, s;
1919
1920 trace_input ("and", OP_REG_REG, 0);
1921
1922 /* Compute the result. */
1923 op0 = State.regs[ OP[0] ];
1924 op1 = State.regs[ OP[1] ];
1925 result = op0 & op1;
1926
1927 /* Compute the condition codes. */
1928 z = (result == 0);
1929 s = (result & 0x80000000);
1930
1931 /* Store the result and condition codes. */
1932 State.regs[OP[1]] = result;
1933 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1934 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1935 trace_output (OP_REG_REG);
1936
1937 return 2;
1938 }
1939
1940 /* andi zero_extend(imm16), reg, reg */
1941 int
1942 OP_6C0 ()
1943 {
1944 unsigned int result, z;
1945
1946 trace_input ("andi", OP_UIMM_REG_REG, 0);
1947
1948 result = OP[2] & State.regs[ OP[0] ];
1949
1950 /* Compute the condition codes. */
1951 z = (result == 0);
1952
1953 /* Store the result and condition codes. */
1954 State.regs[ OP[1] ] = result;
1955
1956 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1957 PSW |= (z ? PSW_Z : 0);
1958
1959 trace_output (OP_UIMM_REG_REG);
1960
1961 return 4;
1962 }
1963
1964 /* xor reg, reg */
1965 int
1966 OP_120 ()
1967 {
1968 unsigned int op0, op1, result, z, s;
1969
1970 trace_input ("xor", OP_REG_REG, 0);
1971
1972 /* Compute the result. */
1973 op0 = State.regs[ OP[0] ];
1974 op1 = State.regs[ OP[1] ];
1975 result = op0 ^ op1;
1976
1977 /* Compute the condition codes. */
1978 z = (result == 0);
1979 s = (result & 0x80000000);
1980
1981 /* Store the result and condition codes. */
1982 State.regs[OP[1]] = result;
1983 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1984 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1985 trace_output (OP_REG_REG);
1986
1987 return 2;
1988 }
1989
1990 /* xori zero_extend(imm16), reg, reg */
1991 int
1992 OP_6A0 ()
1993 {
1994 unsigned int op0, op1, result, z, s;
1995
1996 trace_input ("xori", OP_UIMM_REG_REG, 0);
1997 op0 = OP[2];
1998 op1 = State.regs[ OP[0] ];
1999 result = op0 ^ op1;
2000
2001 /* Compute the condition codes. */
2002 z = (result == 0);
2003 s = (result & 0x80000000);
2004
2005 /* Store the result and condition codes. */
2006 State.regs[OP[1]] = result;
2007 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2008 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2009 trace_output (OP_UIMM_REG_REG);
2010
2011 return 4;
2012 }
2013
2014 /* not reg1, reg2 */
2015 int
2016 OP_20 ()
2017 {
2018 unsigned int op0, result, z, s;
2019
2020 trace_input ("not", OP_REG_REG_MOVE, 0);
2021 /* Compute the result. */
2022 op0 = State.regs[ OP[0] ];
2023 result = ~op0;
2024
2025 /* Compute the condition codes. */
2026 z = (result == 0);
2027 s = (result & 0x80000000);
2028
2029 /* Store the result and condition codes. */
2030 State.regs[OP[1]] = result;
2031 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2032 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2033 trace_output (OP_REG_REG_MOVE);
2034
2035 return 2;
2036 }
2037
2038 /* set1 */
2039 int
2040 OP_7C0 ()
2041 {
2042 unsigned int op0, op1, op2;
2043 int temp;
2044
2045 trace_input ("set1", OP_BIT, 0);
2046 op0 = State.regs[ OP[0] ];
2047 op1 = OP[1] & 0x7;
2048 temp = SEXT16 (OP[2]);
2049 op2 = temp;
2050 temp = load_mem (op0 + op2, 1);
2051 PSW &= ~PSW_Z;
2052 if ((temp & (1 << op1)) == 0)
2053 PSW |= PSW_Z;
2054 temp |= (1 << op1);
2055 store_mem (op0 + op2, 1, temp);
2056 trace_output (OP_BIT);
2057
2058 return 4;
2059 }
2060
2061 /* not1 */
2062 int
2063 OP_47C0 ()
2064 {
2065 unsigned int op0, op1, op2;
2066 int temp;
2067
2068 trace_input ("not1", OP_BIT, 0);
2069 op0 = State.regs[ OP[0] ];
2070 op1 = OP[1] & 0x7;
2071 temp = SEXT16 (OP[2]);
2072 op2 = temp;
2073 temp = load_mem (op0 + op2, 1);
2074 PSW &= ~PSW_Z;
2075 if ((temp & (1 << op1)) == 0)
2076 PSW |= PSW_Z;
2077 temp ^= (1 << op1);
2078 store_mem (op0 + op2, 1, temp);
2079 trace_output (OP_BIT);
2080
2081 return 4;
2082 }
2083
2084 /* clr1 */
2085 int
2086 OP_87C0 ()
2087 {
2088 unsigned int op0, op1, op2;
2089 int temp;
2090
2091 trace_input ("clr1", OP_BIT, 0);
2092 op0 = State.regs[ OP[0] ];
2093 op1 = OP[1] & 0x7;
2094 temp = SEXT16 (OP[2]);
2095 op2 = temp;
2096 temp = load_mem (op0 + op2, 1);
2097 PSW &= ~PSW_Z;
2098 if ((temp & (1 << op1)) == 0)
2099 PSW |= PSW_Z;
2100 temp &= ~(1 << op1);
2101 store_mem (op0 + op2, 1, temp);
2102 trace_output (OP_BIT);
2103
2104 return 4;
2105 }
2106
2107 /* tst1 */
2108 int
2109 OP_C7C0 ()
2110 {
2111 unsigned int op0, op1, op2;
2112 int temp;
2113
2114 trace_input ("tst1", OP_BIT, 0);
2115 op0 = State.regs[ OP[0] ];
2116 op1 = OP[1] & 0x7;
2117 temp = SEXT16 (OP[2]);
2118 op2 = temp;
2119 temp = load_mem (op0 + op2, 1);
2120 PSW &= ~PSW_Z;
2121 if ((temp & (1 << op1)) == 0)
2122 PSW |= PSW_Z;
2123 trace_output (OP_BIT);
2124
2125 return 4;
2126 }
2127
2128 /* breakpoint */
2129 int
2130 OP_FFFF ()
2131 {
2132 State.exception = SIGTRAP;
2133 return -4;
2134 }
2135
2136 /* di */
2137 int
2138 OP_16007E0 ()
2139 {
2140 trace_input ("di", OP_NONE, 0);
2141 PSW |= PSW_ID;
2142 trace_output (OP_NONE);
2143
2144 return 4;
2145 }
2146
2147 /* ei */
2148 int
2149 OP_16087E0 ()
2150 {
2151 trace_input ("ei", OP_NONE, 0);
2152 PSW &= ~PSW_ID;
2153 trace_output (OP_NONE);
2154
2155 return 4;
2156 }
2157
2158 /* halt */
2159 int
2160 OP_12007E0 ()
2161 {
2162 trace_input ("halt", OP_NONE, 0);
2163 /* FIXME this should put processor into a mode where NMI still handled */
2164 State.exception = SIGQUIT;
2165 trace_output (OP_NONE);
2166
2167 return 4;
2168 }
2169
2170 /* reti */
2171 int
2172 OP_14007E0 ()
2173 {
2174 trace_input ("reti", OP_NONE, 0);
2175 trace_output (OP_NONE);
2176
2177 /* Restore for NMI if only NP on, otherwise is interrupt or exception. */
2178 if ((PSW & (PSW_NP | PSW_EP)) == PSW_NP)
2179 {
2180 PC = FEPC - 4;
2181 PSW = FEPSW;
2182 }
2183 else
2184 {
2185 PC = EIPC - 4;
2186 PSW = EIPSW;
2187 }
2188
2189 return 0;
2190 }
2191
2192 /* trap */
2193 int
2194 OP_10007E0 ()
2195 {
2196 trace_input ("trap", OP_TRAP, 0);
2197 trace_output (OP_TRAP);
2198
2199 /* Trap 31 is used for simulating OS I/O functions */
2200
2201 if (OP[0] == 31)
2202 {
2203 int save_errno = errno;
2204 errno = 0;
2205
2206 /* Registers passed to trap 0 */
2207
2208 #define FUNC State.regs[6] /* function number, return value */
2209 #define PARM1 State.regs[7] /* optional parm 1 */
2210 #define PARM2 State.regs[8] /* optional parm 2 */
2211 #define PARM3 State.regs[9] /* optional parm 3 */
2212
2213 /* Registers set by trap 0 */
2214
2215 #define RETVAL State.regs[10] /* return value */
2216 #define RETERR State.regs[11] /* return error code */
2217
2218 /* Turn a pointer in a register into a pointer into real memory. */
2219
2220 #define MEMPTR(x) (map (x))
2221
2222 switch (FUNC)
2223 {
2224
2225 #if !defined(__GO32__) && !defined(_WIN32)
2226 #ifdef SYS_fork
2227 case SYS_fork:
2228 RETVAL = fork ();
2229 break;
2230 #endif
2231 #endif
2232
2233 #if !defined(__GO32__) && !defined(_WIN32)
2234 #ifdef SYS_execv
2235 case SYS_execve:
2236 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2237 (char **)MEMPTR (PARM3));
2238 break;
2239 #endif
2240 #endif
2241
2242 #if !defined(__GO32__) && !defined(_WIN32)
2243 #ifdef SYS_execv
2244 case SYS_execv:
2245 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2246 break;
2247 #endif
2248 #endif
2249
2250 #if 0
2251 #ifdef SYS_pipe
2252 case SYS_pipe:
2253 {
2254 reg_t buf;
2255 int host_fd[2];
2256
2257 buf = PARM1;
2258 RETVAL = pipe (host_fd);
2259 SW (buf, host_fd[0]);
2260 buf += sizeof(uint16);
2261 SW (buf, host_fd[1]);
2262 }
2263 break;
2264 #endif
2265 #endif
2266
2267 #if 0
2268 #ifdef SYS_wait
2269 case SYS_wait:
2270 {
2271 int status;
2272
2273 RETVAL = wait (&status);
2274 SW (PARM1, status);
2275 }
2276 break;
2277 #endif
2278 #endif
2279
2280 #ifdef SYS_read
2281 case SYS_read:
2282 RETVAL = sim_io_read (simulator, PARM1, MEMPTR (PARM2), PARM3);
2283 break;
2284 #endif
2285
2286 #ifdef SYS_write
2287 case SYS_write:
2288 if (PARM1 == 1)
2289 RETVAL = sim_io_write_stdout (simulator, MEMPTR (PARM2), PARM3);
2290 else
2291 RETVAL = sim_io_write (simulator, PARM1, MEMPTR (PARM2), PARM3);
2292 break;
2293 #endif
2294
2295 #ifdef SYS_lseek
2296 case SYS_lseek:
2297 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
2298 break;
2299 #endif
2300
2301 #ifdef SYS_close
2302 case SYS_close:
2303 RETVAL = sim_io_close (simulator, PARM1);
2304 break;
2305 #endif
2306
2307 #ifdef SYS_open
2308 case SYS_open:
2309 RETVAL = sim_io_open (simulator, MEMPTR (PARM1), PARM2);
2310 break;
2311 #endif
2312
2313 #ifdef SYS_exit
2314 case SYS_exit:
2315 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
2316 State.exception = PARM1 & 0xffff; /* get signal encoded by kill */
2317 else if (PARM1 == 0xdead)
2318 State.exception = SIGABRT; /* old libraries */
2319 else
2320 State.exception = SIG_V850_EXIT; /* PARM1 has exit status encoded */
2321 break;
2322 #endif
2323
2324 #if !defined(__GO32__) && !defined(_WIN32)
2325 #ifdef SYS_stat
2326 case SYS_stat: /* added at hmsi */
2327 /* stat system call */
2328 {
2329 struct stat host_stat;
2330 reg_t buf;
2331
2332 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2333
2334 buf = PARM2;
2335
2336 /* Just wild-assed guesses. */
2337 store_mem (buf, 2, host_stat.st_dev);
2338 store_mem (buf + 2, 2, host_stat.st_ino);
2339 store_mem (buf + 4, 4, host_stat.st_mode);
2340 store_mem (buf + 8, 2, host_stat.st_nlink);
2341 store_mem (buf + 10, 2, host_stat.st_uid);
2342 store_mem (buf + 12, 2, host_stat.st_gid);
2343 store_mem (buf + 14, 2, host_stat.st_rdev);
2344 store_mem (buf + 16, 4, host_stat.st_size);
2345 store_mem (buf + 20, 4, host_stat.st_atime);
2346 store_mem (buf + 28, 4, host_stat.st_mtime);
2347 store_mem (buf + 36, 4, host_stat.st_ctime);
2348 }
2349 break;
2350 #endif
2351 #endif
2352
2353 #if !defined(__GO32__) && !defined(_WIN32)
2354 #ifdef SYS_chown
2355 case SYS_chown:
2356 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2357 break;
2358 #endif
2359 #endif
2360
2361 #ifdef SYS_chmod
2362 #if HAVE_CHMOD
2363 case SYS_chmod:
2364 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2365 break;
2366 #endif
2367 #endif
2368
2369 #ifdef SYS_time
2370 #if HAVE_TIME
2371 case SYS_time:
2372 {
2373 time_t now;
2374 RETVAL = time (&now);
2375 store_mem (PARM1, 4, now);
2376 }
2377 break;
2378 #endif
2379 #endif
2380
2381 #if !defined(__GO32__) && !defined(_WIN32)
2382 #ifdef SYS_times
2383 case SYS_times:
2384 {
2385 struct tms tms;
2386 RETVAL = times (&tms);
2387 store_mem (PARM1, 4, tms.tms_utime);
2388 store_mem (PARM1 + 4, 4, tms.tms_stime);
2389 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2390 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2391 break;
2392 }
2393 #endif
2394 #endif
2395
2396 #ifdef SYS_gettimeofday
2397 #if !defined(__GO32__) && !defined(_WIN32)
2398 case SYS_gettimeofday:
2399 {
2400 struct timeval t;
2401 struct timezone tz;
2402 RETVAL = gettimeofday (&t, &tz);
2403 store_mem (PARM1, 4, t.tv_sec);
2404 store_mem (PARM1 + 4, 4, t.tv_usec);
2405 store_mem (PARM2, 4, tz.tz_minuteswest);
2406 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2407 break;
2408 }
2409 #endif
2410 #endif
2411
2412 #ifdef SYS_utime
2413 #if HAVE_UTIME
2414 case SYS_utime:
2415 /* Cast the second argument to void *, to avoid type mismatch
2416 if a prototype is present. */
2417 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2418 break;
2419 #endif
2420 #endif
2421
2422 default:
2423 abort ();
2424 }
2425 RETERR = errno;
2426 errno = save_errno;
2427
2428 return 4;
2429 }
2430 else
2431 { /* Trap 0 -> 30 */
2432 EIPC = PC + 4;
2433 EIPSW = PSW;
2434 /* Mask out EICC */
2435 ECR &= 0xffff0000;
2436 ECR |= 0x40 + OP[0];
2437 /* Flag that we are now doing exception processing. */
2438 PSW |= PSW_EP | PSW_ID;
2439 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
2440
2441 return 0;
2442 }
2443 }
2444
2445 /* ldsr, reg,reg */
2446 int
2447 OP_2007E0 ()
2448 {
2449 trace_input ("ldsr", OP_LDSR, 0);
2450
2451 State.sregs[ OP[1] ] = State.regs[ OP[0] ];
2452
2453 trace_output (OP_LDSR);
2454
2455 return 4;
2456 }
2457
2458 /* stsr */
2459 int
2460 OP_4007E0 ()
2461 {
2462 trace_input ("stsr", OP_STSR, 0);
2463
2464 State.regs[ OP[1] ] = State.sregs[ OP[0] ];
2465
2466 trace_output (OP_STSR);
2467
2468 return 4;
2469 }
2470
2471 /* tst1 reg2, [reg1] */
2472 int
2473 OP_E607E0 (void)
2474 {
2475 int temp;
2476
2477 trace_input ("tst1", OP_BIT_LOAD, 1);
2478
2479 temp = load_mem (State.regs[ OP[0] ], 1);
2480
2481 PSW &= ~PSW_Z;
2482 if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
2483 PSW |= PSW_Z;
2484
2485 trace_output (OP_BIT_LOAD);
2486
2487 return 4;
2488 }
2489
2490 /* mulu reg1, reg2, reg3 */
2491 int
2492 OP_22207E0 (void)
2493 {
2494 trace_input ("mulu", OP_REG_REG_REG, 0);
2495
2496 Multiply64 (false, State.regs[ OP[0] ]);
2497
2498 trace_output (OP_REG_REG_REG);
2499
2500 return 4;
2501 }
2502
2503 /* start-sanitize-v850e */
2504
2505 #define BIT_CHANGE_OP( name, binop ) \
2506 unsigned int bit; \
2507 unsigned int temp; \
2508 \
2509 trace_input (name, OP_BIT_CHANGE, 0); \
2510 \
2511 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
2512 temp = load_mem (State.regs[ OP[0] ], 1); \
2513 \
2514 PSW &= ~PSW_Z; \
2515 if ((temp & bit) == 0) \
2516 PSW |= PSW_Z; \
2517 temp binop bit; \
2518 \
2519 store_mem (State.regs[ OP[0] ], 1, temp); \
2520 \
2521 trace_output (OP_BIT_CHANGE); \
2522 \
2523 return 4;
2524
2525 /* clr1 reg2, [reg1] */
2526 int
2527 OP_E407E0 (void)
2528 {
2529 BIT_CHANGE_OP ("clr1", &= ~ );
2530 }
2531
2532 /* not1 reg2, [reg1] */
2533 int
2534 OP_E207E0 (void)
2535 {
2536 BIT_CHANGE_OP ("not1", ^= );
2537 }
2538
2539 /* set1 */
2540 int
2541 OP_E007E0 (void)
2542 {
2543 BIT_CHANGE_OP ("set1", |= );
2544 }
2545
2546 /* sasf */
2547 int
2548 OP_20007E0 (void)
2549 {
2550 trace_input ("sasf", OP_EX1, 0);
2551
2552 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2553
2554 trace_output (OP_EX1);
2555
2556 return 4;
2557 }
2558 /* end-sanitize-v850e */
2559
2560 /* start-sanitize-v850eq */
2561 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2562 static void
2563 divun
2564 (
2565 unsigned int N,
2566 unsigned long int als,
2567 unsigned long int sfi,
2568 unsigned long int * quotient_ptr,
2569 unsigned long int * remainder_ptr,
2570 boolean * overflow_ptr
2571 )
2572 {
2573 unsigned long ald = sfi >> (N - 1);
2574 unsigned long alo = als;
2575 unsigned int Q = 1;
2576 unsigned int C;
2577 unsigned int S = 0;
2578 unsigned int i;
2579 unsigned int R1 = 1;
2580 unsigned int DBZ = (als == 0) ? 1 : 0;
2581 unsigned long alt = Q ? ~als : als;
2582
2583 /* 1st Loop */
2584 alo = ald + alt + Q;
2585 C = (((alt >> 31) & (ald >> 31))
2586 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2587 C = C ^ Q;
2588 Q = ~(C ^ S) & 1;
2589 R1 = (alo == 0) ? 0 : (R1 & Q);
2590 if ((S ^ (alo>>31)) && !C)
2591 {
2592 DBZ = 1;
2593 }
2594 S = alo >> 31;
2595 sfi = (sfi << (32-N+1)) | Q;
2596 ald = (alo << 1) | (sfi >> 31);
2597
2598 /* 2nd - N-1th Loop */
2599 for (i = 2; i < N; i++)
2600 {
2601 alt = Q ? ~als : als;
2602 alo = ald + alt + Q;
2603 C = (((alt >> 31) & (ald >> 31))
2604 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2605 C = C ^ Q;
2606 Q = ~(C ^ S) & 1;
2607 R1 = (alo == 0) ? 0 : (R1 & Q);
2608 if ((S ^ (alo>>31)) && !C && !DBZ)
2609 {
2610 DBZ = 1;
2611 }
2612 S = alo >> 31;
2613 sfi = (sfi << 1) | Q;
2614 ald = (alo << 1) | (sfi >> 31);
2615 }
2616
2617 /* Nth Loop */
2618 alt = Q ? ~als : als;
2619 alo = ald + alt + Q;
2620 C = (((alt >> 31) & (ald >> 31))
2621 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2622 C = C ^ Q;
2623 Q = ~(C ^ S) & 1;
2624 R1 = (alo == 0) ? 0 : (R1 & Q);
2625 if ((S ^ (alo>>31)) && !C)
2626 {
2627 DBZ = 1;
2628 }
2629
2630 * quotient_ptr = (sfi << 1) | Q;
2631 * remainder_ptr = Q ? alo : (alo + als);
2632 * overflow_ptr = DBZ | R1;
2633 }
2634
2635 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2636 static void
2637 divn
2638 (
2639 unsigned int N,
2640 unsigned long int als,
2641 unsigned long int sfi,
2642 signed long int * quotient_ptr,
2643 signed long int * remainder_ptr,
2644 boolean * overflow_ptr
2645 )
2646 {
2647 unsigned long ald = (signed long) sfi >> (N - 1);
2648 unsigned long alo = als;
2649 unsigned int SS = als >> 31;
2650 unsigned int SD = sfi >> 31;
2651 unsigned int R1 = 1;
2652 unsigned int OV;
2653 unsigned int DBZ = als == 0 ? 1 : 0;
2654 unsigned int Q = ~(SS ^ SD) & 1;
2655 unsigned int C;
2656 unsigned int S;
2657 unsigned int i;
2658 unsigned long alt = Q ? ~als : als;
2659
2660
2661 /* 1st Loop */
2662
2663 alo = ald + alt + Q;
2664 C = (((alt >> 31) & (ald >> 31))
2665 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2666 Q = C ^ SS;
2667 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2668 S = alo >> 31;
2669 sfi = (sfi << (32-N+1)) | Q;
2670 ald = (alo << 1) | (sfi >> 31);
2671 if ((alo >> 31) ^ (ald >> 31))
2672 {
2673 DBZ = 1;
2674 }
2675
2676 /* 2nd - N-1th Loop */
2677
2678 for (i = 2; i < N; i++)
2679 {
2680 alt = Q ? ~als : als;
2681 alo = ald + alt + Q;
2682 C = (((alt >> 31) & (ald >> 31))
2683 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2684 Q = C ^ SS;
2685 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2686 S = alo >> 31;
2687 sfi = (sfi << 1) | Q;
2688 ald = (alo << 1) | (sfi >> 31);
2689 if ((alo >> 31) ^ (ald >> 31))
2690 {
2691 DBZ = 1;
2692 }
2693 }
2694
2695 /* Nth Loop */
2696 alt = Q ? ~als : als;
2697 alo = ald + alt + Q;
2698 C = (((alt >> 31) & (ald >> 31))
2699 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2700 Q = C ^ SS;
2701 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2702 sfi = (sfi << (32-N+1));
2703 ald = alo;
2704
2705 /* End */
2706 if (alo != 0)
2707 {
2708 alt = Q ? ~als : als;
2709 alo = ald + alt + Q;
2710 }
2711 R1 = R1 & ((~alo >> 31) ^ SD);
2712 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2713 if (N != 32)
2714 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2715 else
2716 ald = sfi = sfi | Q;
2717
2718 OV = DBZ | ((alo == 0) ? 0 : R1);
2719
2720 * remainder_ptr = alo;
2721
2722 /* Adj */
2723 if (((alo != 0) && ((SS ^ SD) ^ R1))
2724 || ((alo == 0) && (SS ^ R1)))
2725 alo = ald + 1;
2726 else
2727 alo = ald;
2728
2729 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2730
2731 * quotient_ptr = alo;
2732 * overflow_ptr = OV;
2733 }
2734
2735 /* sdivun imm5, reg1, reg2, reg3 */
2736 int
2737 OP_1C207E0 (void)
2738 {
2739 unsigned long int quotient;
2740 unsigned long int remainder;
2741 unsigned long int divide_by;
2742 unsigned long int divide_this;
2743 boolean overflow = false;
2744 unsigned int imm5;
2745
2746 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2747
2748 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2749
2750 divide_by = State.regs[ OP[0] ];
2751 divide_this = State.regs[ OP[1] ] << imm5;
2752
2753 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2754
2755 State.regs[ OP[1] ] = quotient;
2756 State.regs[ OP[2] >> 11 ] = remainder;
2757
2758 /* Set condition codes. */
2759 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2760
2761 if (overflow) PSW |= PSW_OV;
2762 if (quotient == 0) PSW |= PSW_Z;
2763 if (quotient & 0x80000000) PSW |= PSW_S;
2764
2765 trace_output (OP_IMM_REG_REG_REG);
2766
2767 return 4;
2768 }
2769
2770 /* sdivn imm5, reg1, reg2, reg3 */
2771 int
2772 OP_1C007E0 (void)
2773 {
2774 signed long int quotient;
2775 signed long int remainder;
2776 signed long int divide_by;
2777 signed long int divide_this;
2778 boolean overflow = false;
2779 unsigned int imm5;
2780
2781 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2782
2783 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2784
2785 divide_by = State.regs[ OP[0] ];
2786 divide_this = State.regs[ OP[1] ] << imm5;
2787
2788 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2789
2790 State.regs[ OP[1] ] = quotient;
2791 State.regs[ OP[2] >> 11 ] = remainder;
2792
2793 /* Set condition codes. */
2794 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2795
2796 if (overflow) PSW |= PSW_OV;
2797 if (quotient == 0) PSW |= PSW_Z;
2798 if (quotient < 0) PSW |= PSW_S;
2799
2800 trace_output (OP_IMM_REG_REG_REG);
2801
2802 return 4;
2803 }
2804
2805 /* sdivhun imm5, reg1, reg2, reg3 */
2806 int
2807 OP_18207E0 (void)
2808 {
2809 unsigned long int quotient;
2810 unsigned long int remainder;
2811 unsigned long int divide_by;
2812 unsigned long int divide_this;
2813 boolean overflow = false;
2814 unsigned int imm5;
2815
2816 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2817
2818 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2819
2820 divide_by = State.regs[ OP[0] ] & 0xffff;
2821 divide_this = State.regs[ OP[1] ] << imm5;
2822
2823 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2824
2825 State.regs[ OP[1] ] = quotient;
2826 State.regs[ OP[2] >> 11 ] = remainder;
2827
2828 /* Set condition codes. */
2829 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2830
2831 if (overflow) PSW |= PSW_OV;
2832 if (quotient == 0) PSW |= PSW_Z;
2833 if (quotient & 0x80000000) PSW |= PSW_S;
2834
2835 trace_output (OP_IMM_REG_REG_REG);
2836
2837 return 4;
2838 }
2839
2840 /* sdivhn imm5, reg1, reg2, reg3 */
2841 int
2842 OP_18007E0 (void)
2843 {
2844 signed long int quotient;
2845 signed long int remainder;
2846 signed long int divide_by;
2847 signed long int divide_this;
2848 boolean overflow = false;
2849 unsigned int imm5;
2850
2851 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2852
2853 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2854
2855 divide_by = SEXT16 (State.regs[ OP[0] ]);
2856 divide_this = State.regs[ OP[1] ] << imm5;
2857
2858 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2859
2860 State.regs[ OP[1] ] = quotient;
2861 State.regs[ OP[2] >> 11 ] = remainder;
2862
2863 /* Set condition codes. */
2864 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2865
2866 if (overflow) PSW |= PSW_OV;
2867 if (quotient == 0) PSW |= PSW_Z;
2868 if (quotient < 0) PSW |= PSW_S;
2869
2870 trace_output (OP_IMM_REG_REG_REG);
2871
2872 return 4;
2873 }
2874 /* end-sanitize-v850eq */
2875
2876 /* start-sanitize-v850e */
2877 /* divu reg1, reg2, reg3 */
2878 int
2879 OP_2C207E0 (void)
2880 {
2881 unsigned long int quotient;
2882 unsigned long int remainder;
2883 unsigned long int divide_by;
2884 unsigned long int divide_this;
2885 boolean overflow = false;
2886
2887 if ((OP[3] & 0x3c0000) == 0)
2888 {
2889 trace_input ("divu", OP_REG_REG_REG, 0);
2890
2891 /* Compute the result. */
2892
2893 divide_by = State.regs[ OP[0] ];
2894 divide_this = State.regs[ OP[1] ];
2895
2896 if (divide_by == 0)
2897 {
2898 overflow = true;
2899 divide_by = 1;
2900 }
2901
2902 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2903 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2904
2905 /* Set condition codes. */
2906 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2907
2908 if (overflow) PSW |= PSW_OV;
2909 if (quotient == 0) PSW |= PSW_Z;
2910 if (quotient & 0x80000000) PSW |= PSW_S;
2911
2912 trace_output (OP_REG_REG_REG);
2913 }
2914 /* start-sanitize-v850eq */
2915 /* divun imm5, reg1, reg2, reg3 */
2916 else
2917 {
2918 unsigned int imm5;
2919
2920 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
2921
2922 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2923
2924 divide_by = State.regs[ OP[0] ];
2925 divide_this = State.regs[ OP[1] ];
2926
2927 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2928
2929 State.regs[ OP[1] ] = quotient;
2930 State.regs[ OP[2] >> 11 ] = remainder;
2931
2932 /* Set condition codes. */
2933 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2934
2935 if (overflow) PSW |= PSW_OV;
2936 if (quotient == 0) PSW |= PSW_Z;
2937 if (quotient & 0x80000000) PSW |= PSW_S;
2938
2939 trace_output (OP_IMM_REG_REG_REG);
2940 }
2941 /* end-sanitize-v850eq */
2942
2943 return 4;
2944 }
2945
2946 /* div reg1, reg2, reg3 */
2947 int
2948 OP_2C007E0 (void)
2949 {
2950 signed long int quotient;
2951 signed long int remainder;
2952 signed long int divide_by;
2953 signed long int divide_this;
2954 boolean overflow = false;
2955
2956 if ((OP[3] & 0x3c0000) == 0)
2957 {
2958 trace_input ("div", OP_REG_REG_REG, 0);
2959
2960 /* Compute the result. */
2961
2962 divide_by = State.regs[ OP[0] ];
2963 divide_this = State.regs[ OP[1] ];
2964
2965 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2966 {
2967 overflow = true;
2968 divide_by = 1;
2969 }
2970
2971 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2972 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2973
2974 /* Set condition codes. */
2975 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2976
2977 if (overflow) PSW |= PSW_OV;
2978 if (quotient == 0) PSW |= PSW_Z;
2979 if (quotient < 0) PSW |= PSW_S;
2980
2981 trace_output (OP_REG_REG_REG);
2982 }
2983 /* start-sanitize-v850eq */
2984 /* divn imm5, reg1, reg2, reg3 */
2985 else
2986 {
2987 unsigned int imm5;
2988
2989 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
2990
2991 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2992
2993 divide_by = State.regs[ OP[0] ];
2994 divide_this = State.regs[ OP[1] ];
2995
2996 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2997
2998 State.regs[ OP[1] ] = quotient;
2999 State.regs[ OP[2] >> 11 ] = remainder;
3000
3001 /* Set condition codes. */
3002 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3003
3004 if (overflow) PSW |= PSW_OV;
3005 if (quotient == 0) PSW |= PSW_Z;
3006 if (quotient < 0) PSW |= PSW_S;
3007
3008 trace_output (OP_IMM_REG_REG_REG);
3009 }
3010 /* end-sanitize-v850eq */
3011
3012 return 4;
3013 }
3014
3015 /* divhu reg1, reg2, reg3 */
3016 int
3017 OP_28207E0 (void)
3018 {
3019 unsigned long int quotient;
3020 unsigned long int remainder;
3021 unsigned long int divide_by;
3022 unsigned long int divide_this;
3023 boolean overflow = false;
3024
3025 if ((OP[3] & 0x3c0000) == 0)
3026 {
3027 trace_input ("divhu", OP_REG_REG_REG, 0);
3028
3029 /* Compute the result. */
3030
3031 divide_by = State.regs[ OP[0] ] & 0xffff;
3032 divide_this = State.regs[ OP[1] ];
3033
3034 if (divide_by == 0)
3035 {
3036 overflow = true;
3037 divide_by = 1;
3038 }
3039
3040 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3041 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3042
3043 /* Set condition codes. */
3044 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3045
3046 if (overflow) PSW |= PSW_OV;
3047 if (quotient == 0) PSW |= PSW_Z;
3048 if (quotient & 0x80000000) PSW |= PSW_S;
3049
3050 trace_output (OP_REG_REG_REG);
3051 }
3052 /* start-sanitize-v850eq */
3053 /* divhun imm5, reg1, reg2, reg3 */
3054 else
3055 {
3056 unsigned int imm5;
3057
3058 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
3059
3060 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3061
3062 divide_by = State.regs[ OP[0] ] & 0xffff;
3063 divide_this = State.regs[ OP[1] ];
3064
3065 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3066
3067 State.regs[ OP[1] ] = quotient;
3068 State.regs[ OP[2] >> 11 ] = remainder;
3069
3070 /* Set condition codes. */
3071 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3072
3073 if (overflow) PSW |= PSW_OV;
3074 if (quotient == 0) PSW |= PSW_Z;
3075 if (quotient & 0x80000000) PSW |= PSW_S;
3076
3077 trace_output (OP_IMM_REG_REG_REG);
3078 }
3079 /* end-sanitize-v850eq */
3080
3081 return 4;
3082 }
3083
3084 /* divh reg1, reg2, reg3 */
3085 int
3086 OP_28007E0 (void)
3087 {
3088 signed long int quotient;
3089 signed long int remainder;
3090 signed long int divide_by;
3091 signed long int divide_this;
3092 boolean overflow = false;
3093
3094 if ((OP[3] & 0x3c0000) == 0)
3095 {
3096 trace_input ("divh", OP_REG_REG_REG, 0);
3097
3098 /* Compute the result. */
3099
3100 divide_by = State.regs[ OP[0] ];
3101 divide_this = SEXT16 (State.regs[ OP[1] ]);
3102
3103 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3104 {
3105 overflow = true;
3106 divide_by = 1;
3107 }
3108
3109 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3110 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3111
3112 /* Set condition codes. */
3113 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3114
3115 if (overflow) PSW |= PSW_OV;
3116 if (quotient == 0) PSW |= PSW_Z;
3117 if (quotient < 0) PSW |= PSW_S;
3118
3119 trace_output (OP_REG_REG_REG);
3120 }
3121 /* start-sanitize-v850eq */
3122 /* divhn imm5, reg1, reg2, reg3 */
3123 else
3124 {
3125 unsigned int imm5;
3126
3127 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
3128
3129 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3130
3131 divide_by = SEXT16 (State.regs[ OP[0] ]);
3132 divide_this = State.regs[ OP[1] ];
3133
3134 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3135
3136 State.regs[ OP[1] ] = quotient;
3137 State.regs[ OP[2] >> 11 ] = remainder;
3138
3139 /* Set condition codes. */
3140 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3141
3142 if (overflow) PSW |= PSW_OV;
3143 if (quotient == 0) PSW |= PSW_Z;
3144 if (quotient < 0) PSW |= PSW_S;
3145
3146 trace_output (OP_IMM_REG_REG_REG);
3147 }
3148 /* end-sanitize-v850eq */
3149
3150 return 4;
3151 }
3152
3153 /* mulu imm9, reg2, reg3 */
3154 int
3155 OP_24207E0 (void)
3156 {
3157 trace_input ("mulu", OP_IMM_REG_REG, 0);
3158
3159 Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
3160
3161 trace_output (OP_IMM_REG_REG);
3162
3163 return 4;
3164 }
3165
3166 /* mul imm9, reg2, reg3 */
3167 int
3168 OP_24007E0 (void)
3169 {
3170 trace_input ("mul", OP_IMM_REG_REG, 0);
3171
3172 Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
3173
3174 trace_output (OP_IMM_REG_REG);
3175
3176 return 4;
3177 }
3178
3179 /* cmov imm5, reg2, reg3 */
3180 int
3181 OP_30007E0 (void)
3182 {
3183 trace_input ("cmov", OP_IMM_REG_REG, 0);
3184
3185 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? SEXT5( OP[0] ) : State.regs[ OP[1] ];
3186
3187 trace_output (OP_IMM_REG_REG);
3188
3189 return 4;
3190
3191 }
3192
3193 /* ctret */
3194 int
3195 OP_14407E0 (void)
3196 {
3197 trace_input ("ctret", OP_NONE, 0);
3198
3199 PC = CTPC;
3200 PSW = CTPSW;
3201
3202 trace_output (OP_NONE);
3203
3204 return 0;
3205 }
3206
3207 /* hsw */
3208 int
3209 OP_34407E0 (void)
3210 {
3211 unsigned long value;
3212
3213 trace_input ("hsw", OP_REG_REG3, 0);
3214
3215 value = State.regs[ OP[ 1 ] ];
3216 value >>= 16;
3217 value |= (State.regs[ OP[ 1 ] ] << 16);
3218
3219 State.regs[ OP[2] >> 11 ] = value;
3220
3221 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3222
3223 if (value == 0) PSW |= PSW_Z;
3224 if (value & 0x80000000) PSW |= PSW_S;
3225 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
3226
3227 trace_output (OP_REG_REG3);
3228
3229 return 4;
3230 }
3231
3232 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
3233
3234 /* bsw */
3235 int
3236 OP_34007E0 (void)
3237 {
3238 unsigned long value;
3239
3240 trace_input ("bsw", OP_REG_REG3, 0);
3241
3242 value = State.regs[ OP[ 1 ] ];
3243 value >>= 24;
3244 value |= (State.regs[ OP[ 1 ] ] << 24);
3245 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0x00ff0000);
3246 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x0000ff00);
3247
3248 State.regs[ OP[2] >> 11 ] = value;
3249
3250 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3251
3252 if (value == 0) PSW |= PSW_Z;
3253 if (value & 0x80000000) PSW |= PSW_S;
3254 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
3255
3256 trace_output (OP_REG_REG3);
3257
3258 return 4;
3259 }
3260
3261 /* bsh */
3262 int
3263 OP_34207E0 (void)
3264 {
3265 unsigned long value;
3266
3267 trace_input ("bsh", OP_REG_REG3, 0);
3268
3269 value = State.regs[ OP[ 1 ] ];
3270 value >>= 8;
3271 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0xff00ff00);
3272 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x000000ff);
3273
3274 State.regs[ OP[2] >> 11 ] = value;
3275
3276 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3277
3278 if (value == 0) PSW |= PSW_Z;
3279 if (value & 0x80000000) PSW |= PSW_S;
3280 if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
3281
3282 trace_output (OP_REG_REG3);
3283
3284 return 4;
3285 }
3286
3287 /* pushml list18 */
3288 /* ld.hu */
3289 int
3290 OP_107E0 (void)
3291 {
3292 if (OP[ 1 ] == 0)
3293 {
3294 int i;
3295
3296 trace_input ("pushml", OP_PUSHPOP3, 0);
3297
3298 /* Store the registers with lower number registers being placed at higher addresses. */
3299 for (i = 0; i < 15; i++)
3300 if ((OP[3] & (1 << type3_regs[ i ])))
3301 {
3302 SP -= 4;
3303 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
3304 }
3305
3306 if (OP[3] & (1 << 3))
3307 {
3308 SP -= 4;
3309
3310 store_mem (SP & ~ 3, 4, PSW);
3311 }
3312
3313 if (OP[3] & (1 << 19))
3314 {
3315 SP -= 8;
3316
3317 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3318 {
3319 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3320 store_mem ( SP & ~ 3, 4, FEPSW);
3321 }
3322 else
3323 {
3324 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3325 store_mem ( SP & ~ 3, 4, EIPSW);
3326 }
3327 }
3328
3329 trace_output (OP_PUSHPOP2);
3330 }
3331 else
3332 {
3333 int adr;
3334
3335 trace_input ("ld.hu", OP_LOAD32, 2);
3336
3337 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
3338 adr &= ~0x1;
3339
3340 State.regs[ OP[1] ] = load_mem (adr, 2);
3341
3342 trace_output (OP_LOAD32);
3343 }
3344
3345 return 4;
3346 }
3347
3348 /* prepare list12, imm5 */
3349 /* ld.bu */
3350 int
3351 OP_10780 (void)
3352 {
3353 if (OP[ 1 ] == 0)
3354 {
3355 int i;
3356
3357 trace_input ("prepare", OP_PUSHPOP1, 0);
3358
3359 /* Store the registers with lower number registers being placed at higher addresses. */
3360 for (i = 0; i < 12; i++)
3361 if ((OP[3] & (1 << type1_regs[ i ])))
3362 {
3363 SP -= 4;
3364 store_mem (SP, 4, State.regs[ 20 + i ]);
3365 }
3366
3367 SP -= (OP[3] & 0x3e) << 1;
3368
3369 trace_output (OP_PUSHPOP1);
3370 }
3371 else
3372 {
3373 int adr;
3374
3375 trace_input ("ld.bu", OP_LOAD32, 1);
3376
3377 adr = (State.regs[ OP[0] ]
3378 + (SEXT16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
3379
3380 State.regs[ OP[1] ] = load_mem (adr, 1);
3381
3382 trace_output (OP_LOAD32);
3383 }
3384
3385 return 4;
3386 }
3387
3388 /* prepare list12, imm5, imm32 */
3389 int
3390 OP_1B0780 (void)
3391 {
3392 int i;
3393
3394 trace_input ("prepare", OP_PUSHPOP1, 0);
3395
3396 /* Store the registers with lower number registers being placed at higher addresses. */
3397 for (i = 0; i < 12; i++)
3398 if ((OP[3] & (1 << type1_regs[ i ])))
3399 {
3400 SP -= 4;
3401 store_mem (SP, 4, State.regs[ 20 + i ]);
3402 }
3403
3404 SP -= (OP[3] & 0x3e) << 1;
3405
3406 EP = load_mem (PC + 4, 4);
3407
3408 trace_output (OP_PUSHPOP1);
3409
3410 return 8;
3411 }
3412
3413 /* prepare list12, imm5, imm16-32 */
3414 int
3415 OP_130780 (void)
3416 {
3417 int i;
3418
3419 trace_input ("prepare", OP_PUSHPOP1, 0);
3420
3421 /* Store the registers with lower number registers being placed at higher addresses. */
3422 for (i = 0; i < 12; i++)
3423 if ((OP[3] & (1 << type1_regs[ i ])))
3424 {
3425 SP -= 4;
3426 store_mem (SP, 4, State.regs[ 20 + i ]);
3427 }
3428
3429 SP -= (OP[3] & 0x3e) << 1;
3430
3431 EP = load_mem (PC + 4, 2) << 16;
3432
3433 trace_output (OP_PUSHPOP1);
3434
3435 return 6;
3436 }
3437
3438 /* prepare list12, imm5, imm16 */
3439 int
3440 OP_B0780 (void)
3441 {
3442 int i;
3443
3444 trace_input ("prepare", OP_PUSHPOP1, 0);
3445
3446 /* Store the registers with lower number registers being placed at higher addresses. */
3447 for (i = 0; i < 12; i++)
3448 if ((OP[3] & (1 << type1_regs[ i ])))
3449 {
3450 SP -= 4;
3451 store_mem (SP, 4, State.regs[ 20 + i ]);
3452 }
3453
3454 SP -= (OP[3] & 0x3e) << 1;
3455
3456 EP = SEXT16 (load_mem (PC + 4, 2));
3457
3458 trace_output (OP_PUSHPOP1);
3459
3460 return 6;
3461 }
3462
3463 /* prepare list12, imm5, sp */
3464 int
3465 OP_30780 (void)
3466 {
3467 int i;
3468
3469 trace_input ("prepare", OP_PUSHPOP1, 0);
3470
3471 /* Store the registers with lower number registers being placed at higher addresses. */
3472 for (i = 0; i < 12; i++)
3473 if ((OP[3] & (1 << type1_regs[ i ])))
3474 {
3475 SP -= 4;
3476 store_mem (SP, 4, State.regs[ 20 + i ]);
3477 }
3478
3479 SP -= (OP[3] & 0x3e) << 1;
3480
3481 EP = SP;
3482
3483 trace_output (OP_PUSHPOP1);
3484
3485 return 4;
3486 }
3487
3488 /* sld.hu */
3489 int
3490 OP_70 (void)
3491 {
3492 unsigned long result;
3493
3494 result = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
3495
3496 /* start-sanitize-v850eq */
3497 #ifdef ARCH_v850eq
3498 trace_input ("sld.h", OP_LOAD16, 2);
3499
3500 State.regs[ OP[1] ] = SEXT16 (result);
3501 #else
3502 /* end-sanitize-v850eq */
3503 trace_input ("sld.hu", OP_LOAD16, 2);
3504
3505 State.regs[ OP[1] ] = result;
3506 /* start-sanitize-v850eq */
3507 #endif
3508 /* end-sanitize-v850eq */
3509
3510 trace_output (OP_LOAD16);
3511
3512 return 2;
3513 }
3514
3515 /* cmov reg1, reg2, reg3 */
3516 int
3517 OP_32007E0 (void)
3518 {
3519 trace_input ("cmov", OP_REG_REG_REG, 0);
3520
3521 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
3522
3523 trace_output (OP_REG_REG_REG);
3524
3525 return 4;
3526 }
3527
3528 /* mul reg1, reg2, reg3 */
3529 int
3530 OP_22007E0 (void)
3531 {
3532 trace_input ("mul", OP_REG_REG_REG, 0);
3533
3534 Multiply64 (true, State.regs[ OP[0] ]);
3535
3536 trace_output (OP_REG_REG_REG);
3537
3538 return 4;
3539 }
3540
3541 /* end-sanitize-v850e */
3542 /* start-sanitize-v850eq */
3543
3544 /* popmh list18 */
3545 int
3546 OP_307F0 (void)
3547 {
3548 int i;
3549
3550 trace_input ("popmh", OP_PUSHPOP2, 0);
3551
3552 if (OP[3] & (1 << 19))
3553 {
3554 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3555 {
3556 FEPSW = load_mem ( SP & ~ 3, 4);
3557 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3558 }
3559 else
3560 {
3561 EIPSW = load_mem ( SP & ~ 3, 4);
3562 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3563 }
3564
3565 SP += 8;
3566 }
3567
3568 /* Load the registers with lower number registers being retrieved from higher addresses. */
3569 for (i = 16; i--;)
3570 if ((OP[3] & (1 << type2_regs[ i ])))
3571 {
3572 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
3573 SP += 4;
3574 }
3575
3576 trace_output (OP_PUSHPOP2);
3577
3578 return 4;
3579 }
3580
3581 /* popml lsit18 */
3582 int
3583 OP_107F0 (void)
3584 {
3585 int i;
3586
3587 trace_input ("popml", OP_PUSHPOP3, 0);
3588
3589 if (OP[3] & (1 << 19))
3590 {
3591 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3592 {
3593 FEPSW = load_mem ( SP & ~ 3, 4);
3594 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3595 }
3596 else
3597 {
3598 EIPSW = load_mem ( SP & ~ 3, 4);
3599 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3600 }
3601
3602 SP += 8;
3603 }
3604
3605 if (OP[3] & (1 << 3))
3606 {
3607 PSW = load_mem (SP & ~ 3, 4);
3608 SP += 4;
3609 }
3610
3611 /* Load the registers with lower number registers being retrieved from higher addresses. */
3612 for (i = 15; i--;)
3613 if ((OP[3] & (1 << type3_regs[ i ])))
3614 {
3615 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
3616 SP += 4;
3617 }
3618
3619 trace_output (OP_PUSHPOP2);
3620
3621 return 4;
3622 }
3623
3624 /* pushmh list18 */
3625 int
3626 OP_307E0 (void)
3627 {
3628 int i;
3629
3630 trace_input ("pushmh", OP_PUSHPOP2, 0);
3631
3632 /* Store the registers with lower number registers being placed at higher addresses. */
3633 for (i = 0; i < 16; i++)
3634 if ((OP[3] & (1 << type2_regs[ i ])))
3635 {
3636 SP -= 4;
3637 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
3638 }
3639
3640 if (OP[3] & (1 << 19))
3641 {
3642 SP -= 8;
3643
3644 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3645 {
3646 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3647 store_mem ( SP & ~ 3, 4, FEPSW);
3648 }
3649 else
3650 {
3651 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3652 store_mem ( SP & ~ 3, 4, EIPSW);
3653 }
3654 }
3655
3656 trace_output (OP_PUSHPOP2);
3657
3658 return 4;
3659 }
3660
3661 /* end-sanitize-v850eq */