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* simops.c: Include <sys/stat.h>.
[binutils-gdb.git] / sim / v850 / simops.c
1 #include <signal.h>
2 #include "v850_sim.h"
3 #include "simops.h"
4 #include "sys/syscall.h"
5 #include "bfd.h"
6 #include <errno.h>
7 #include <sys/stat.h>
8
9 enum op_types {
10 OP_UNKNOWN,
11 OP_NONE,
12 OP_TRAP,
13 OP_REG,
14 OP_REG_REG,
15 OP_REG_REG_CMP,
16 OP_REG_REG_MOVE,
17 OP_IMM_REG,
18 OP_IMM_REG_CMP,
19 OP_IMM_REG_MOVE,
20 OP_COND_BR,
21 OP_LOAD16,
22 OP_STORE16,
23 OP_LOAD32,
24 OP_STORE32,
25 OP_JUMP,
26 OP_IMM_REG_REG,
27 OP_UIMM_REG_REG,
28 OP_BIT,
29 OP_EX1,
30 OP_EX2,
31 OP_LDSR,
32 OP_STSR
33 };
34
35 #ifdef DEBUG
36 static void trace_input PARAMS ((char *name, enum op_types type, int size));
37 static void trace_output PARAMS ((enum op_types result));
38 static int init_text_p = 0;
39 static asection *text;
40 static bfd_vma text_start;
41 static bfd_vma text_end;
42 extern bfd *exec_bfd;
43
44 #ifndef SIZE_INSTRUCTION
45 #define SIZE_INSTRUCTION 6
46 #endif
47
48 #ifndef SIZE_OPERANDS
49 #define SIZE_OPERANDS 16
50 #endif
51
52 #ifndef SIZE_VALUES
53 #define SIZE_VALUES 11
54 #endif
55
56 #ifndef SIZE_LOCATION
57 #define SIZE_LOCATION 40
58 #endif
59
60 static void
61 trace_input (name, type, size)
62 char *name;
63 enum op_types type;
64 int size;
65 {
66 char buf[1024];
67 char *p;
68 uint32 values[3];
69 int num_values, i;
70 char *cond;
71 asection *s;
72 const char *filename;
73 const char *functionname;
74 unsigned int linenumber;
75
76 if ((v850_debug & DEBUG_TRACE) == 0)
77 return;
78
79 buf[0] = '\0';
80 if (!init_text_p)
81 {
82 init_text_p = 1;
83 for (s = exec_bfd->sections; s; s = s->next)
84 if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
85 {
86 text = s;
87 text_start = bfd_get_section_vma (exec_bfd, s);
88 text_end = text_start + bfd_section_size (exec_bfd, s);
89 break;
90 }
91 }
92
93 if (text && PC >= text_start && PC < text_end)
94 {
95 filename = (const char *)0;
96 functionname = (const char *)0;
97 linenumber = 0;
98 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
99 &filename, &functionname, &linenumber))
100 {
101 p = buf;
102 if (linenumber)
103 {
104 sprintf (p, "Line %5d ", linenumber);
105 p += strlen (p);
106 }
107
108 if (functionname)
109 {
110 sprintf (p, "Func %s ", functionname);
111 p += strlen (p);
112 }
113 else if (filename)
114 {
115 char *q = (char *) strrchr (filename, '/');
116 sprintf (p, "File %s ", (q) ? q+1 : filename);
117 p += strlen (p);
118 }
119
120 if (*p == ' ')
121 *p = '\0';
122 }
123 }
124
125 (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
126 (unsigned)PC,
127 SIZE_LOCATION, SIZE_LOCATION, buf,
128 SIZE_INSTRUCTION, name);
129
130 switch (type)
131 {
132 default:
133 case OP_UNKNOWN:
134 case OP_NONE:
135 strcpy (buf, "unknown");
136 break;
137
138 case OP_TRAP:
139 sprintf (buf, "%d", OP[0]);
140 break;
141
142 case OP_REG:
143 sprintf (buf, "r%d", OP[0]);
144 break;
145
146 case OP_REG_REG:
147 case OP_REG_REG_CMP:
148 case OP_REG_REG_MOVE:
149 sprintf (buf, "r%d,r%d", OP[0], OP[1]);
150 break;
151
152 case OP_IMM_REG:
153 case OP_IMM_REG_CMP:
154 case OP_IMM_REG_MOVE:
155 sprintf (buf, "%d,r%d", OP[0], OP[1]);
156 break;
157
158 case OP_COND_BR:
159 sprintf (buf, "%d", SEXT9 (OP[0]));
160 break;
161
162 case OP_LOAD16:
163 sprintf (buf, "%d[r30],r%d", OP[1] * size, OP[0]);
164 break;
165
166 case OP_STORE16:
167 sprintf (buf, "r%d,%d[r30]", OP[0], OP[1] * size);
168 break;
169
170 case OP_LOAD32:
171 sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
172 break;
173
174 case OP_STORE32:
175 sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
176 break;
177
178 case OP_JUMP:
179 sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
180 break;
181
182 case OP_IMM_REG_REG:
183 sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
184 break;
185
186 case OP_UIMM_REG_REG:
187 sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
188 break;
189
190 case OP_BIT:
191 sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
192 break;
193
194 case OP_EX1:
195 switch (OP[0] & 0xf)
196 {
197 default: cond = "?"; break;
198 case 0x0: cond = "v"; break;
199 case 0x1: cond = "c"; break;
200 case 0x2: cond = "z"; break;
201 case 0x3: cond = "nh"; break;
202 case 0x4: cond = "s"; break;
203 case 0x5: cond = "t"; break;
204 case 0x6: cond = "lt"; break;
205 case 0x7: cond = "le"; break;
206 case 0x8: cond = "nv"; break;
207 case 0x9: cond = "nc"; break;
208 case 0xa: cond = "nz"; break;
209 case 0xb: cond = "h"; break;
210 case 0xc: cond = "ns"; break;
211 case 0xd: cond = "sa"; break;
212 case 0xe: cond = "ge"; break;
213 case 0xf: cond = "gt"; break;
214 }
215
216 sprintf (buf, "%s,r%d", cond, OP[1]);
217 break;
218
219 case OP_EX2:
220 strcpy (buf, "EX2");
221 break;
222
223 case OP_LDSR:
224 case OP_STSR:
225 sprintf (buf, "r%d,s%d", OP[0], OP[1]);
226 break;
227 }
228
229 if ((v850_debug & DEBUG_VALUES) == 0)
230 {
231 (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
232 }
233 else
234 {
235 (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
236 switch (type)
237 {
238 default:
239 case OP_UNKNOWN:
240 case OP_NONE:
241 case OP_TRAP:
242 num_values = 0;
243 break;
244
245 case OP_REG:
246 case OP_REG_REG_MOVE:
247 values[0] = State.regs[OP[0]];
248 num_values = 1;
249 break;
250
251 case OP_REG_REG:
252 case OP_REG_REG_CMP:
253 values[0] = State.regs[OP[1]];
254 values[1] = State.regs[OP[0]];
255 num_values = 2;
256 break;
257
258 case OP_IMM_REG:
259 case OP_IMM_REG_CMP:
260 values[0] = SEXT5 (OP[0]);
261 values[1] = OP[1];
262 num_values = 2;
263 break;
264
265 case OP_IMM_REG_MOVE:
266 values[0] = SEXT5 (OP[0]);
267 num_values = 1;
268 break;
269
270 case OP_COND_BR:
271 values[0] = State.pc;
272 values[1] = SEXT9 (OP[0]);
273 values[2] = State.sregs[5];
274 num_values = 3;
275 break;
276
277 case OP_LOAD16:
278 values[0] = OP[1] * size;
279 values[1] = State.regs[30];
280 num_values = 2;
281 break;
282
283 case OP_STORE16:
284 values[0] = State.regs[OP[0]];
285 values[1] = OP[1] * size;
286 values[2] = State.regs[30];
287 num_values = 3;
288 break;
289
290 case OP_LOAD32:
291 values[0] = SEXT16 (OP[2]);
292 values[1] = State.regs[OP[0]];
293 num_values = 2;
294 break;
295
296 case OP_STORE32:
297 values[0] = State.regs[OP[1]];
298 values[1] = SEXT16 (OP[2]);
299 values[2] = State.regs[OP[0]];
300 num_values = 3;
301 break;
302
303 case OP_JUMP:
304 values[0] = SEXT22 (OP[0]);
305 values[1] = State.pc;
306 num_values = 2;
307 break;
308
309 case OP_IMM_REG_REG:
310 values[0] = SEXT16 (OP[0]) << size;
311 values[1] = State.regs[OP[1]];
312 num_values = 2;
313 break;
314
315 case OP_UIMM_REG_REG:
316 values[0] = (OP[0] & 0xffff) << size;
317 values[1] = State.regs[OP[1]];
318 num_values = 2;
319 break;
320
321 case OP_BIT:
322 num_values = 0;
323 break;
324
325 case OP_EX1:
326 values[0] = State.sregs[5];
327 num_values = 1;
328 break;
329
330 case OP_EX2:
331 num_values = 0;
332 break;
333
334 case OP_LDSR:
335 values[0] = State.regs[OP[0]];
336 num_values = 1;
337 break;
338
339 case OP_STSR:
340 values[0] = State.sregs[OP[1]];
341 num_values = 1;
342 }
343
344 for (i = 0; i < num_values; i++)
345 (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
346
347 while (i++ < 3)
348 (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
349 }
350 }
351
352 static void
353 trace_output (result)
354 enum op_types result;
355 {
356 if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
357 {
358 switch (result)
359 {
360 default:
361 case OP_UNKNOWN:
362 case OP_NONE:
363 case OP_TRAP:
364 case OP_REG:
365 case OP_REG_REG_CMP:
366 case OP_IMM_REG_CMP:
367 case OP_COND_BR:
368 case OP_STORE16:
369 case OP_STORE32:
370 case OP_BIT:
371 case OP_EX2:
372 break;
373
374 case OP_LOAD16:
375 case OP_STSR:
376 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
377 (unsigned long)State.regs[OP[0]]);
378 break;
379
380 case OP_REG_REG:
381 case OP_REG_REG_MOVE:
382 case OP_IMM_REG:
383 case OP_IMM_REG_MOVE:
384 case OP_LOAD32:
385 case OP_EX1:
386 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
387 (unsigned long)State.regs[OP[1]]);
388 break;
389
390 case OP_IMM_REG_REG:
391 case OP_UIMM_REG_REG:
392 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
393 (unsigned long)State.regs[OP[2]]);
394 break;
395
396 case OP_JUMP:
397 if (OP[1] != 0)
398 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
399 (unsigned long)State.regs[OP[1]]);
400 break;
401
402 case OP_LDSR:
403 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
404 (unsigned long)State.sregs[OP[1]]);
405 break;
406 }
407
408 (*v850_callback->printf_filtered) (v850_callback, "\n");
409 }
410 }
411
412 #else
413 #define trace_input(NAME, IN1, IN2)
414 #define trace_output(RESULT)
415 #endif
416
417 \f
418 /* sld.b */
419 void
420 OP_300 ()
421 {
422 unsigned int op2;
423 int result, temp;
424
425 trace_input ("sld.b", OP_LOAD16, 1);
426 temp = OP[1];
427 temp &= 0x7f;
428 op2 = temp;
429 result = load_mem (State.regs[30] + op2, 1);
430 State.regs[OP[0]] = SEXT8 (result);
431 trace_output (OP_LOAD16);
432 }
433
434 /* sld.h */
435 void
436 OP_400 ()
437 {
438 unsigned int op2;
439 int result, temp;
440
441 trace_input ("sld.h", OP_LOAD16, 2);
442 temp = OP[1];
443 temp &= 0x7f;
444 op2 = temp << 1;
445 result = load_mem (State.regs[30] + op2, 2);
446 State.regs[OP[0]] = SEXT16 (result);
447 trace_output (OP_LOAD16);
448 }
449
450 /* sld.w */
451 void
452 OP_500 ()
453 {
454 unsigned int op2;
455 int result, temp;
456
457 trace_input ("sld.w", OP_LOAD16, 4);
458 temp = OP[1];
459 temp &= 0x7e;
460 op2 = temp << 1;
461 result = load_mem (State.regs[30] + op2, 4);
462 State.regs[OP[0]] = result;
463 trace_output (OP_LOAD16);
464 }
465
466 /* sst.b */
467 void
468 OP_380 ()
469 {
470 unsigned int op0, op1;
471 int temp;
472
473 trace_input ("sst.b", OP_STORE16, 1);
474 op0 = State.regs[OP[0]];
475 temp = OP[1];
476 temp &= 0x7f;
477 op1 = temp;
478 store_mem (State.regs[30] + op1, 1, op0);
479 trace_output (OP_STORE16);
480 }
481
482 /* sst.h */
483 void
484 OP_480 ()
485 {
486 unsigned int op0, op1;
487 int temp;
488
489 trace_input ("sst.h", OP_STORE16, 2);
490 op0 = State.regs[OP[0]];
491 temp = OP[1];
492 temp &= 0x7f;
493 op1 = temp << 1;
494 store_mem (State.regs[30] + op1, 2, op0);
495 trace_output (OP_STORE16);
496 }
497
498 /* sst.w */
499 void
500 OP_501 ()
501 {
502 unsigned int op0, op1;
503 int temp;
504
505 trace_input ("sst.w", OP_STORE16, 4);
506 op0 = State.regs[OP[0]];
507 temp = OP[1];
508 temp &= 0x7e;
509 op1 = temp << 1;
510 store_mem (State.regs[30] + op1, 4, op0);
511 trace_output (OP_STORE16);
512 }
513
514 /* ld.b */
515 void
516 OP_700 ()
517 {
518 unsigned int op0, op2;
519 int result, temp;
520
521 trace_input ("ld.b", OP_LOAD32, 1);
522 op0 = State.regs[OP[0]];
523 temp = SEXT16 (OP[2]);
524 op2 = temp;
525 result = load_mem (op0 + op2, 1);
526 State.regs[OP[1]] = SEXT8 (result);
527 trace_output (OP_LOAD32);
528 }
529
530 /* ld.h */
531 void
532 OP_720 ()
533 {
534 unsigned int op0, op2;
535 int result, temp;
536
537 trace_input ("ld.h", OP_LOAD32, 2);
538 op0 = State.regs[OP[0]];
539 temp = SEXT16 (OP[2]);
540 temp &= ~0x1;
541 op2 = temp;
542 result = load_mem (op0 + op2, 2);
543 State.regs[OP[1]] = SEXT16 (result);
544 trace_output (OP_LOAD32);
545 }
546
547 /* ld.w */
548 void
549 OP_10720 ()
550 {
551 unsigned int op0, op2;
552 int result, temp;
553
554 trace_input ("ld.w", OP_LOAD32, 4);
555 op0 = State.regs[OP[0]];
556 temp = SEXT16 (OP[2]);
557 temp &= ~0x1;
558 op2 = temp;
559 result = load_mem (op0 + op2, 4);
560 State.regs[OP[1]] = result;
561 trace_output (OP_LOAD32);
562 }
563
564 /* st.b */
565 void
566 OP_740 ()
567 {
568 unsigned int op0, op1, op2;
569 int temp;
570
571 trace_input ("st.b", OP_STORE32, 1);
572 op0 = State.regs[OP[0]];
573 op1 = State.regs[OP[1]];
574 temp = SEXT16 (OP[2]);
575 op2 = temp;
576 store_mem (op0 + op2, 1, op1);
577 trace_output (OP_STORE32);
578 }
579
580 /* st.h */
581 void
582 OP_760 ()
583 {
584 unsigned int op0, op1, op2;
585 int temp;
586
587 trace_input ("st.h", OP_STORE32, 2);
588 op0 = State.regs[OP[0]];
589 op1 = State.regs[OP[1]];
590 temp = SEXT16 (OP[2] & ~0x1);
591 op2 = temp;
592 store_mem (op0 + op2, 2, op1);
593 trace_output (OP_STORE32);
594 }
595
596 /* st.w */
597 void
598 OP_10760 ()
599 {
600 unsigned int op0, op1, op2;
601 int temp;
602
603 trace_input ("st.w", OP_STORE32, 4);
604 op0 = State.regs[OP[0]];
605 op1 = State.regs[OP[1]];
606 temp = SEXT16 (OP[2] & ~0x1);
607 op2 = temp;
608 store_mem (op0 + op2, 4, op1);
609 trace_output (OP_STORE32);
610 }
611
612 /* bv disp9 */
613 void
614 OP_580 ()
615 {
616 unsigned int psw;
617 int op0;
618
619 trace_input ("bv", OP_COND_BR, 0);
620 op0 = SEXT9 (OP[0]);
621 psw = State.sregs[5];
622
623 if ((psw & PSW_OV) != 0)
624 State.pc += op0;
625 else
626 State.pc += 2;
627 trace_output (OP_COND_BR);
628 }
629
630 /* bl disp9 */
631 void
632 OP_581 ()
633 {
634 unsigned int psw;
635 int op0;
636
637 trace_input ("bl", OP_COND_BR, 0);
638 op0 = SEXT9 (OP[0]);
639 psw = State.sregs[5];
640
641 if ((psw & PSW_CY) != 0)
642 State.pc += op0;
643 else
644 State.pc += 2;
645 trace_output (OP_COND_BR);
646 }
647
648 /* be disp9 */
649 void
650 OP_582 ()
651 {
652 unsigned int psw;
653 int op0;
654
655 trace_input ("be", OP_COND_BR, 0);
656 op0 = SEXT9 (OP[0]);
657 psw = State.sregs[5];
658
659 if ((psw & PSW_Z) != 0)
660 State.pc += op0;
661 else
662 State.pc += 2;
663 trace_output (OP_COND_BR);
664 }
665
666 /* bnh disp 9*/
667 void
668 OP_583 ()
669 {
670 unsigned int psw;
671 int op0;
672
673 trace_input ("bnh", OP_COND_BR, 0);
674 op0 = SEXT9 (OP[0]);
675 psw = State.sregs[5];
676
677 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
678 State.pc += op0;
679 else
680 State.pc += 2;
681 trace_output (OP_COND_BR);
682 }
683
684 /* bn disp9 */
685 void
686 OP_584 ()
687 {
688 unsigned int psw;
689 int op0;
690
691 trace_input ("bn", OP_COND_BR, 0);
692 op0 = SEXT9 (OP[0]);
693 psw = State.sregs[5];
694
695 if ((psw & PSW_S) != 0)
696 State.pc += op0;
697 else
698 State.pc += 2;
699 trace_output (OP_COND_BR);
700 }
701
702 /* br disp9 */
703 void
704 OP_585 ()
705 {
706 unsigned int psw;
707 int op0;
708
709 trace_input ("br", OP_COND_BR, 0);
710 op0 = SEXT9 (OP[0]);
711 State.pc += op0;
712 trace_output (OP_COND_BR);
713 }
714
715 /* blt disp9 */
716 void
717 OP_586 ()
718 {
719 unsigned int psw;
720 int op0;
721
722 trace_input ("blt", OP_COND_BR, 0);
723 op0 = SEXT9 (OP[0]);
724 psw = State.sregs[5];
725
726 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
727 State.pc += op0;
728 else
729 State.pc += 2;
730 trace_output (OP_COND_BR);
731 }
732
733 /* ble disp9 */
734 void
735 OP_587 ()
736 {
737 unsigned int psw;
738 int op0;
739
740 trace_input ("ble", OP_COND_BR, 0);
741 op0 = SEXT9 (OP[0]);
742 psw = State.sregs[5];
743
744 if ((((psw & PSW_Z) != 0)
745 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
746 State.pc += op0;
747 else
748 State.pc += 2;
749 trace_output (OP_COND_BR);
750 }
751
752 /* bnv disp9 */
753 void
754 OP_588 ()
755 {
756 unsigned int psw;
757 int op0;
758
759 trace_input ("bnv", OP_COND_BR, 0);
760 op0 = SEXT9 (OP[0]);
761 psw = State.sregs[5];
762
763 if ((psw & PSW_OV) == 0)
764 State.pc += op0;
765 else
766 State.pc += 2;
767 trace_output (OP_COND_BR);
768 }
769
770 /* bnl disp9 */
771 void
772 OP_589 ()
773 {
774 unsigned int psw;
775 int op0;
776
777 trace_input ("bnl", OP_COND_BR, 0);
778 op0 = SEXT9 (OP[0]);
779 psw = State.sregs[5];
780
781 if ((psw & PSW_CY) == 0)
782 State.pc += op0;
783 else
784 State.pc += 2;
785 trace_output (OP_COND_BR);
786 }
787
788 /* bne disp9 */
789 void
790 OP_58A ()
791 {
792 unsigned int psw;
793 int op0;
794
795 trace_input ("bne", OP_COND_BR, 0);
796 op0 = SEXT9 (OP[0]);
797 psw = State.sregs[5];
798
799 if ((psw & PSW_Z) == 0)
800 State.pc += op0;
801 else
802 State.pc += 2;
803 trace_output (OP_COND_BR);
804 }
805
806 /* bh disp9 */
807 void
808 OP_58B ()
809 {
810 unsigned int psw;
811 int op0;
812
813 trace_input ("bh", OP_COND_BR, 0);
814 op0 = SEXT9 (OP[0]);
815 psw = State.sregs[5];
816
817 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
818 State.pc += op0;
819 else
820 State.pc += 2;
821 trace_output (OP_COND_BR);
822 }
823
824 /* bp disp9 */
825 void
826 OP_58C ()
827 {
828 unsigned int psw;
829 int op0;
830
831 trace_input ("bp", OP_COND_BR, 0);
832 op0 = SEXT9 (OP[0]);
833 psw = State.sregs[5];
834
835 if ((psw & PSW_S) == 0)
836 State.pc += op0;
837 else
838 State.pc += 2;
839 trace_output (OP_COND_BR);
840 }
841
842 /* bsa disp9 */
843 void
844 OP_58D ()
845 {
846 unsigned int psw;
847 int op0;
848
849 trace_input ("bsa", OP_COND_BR, 0);
850 op0 = SEXT9 (OP[0]);
851 psw = State.sregs[5];
852
853 if ((psw & PSW_SAT) != 0)
854 State.pc += op0;
855 else
856 State.pc += 2;
857 trace_output (OP_COND_BR);
858 }
859
860 /* bge disp9 */
861 void
862 OP_58E ()
863 {
864 unsigned int psw;
865 int op0;
866
867 trace_input ("bge", OP_COND_BR, 0);
868 op0 = SEXT9 (OP[0]);
869 psw = State.sregs[5];
870
871 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
872 State.pc += op0;
873 else
874 State.pc += 2;
875 trace_output (OP_COND_BR);
876 }
877
878 /* bgt disp9 */
879 void
880 OP_58F ()
881 {
882 unsigned int psw;
883 int op0;
884
885 trace_input ("bgt", OP_COND_BR, 0);
886 op0 = SEXT9 (OP[0]);
887 psw = State.sregs[5];
888
889 if ((((psw & PSW_Z) != 0)
890 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
891 State.pc += op0;
892 else
893 State.pc += 2;
894 trace_output (OP_COND_BR);
895 }
896
897 /* jmp [reg1] */
898 void
899 OP_60 ()
900 {
901 /* interp.c will bump this by +2, so correct for it here. */
902 trace_input ("jmp", OP_REG, 0);
903 State.pc = State.regs[OP[0]] - 2;
904 trace_output (OP_REG);
905 }
906
907 /* jarl disp22, reg */
908 void
909 OP_780 ()
910 {
911 unsigned int op0, opc;
912 int temp;
913
914 trace_input ("jarl", OP_JUMP, 0);
915 temp = SEXT22 (OP[0]);
916 op0 = temp;
917 opc = State.pc;
918
919 State.pc += temp;
920
921 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
922 if (OP[1] != 0)
923 State.regs[OP[1]] = opc + 4;
924 trace_output (OP_JUMP);
925 }
926
927 /* add reg, reg */
928 void
929 OP_1C0 ()
930 {
931 unsigned int op0, op1, result, z, s, cy, ov;
932
933 trace_input ("add", OP_REG_REG, 0);
934 /* Compute the result. */
935 op0 = State.regs[OP[0]];
936 op1 = State.regs[OP[1]];
937 result = op0 + op1;
938
939 /* Compute the condition codes. */
940 z = (result == 0);
941 s = (result & 0x80000000);
942 cy = (result < op0 || result < op1);
943 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
944 && (op0 & 0x80000000) != (result & 0x80000000));
945
946 /* Store the result and condition codes. */
947 State.regs[OP[1]] = result;
948 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
949 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
950 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
951 trace_output (OP_REG_REG);
952 }
953
954 /* add sign_extend(imm5), reg */
955 void
956 OP_240 ()
957 {
958 unsigned int op0, op1, result, z, s, cy, ov;
959 int temp;
960
961 trace_input ("add", OP_IMM_REG, 0);
962
963 /* Compute the result. */
964 temp = SEXT5 (OP[0]);
965 op0 = temp;
966 op1 = State.regs[OP[1]];
967 result = op0 + op1;
968
969 /* Compute the condition codes. */
970 z = (result == 0);
971 s = (result & 0x80000000);
972 cy = (result < op0 || result < op1);
973 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
974 && (op0 & 0x80000000) != (result & 0x80000000));
975
976 /* Store the result and condition codes. */
977 State.regs[OP[1]] = result;
978 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
979 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
980 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
981 trace_output (OP_IMM_REG);
982 }
983
984 /* addi sign_extend(imm16), reg, reg */
985 void
986 OP_600 ()
987 {
988 unsigned int op0, op1, result, z, s, cy, ov;
989 int temp;
990
991 trace_input ("addi", OP_IMM_REG_REG, 0);
992
993 /* Compute the result. */
994 temp = SEXT16 (OP[0]);
995 op0 = temp;
996 op1 = State.regs[OP[1]];
997 result = op0 + op1;
998
999 /* Compute the condition codes. */
1000 z = (result == 0);
1001 s = (result & 0x80000000);
1002 cy = (result < op0 || result < op1);
1003 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1004 && (op0 & 0x80000000) != (result & 0x80000000));
1005
1006 /* Store the result and condition codes. */
1007 State.regs[OP[2]] = result;
1008 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1009 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1010 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1011 trace_output (OP_IMM_REG_REG);
1012 }
1013
1014 /* sub reg1, reg2 */
1015 void
1016 OP_1A0 ()
1017 {
1018 unsigned int op0, op1, result, z, s, cy, ov;
1019
1020 trace_input ("sub", OP_REG_REG, 0);
1021 /* Compute the result. */
1022 op0 = State.regs[OP[0]];
1023 op1 = State.regs[OP[1]];
1024 result = op1 - op0;
1025
1026 /* Compute the condition codes. */
1027 z = (result == 0);
1028 s = (result & 0x80000000);
1029 cy = (op1 < op0);
1030 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1031 && (op1 & 0x80000000) != (result & 0x80000000));
1032
1033 /* Store the result and condition codes. */
1034 State.regs[OP[1]] = result;
1035 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1036 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1037 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1038 trace_output (OP_REG_REG);
1039 }
1040
1041 /* subr reg1, reg2 */
1042 void
1043 OP_180 ()
1044 {
1045 unsigned int op0, op1, result, z, s, cy, ov;
1046
1047 trace_input ("subr", OP_REG_REG, 0);
1048 /* Compute the result. */
1049 op0 = State.regs[OP[0]];
1050 op1 = State.regs[OP[1]];
1051 result = op0 - op1;
1052
1053 /* Compute the condition codes. */
1054 z = (result == 0);
1055 s = (result & 0x80000000);
1056 cy = (op0 < op1);
1057 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1058 && (op0 & 0x80000000) != (result & 0x80000000));
1059
1060 /* Store the result and condition codes. */
1061 State.regs[OP[1]] = result;
1062 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1063 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1064 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1065 trace_output (OP_REG_REG);
1066 }
1067
1068 /* mulh reg1, reg2 */
1069 void
1070 OP_E0 ()
1071 {
1072 trace_input ("mulh", OP_REG_REG, 0);
1073 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
1074 * (State.regs[OP[0]] & 0xffff));
1075 trace_output (OP_REG_REG);
1076 }
1077
1078 /* mulh sign_extend(imm5), reg2
1079
1080 Condition codes */
1081 void
1082 OP_2E0 ()
1083 {
1084 int value = SEXT5 (OP[0]);
1085
1086 trace_input ("mulh", OP_IMM_REG, 0);
1087 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
1088 trace_output (OP_IMM_REG);
1089 }
1090
1091 /* mulhi imm16, reg1, reg2 */
1092 void
1093 OP_6E0 ()
1094 {
1095 int value = OP[0] & 0xffff;
1096
1097 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1098 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
1099 trace_output (OP_IMM_REG_REG);
1100 }
1101
1102 /* divh reg1, reg2 */
1103 void
1104 OP_40 ()
1105 {
1106 unsigned int op0, op1, result, ov, s, z;
1107 int temp;
1108
1109 trace_input ("divh", OP_REG_REG, 0);
1110
1111 /* Compute the result. */
1112 temp = SEXT16 (State.regs[OP[0]]);
1113 op0 = temp;
1114 op1 = State.regs[OP[1]];
1115
1116 if (op0 == 0xffffffff && op1 == 0x80000000)
1117 {
1118 result = 0x80000000;
1119 ov = 1;
1120 }
1121 else if (op0 != 0)
1122 {
1123 result = op1 / op0;
1124 ov = 0;
1125 }
1126 else
1127 {
1128 result = 0x0;
1129 ov = 1;
1130 }
1131
1132 /* Compute the condition codes. */
1133 z = (result == 0);
1134 s = (result & 0x80000000);
1135
1136 /* Store the result and condition codes. */
1137 State.regs[OP[1]] = result;
1138 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1139 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1140 | (ov ? PSW_OV : 0));
1141 trace_output (OP_REG_REG);
1142 }
1143
1144 /* cmp reg, reg */
1145 void
1146 OP_1E0 ()
1147 {
1148 unsigned int op0, op1, result, z, s, cy, ov;
1149
1150 trace_input ("cmp", OP_REG_REG_CMP, 0);
1151 /* Compute the result. */
1152 op0 = State.regs[OP[0]];
1153 op1 = State.regs[OP[1]];
1154 result = op1 - op0;
1155
1156 /* Compute the condition codes. */
1157 z = (result == 0);
1158 s = (result & 0x80000000);
1159 cy = (op1 < op0);
1160 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1161 && (op1 & 0x80000000) != (result & 0x80000000));
1162
1163 /* Set condition codes. */
1164 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1165 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1166 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1167 trace_output (OP_REG_REG_CMP);
1168 }
1169
1170 /* cmp sign_extend(imm5), reg */
1171 void
1172 OP_260 ()
1173 {
1174 unsigned int op0, op1, result, z, s, cy, ov;
1175 int temp;
1176
1177 /* Compute the result. */
1178 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1179 temp = SEXT5 (OP[0]);
1180 op0 = temp;
1181 op1 = State.regs[OP[1]];
1182 result = op1 - op0;
1183
1184 /* Compute the condition codes. */
1185 z = (result == 0);
1186 s = (result & 0x80000000);
1187 cy = (op1 < op0);
1188 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1189 && (op1 & 0x80000000) != (result & 0x80000000));
1190
1191 /* Set condition codes. */
1192 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1193 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1194 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1195 trace_output (OP_IMM_REG_CMP);
1196 }
1197
1198 /* setf cccc,reg2 */
1199 void
1200 OP_7E0 ()
1201 {
1202 /* Hack alert. We turn off a bit in op0 since we really only
1203 wanted 4 bits. */
1204 unsigned int op0, psw, result = 0;
1205
1206 trace_input ("setf", OP_EX1, 0);
1207 op0 = OP[0] & 0xf;
1208 psw = State.sregs[5];
1209
1210 switch (op0)
1211 {
1212 case 0x0:
1213 result = ((psw & PSW_OV) != 0);
1214 break;
1215 case 0x1:
1216 result = ((psw & PSW_CY) != 0);
1217 break;
1218 case 0x2:
1219 result = ((psw & PSW_Z) != 0);
1220 break;
1221 case 0x3:
1222 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
1223 break;
1224 case 0x4:
1225 result = ((psw & PSW_S) != 0);
1226 break;
1227 case 0x5:
1228 result = 1;
1229 break;
1230 case 0x6:
1231 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
1232 break;
1233 case 0x7:
1234 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
1235 || ((psw & PSW_Z) != 0)) != 0);
1236 break;
1237 case 0x8:
1238 result = ((psw & PSW_OV) == 0);
1239 break;
1240 case 0x9:
1241 result = ((psw & PSW_CY) == 0);
1242 break;
1243 case 0xa:
1244 result = ((psw & PSW_Z) == 0);
1245 break;
1246 case 0xb:
1247 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
1248 break;
1249 case 0xc:
1250 result = ((psw & PSW_S) == 0);
1251 break;
1252 case 0xd:
1253 result = ((psw & PSW_SAT) != 0);
1254 break;
1255 case 0xe:
1256 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
1257 break;
1258 case 0xf:
1259 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
1260 || ((psw & PSW_Z) != 0)) == 0);
1261 break;
1262 }
1263
1264 State.regs[OP[1]] = result;
1265 trace_output (OP_EX1);
1266 }
1267
1268 /* satadd reg,reg */
1269 void
1270 OP_C0 ()
1271 {
1272 unsigned int op0, op1, result, z, s, cy, ov, sat;
1273
1274 trace_input ("satadd", OP_REG_REG, 0);
1275 /* Compute the result. */
1276 op0 = State.regs[OP[0]];
1277 op1 = State.regs[OP[1]];
1278 result = op0 + op1;
1279
1280 /* Compute the condition codes. */
1281 z = (result == 0);
1282 s = (result & 0x80000000);
1283 cy = (result < op0 || result < op1);
1284 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1285 && (op0 & 0x80000000) != (result & 0x80000000));
1286 sat = ov;
1287
1288 /* Store the result and condition codes. */
1289 State.regs[OP[1]] = result;
1290 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1291 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1292 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1293 | (sat ? PSW_SAT : 0));
1294
1295 /* Handle saturated results. */
1296 if (sat && s)
1297 State.regs[OP[1]] = 0x80000000;
1298 else if (sat)
1299 State.regs[OP[1]] = 0x7fffffff;
1300 trace_output (OP_REG_REG);
1301 }
1302
1303 /* satadd sign_extend(imm5), reg */
1304 void
1305 OP_220 ()
1306 {
1307 unsigned int op0, op1, result, z, s, cy, ov, sat;
1308
1309 int temp;
1310
1311 trace_input ("satadd", OP_IMM_REG, 0);
1312
1313 /* Compute the result. */
1314 temp = SEXT5 (OP[0]);
1315 op0 = temp;
1316 op1 = State.regs[OP[1]];
1317 result = op0 + op1;
1318
1319 /* Compute the condition codes. */
1320 z = (result == 0);
1321 s = (result & 0x80000000);
1322 cy = (result < op0 || result < op1);
1323 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1324 && (op0 & 0x80000000) != (result & 0x80000000));
1325 sat = ov;
1326
1327 /* Store the result and condition codes. */
1328 State.regs[OP[1]] = result;
1329 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1330 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1331 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1332 | (sat ? PSW_SAT : 0));
1333
1334 /* Handle saturated results. */
1335 if (sat && s)
1336 State.regs[OP[1]] = 0x80000000;
1337 else if (sat)
1338 State.regs[OP[1]] = 0x7fffffff;
1339 trace_output (OP_IMM_REG);
1340 }
1341
1342 /* satsub reg1, reg2 */
1343 void
1344 OP_A0 ()
1345 {
1346 unsigned int op0, op1, result, z, s, cy, ov, sat;
1347
1348 trace_input ("satsub", OP_REG_REG, 0);
1349
1350 /* Compute the result. */
1351 op0 = State.regs[OP[0]];
1352 op1 = State.regs[OP[1]];
1353 result = op1 - op0;
1354
1355 /* Compute the condition codes. */
1356 z = (result == 0);
1357 s = (result & 0x80000000);
1358 cy = (op1 < op0);
1359 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1360 && (op1 & 0x80000000) != (result & 0x80000000));
1361 sat = ov;
1362
1363 /* Store the result and condition codes. */
1364 State.regs[OP[1]] = result;
1365 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1366 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1367 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1368 | (sat ? PSW_SAT : 0));
1369
1370 /* Handle saturated results. */
1371 if (sat && s)
1372 State.regs[OP[1]] = 0x80000000;
1373 else if (sat)
1374 State.regs[OP[1]] = 0x7fffffff;
1375 trace_output (OP_REG_REG);
1376 }
1377
1378 /* satsubi sign_extend(imm16), reg */
1379 void
1380 OP_660 ()
1381 {
1382 unsigned int op0, op1, result, z, s, cy, ov, sat;
1383 int temp;
1384
1385 trace_input ("satsubi", OP_IMM_REG, 0);
1386
1387 /* Compute the result. */
1388 temp = SEXT16 (OP[0]);
1389 op0 = temp;
1390 op1 = State.regs[OP[1]];
1391 result = op1 - op0;
1392
1393 /* Compute the condition codes. */
1394 z = (result == 0);
1395 s = (result & 0x80000000);
1396 cy = (op1 < op0);
1397 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1398 && (op1 & 0x80000000) != (result & 0x80000000));
1399 sat = ov;
1400
1401 /* Store the result and condition codes. */
1402 State.regs[OP[1]] = result;
1403 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1404 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1405 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1406 | (sat ? PSW_SAT : 0));
1407
1408 /* Handle saturated results. */
1409 if (sat && s)
1410 State.regs[OP[1]] = 0x80000000;
1411 else if (sat)
1412 State.regs[OP[1]] = 0x7fffffff;
1413 trace_output (OP_IMM_REG);
1414 }
1415
1416 /* satsubr reg,reg */
1417 void
1418 OP_80 ()
1419 {
1420 unsigned int op0, op1, result, z, s, cy, ov, sat;
1421
1422 trace_input ("satsubr", OP_REG_REG, 0);
1423
1424 /* Compute the result. */
1425 op0 = State.regs[OP[0]];
1426 op1 = State.regs[OP[1]];
1427 result = op0 - op1;
1428
1429 /* Compute the condition codes. */
1430 z = (result == 0);
1431 s = (result & 0x80000000);
1432 cy = (result < op0);
1433 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1434 && (op1 & 0x80000000) != (result & 0x80000000));
1435 sat = ov;
1436
1437 /* Store the result and condition codes. */
1438 State.regs[OP[1]] = result;
1439 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1440 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1441 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1442 | (sat ? PSW_SAT : 0));
1443
1444 /* Handle saturated results. */
1445 if (sat && s)
1446 State.regs[OP[1]] = 0x80000000;
1447 else if (sat)
1448 State.regs[OP[1]] = 0x7fffffff;
1449 trace_output (OP_REG_REG);
1450 }
1451
1452 /* tst reg,reg */
1453 void
1454 OP_160 ()
1455 {
1456 unsigned int op0, op1, result, z, s;
1457
1458 trace_input ("tst", OP_REG_REG_CMP, 0);
1459
1460 /* Compute the result. */
1461 op0 = State.regs[OP[0]];
1462 op1 = State.regs[OP[1]];
1463 result = op0 & op1;
1464
1465 /* Compute the condition codes. */
1466 z = (result == 0);
1467 s = (result & 0x80000000);
1468
1469 /* Store the condition codes. */
1470 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1471 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1472 trace_output (OP_REG_REG_CMP);
1473 }
1474
1475 /* mov reg, reg */
1476 void
1477 OP_0 ()
1478 {
1479 trace_input ("mov", OP_REG_REG_MOVE, 0);
1480 State.regs[OP[1]] = State.regs[OP[0]];
1481 trace_output (OP_REG_REG_MOVE);
1482 }
1483
1484 /* mov sign_extend(imm5), reg */
1485 void
1486 OP_200 ()
1487 {
1488 int value = SEXT5 (OP[0]);
1489
1490 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1491 State.regs[OP[1]] = value;
1492 trace_output (OP_IMM_REG_MOVE);
1493 }
1494
1495 /* movea sign_extend(imm16), reg, reg */
1496
1497 void
1498 OP_620 ()
1499 {
1500 int value = SEXT16 (OP[0]);
1501
1502 trace_input ("movea", OP_IMM_REG_REG, 0);
1503 State.regs[OP[2]] = State.regs[OP[1]] + value;
1504 trace_output (OP_IMM_REG_REG);
1505 }
1506
1507 /* movhi imm16, reg, reg */
1508 void
1509 OP_640 ()
1510 {
1511 uint32 value = (OP[0] & 0xffff) << 16;
1512
1513 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1514 State.regs[OP[2]] = State.regs[OP[1]] + value;
1515 trace_output (OP_UIMM_REG_REG);
1516 }
1517
1518 /* sar zero_extend(imm5),reg1 */
1519 void
1520 OP_2A0 ()
1521 {
1522 unsigned int op0, op1, result, z, s, cy;
1523
1524 trace_input ("sar", OP_IMM_REG, 0);
1525 op0 = OP[0] & 0x1f;
1526 op1 = State.regs[OP[1]];
1527 result = (signed)op1 >> op0;
1528
1529 /* Compute the condition codes. */
1530 z = (result == 0);
1531 s = (result & 0x80000000);
1532 cy = (op1 & (1 << (op0 - 1)));
1533
1534 /* Store the result and condition codes. */
1535 State.regs[OP[1]] = result;
1536 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1537 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1538 | (cy ? PSW_CY : 0));
1539 trace_output (OP_IMM_REG);
1540 }
1541
1542 /* sar reg1, reg2 */
1543 void
1544 OP_A007E0 ()
1545 {
1546 unsigned int op0, op1, result, z, s, cy;
1547
1548 trace_input ("sar", OP_REG_REG, 0);
1549 op0 = State.regs[OP[0]] & 0x1f;
1550 op1 = State.regs[OP[1]];
1551 result = (signed)op1 >> op0;
1552
1553 /* Compute the condition codes. */
1554 z = (result == 0);
1555 s = (result & 0x80000000);
1556 cy = (op1 & (1 << (op0 - 1)));
1557
1558 /* Store the result and condition codes. */
1559 State.regs[OP[1]] = result;
1560 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1561 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1562 | (cy ? PSW_CY : 0));
1563 trace_output (OP_REG_REG);
1564 }
1565
1566 /* shl zero_extend(imm5),reg1 */
1567 void
1568 OP_2C0 ()
1569 {
1570 unsigned int op0, op1, result, z, s, cy;
1571
1572 trace_input ("shl", OP_IMM_REG, 0);
1573 op0 = OP[0] & 0x1f;
1574 op1 = State.regs[OP[1]];
1575 result = op1 << op0;
1576
1577 /* Compute the condition codes. */
1578 z = (result == 0);
1579 s = (result & 0x80000000);
1580 cy = (op1 & (1 << (32 - op0)));
1581
1582 /* Store the result and condition codes. */
1583 State.regs[OP[1]] = result;
1584 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1585 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1586 | (cy ? PSW_CY : 0));
1587 trace_output (OP_IMM_REG);
1588 }
1589
1590 /* shl reg1, reg2 */
1591 void
1592 OP_C007E0 ()
1593 {
1594 unsigned int op0, op1, result, z, s, cy;
1595
1596 trace_input ("shl", OP_REG_REG, 0);
1597 op0 = State.regs[OP[0]] & 0x1f;
1598 op1 = State.regs[OP[1]];
1599 result = op1 << op0;
1600
1601 /* Compute the condition codes. */
1602 z = (result == 0);
1603 s = (result & 0x80000000);
1604 cy = (op1 & (1 << (32 - op0)));
1605
1606 /* Store the result and condition codes. */
1607 State.regs[OP[1]] = result;
1608 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1609 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1610 | (cy ? PSW_CY : 0));
1611 trace_output (OP_REG_REG);
1612 }
1613
1614 /* shr zero_extend(imm5),reg1 */
1615 void
1616 OP_280 ()
1617 {
1618 unsigned int op0, op1, result, z, s, cy;
1619
1620 trace_input ("shr", OP_IMM_REG, 0);
1621 op0 = OP[0] & 0x1f;
1622 op1 = State.regs[OP[1]];
1623 result = op1 >> op0;
1624
1625 /* Compute the condition codes. */
1626 z = (result == 0);
1627 s = (result & 0x80000000);
1628 cy = (op1 & (1 << (op0 - 1)));
1629
1630 /* Store the result and condition codes. */
1631 State.regs[OP[1]] = result;
1632 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1633 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1634 | (cy ? PSW_CY : 0));
1635 trace_output (OP_IMM_REG);
1636 }
1637
1638 /* shr reg1, reg2 */
1639 void
1640 OP_8007E0 ()
1641 {
1642 unsigned int op0, op1, result, z, s, cy;
1643
1644 trace_input ("shr", OP_REG_REG, 0);
1645 op0 = State.regs[OP[0]] & 0x1f;
1646 op1 = State.regs[OP[1]];
1647 result = op1 >> op0;
1648
1649 /* Compute the condition codes. */
1650 z = (result == 0);
1651 s = (result & 0x80000000);
1652 cy = (op1 & (1 << (op0 - 1)));
1653
1654 /* Store the result and condition codes. */
1655 State.regs[OP[1]] = result;
1656 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1657 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1658 | (cy ? PSW_CY : 0));
1659 trace_output (OP_REG_REG);
1660 }
1661
1662 /* or reg, reg */
1663 void
1664 OP_100 ()
1665 {
1666 unsigned int op0, op1, result, z, s;
1667
1668 trace_input ("or", OP_REG_REG, 0);
1669
1670 /* Compute the result. */
1671 op0 = State.regs[OP[0]];
1672 op1 = State.regs[OP[1]];
1673 result = op0 | op1;
1674
1675 /* Compute the condition codes. */
1676 z = (result == 0);
1677 s = (result & 0x80000000);
1678
1679 /* Store the result and condition codes. */
1680 State.regs[OP[1]] = result;
1681 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1682 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1683 trace_output (OP_REG_REG);
1684 }
1685
1686 /* ori zero_extend(imm16), reg, reg */
1687 void
1688 OP_680 ()
1689 {
1690 unsigned int op0, op1, result, z, s;
1691
1692 trace_input ("ori", OP_UIMM_REG_REG, 0);
1693 op0 = OP[0] & 0xffff;
1694 op1 = State.regs[OP[1]];
1695 result = op0 | op1;
1696
1697 /* Compute the condition codes. */
1698 z = (result == 0);
1699 s = (result & 0x80000000);
1700
1701 /* Store the result and condition codes. */
1702 State.regs[OP[2]] = result;
1703 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1704 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1705 trace_output (OP_UIMM_REG_REG);
1706 }
1707
1708 /* and reg, reg */
1709 void
1710 OP_140 ()
1711 {
1712 unsigned int op0, op1, result, z, s;
1713
1714 trace_input ("and", OP_REG_REG, 0);
1715
1716 /* Compute the result. */
1717 op0 = State.regs[OP[0]];
1718 op1 = State.regs[OP[1]];
1719 result = op0 & op1;
1720
1721 /* Compute the condition codes. */
1722 z = (result == 0);
1723 s = (result & 0x80000000);
1724
1725 /* Store the result and condition codes. */
1726 State.regs[OP[1]] = result;
1727 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1728 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1729 trace_output (OP_REG_REG);
1730 }
1731
1732 /* andi zero_extend(imm16), reg, reg */
1733 void
1734 OP_6C0 ()
1735 {
1736 unsigned int op0, op1, result, z;
1737
1738 trace_input ("andi", OP_UIMM_REG_REG, 0);
1739 op0 = OP[0] & 0xffff;
1740 op1 = State.regs[OP[1]];
1741 result = op0 & op1;
1742
1743 /* Compute the condition codes. */
1744 z = (result == 0);
1745
1746 /* Store the result and condition codes. */
1747 State.regs[OP[2]] = result;
1748 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1749 State.sregs[5] |= (z ? PSW_Z : 0);
1750 trace_output (OP_UIMM_REG_REG);
1751 }
1752
1753 /* xor reg, reg */
1754 void
1755 OP_120 ()
1756 {
1757 unsigned int op0, op1, result, z, s;
1758
1759 trace_input ("xor", OP_REG_REG, 0);
1760
1761 /* Compute the result. */
1762 op0 = State.regs[OP[0]];
1763 op1 = State.regs[OP[1]];
1764 result = op0 ^ op1;
1765
1766 /* Compute the condition codes. */
1767 z = (result == 0);
1768 s = (result & 0x80000000);
1769
1770 /* Store the result and condition codes. */
1771 State.regs[OP[1]] = result;
1772 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1773 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1774 trace_output (OP_REG_REG);
1775 }
1776
1777 /* xori zero_extend(imm16), reg, reg */
1778 void
1779 OP_6A0 ()
1780 {
1781 unsigned int op0, op1, result, z, s;
1782
1783 trace_input ("xori", OP_UIMM_REG_REG, 0);
1784 op0 = OP[0] & 0xffff;
1785 op1 = State.regs[OP[1]];
1786 result = op0 ^ op1;
1787
1788 /* Compute the condition codes. */
1789 z = (result == 0);
1790 s = (result & 0x80000000);
1791
1792 /* Store the result and condition codes. */
1793 State.regs[OP[2]] = result;
1794 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1795 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1796 trace_output (OP_UIMM_REG_REG);
1797 }
1798
1799 /* not reg1, reg2 */
1800 void
1801 OP_20 ()
1802 {
1803 unsigned int op0, result, z, s;
1804
1805 trace_input ("not", OP_REG_REG_MOVE, 0);
1806 /* Compute the result. */
1807 op0 = State.regs[OP[0]];
1808 result = ~op0;
1809
1810 /* Compute the condition codes. */
1811 z = (result == 0);
1812 s = (result & 0x80000000);
1813
1814 /* Store the result and condition codes. */
1815 State.regs[OP[1]] = result;
1816 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1817 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1818 trace_output (OP_REG_REG_MOVE);
1819 }
1820
1821 /* set1 */
1822 void
1823 OP_7C0 ()
1824 {
1825 unsigned int op0, op1, op2;
1826 int temp;
1827
1828 trace_input ("set1", OP_BIT, 0);
1829 op0 = State.regs[OP[0]];
1830 op1 = OP[1] & 0x7;
1831 temp = SEXT16 (OP[2]);
1832 op2 = temp;
1833 temp = load_mem (op0 + op2, 1);
1834 State.sregs[5] &= ~PSW_Z;
1835 if ((temp & (1 << op1)) == 0)
1836 State.sregs[5] |= PSW_Z;
1837 temp |= (1 << op1);
1838 store_mem (op0 + op2, 1, temp);
1839 trace_output (OP_BIT);
1840 }
1841
1842 /* not1 */
1843 void
1844 OP_47C0 ()
1845 {
1846 unsigned int op0, op1, op2;
1847 int temp;
1848
1849 trace_input ("not1", OP_BIT, 0);
1850 op0 = State.regs[OP[0]];
1851 op1 = OP[1] & 0x7;
1852 temp = SEXT16 (OP[2]);
1853 op2 = temp;
1854 temp = load_mem (op0 + op2, 1);
1855 State.sregs[5] &= ~PSW_Z;
1856 if ((temp & (1 << op1)) == 0)
1857 State.sregs[5] |= PSW_Z;
1858 temp ^= (1 << op1);
1859 store_mem (op0 + op2, 1, temp);
1860 trace_output (OP_BIT);
1861 }
1862
1863 /* clr1 */
1864 void
1865 OP_87C0 ()
1866 {
1867 unsigned int op0, op1, op2;
1868 int temp;
1869
1870 trace_input ("clr1", OP_BIT, 0);
1871 op0 = State.regs[OP[0]];
1872 op1 = OP[1] & 0x7;
1873 temp = SEXT16 (OP[2]);
1874 op2 = temp;
1875 temp = load_mem (op0 + op2, 1);
1876 State.sregs[5] &= ~PSW_Z;
1877 if ((temp & (1 << op1)) == 0)
1878 State.sregs[5] |= PSW_Z;
1879 temp &= ~(1 << op1);
1880 store_mem (op0 + op2, 1, temp);
1881 trace_output (OP_BIT);
1882 }
1883
1884 /* tst1 */
1885 void
1886 OP_C7C0 ()
1887 {
1888 unsigned int op0, op1, op2;
1889 int temp;
1890
1891 trace_input ("tst1", OP_BIT, 0);
1892 op0 = State.regs[OP[0]];
1893 op1 = OP[1] & 0x7;
1894 temp = SEXT16 (OP[2]);
1895 op2 = temp;
1896 temp = load_mem (op0 + op2, 1);
1897 State.sregs[5] &= ~PSW_Z;
1898 if ((temp & (1 << op1)) == 0)
1899 State.sregs[5] |= PSW_Z;
1900 trace_output (OP_BIT);
1901 }
1902
1903 /* breakpoint */
1904 void
1905 OP_FFFF ()
1906 {
1907 State.exception = SIGTRAP;
1908 PC -= 4;
1909 }
1910
1911 /* di */
1912 void
1913 OP_16007E0 ()
1914 {
1915 trace_input ("di", OP_NONE, 0);
1916 State.sregs[5] |= PSW_ID;
1917 trace_output (OP_NONE);
1918 }
1919
1920 /* ei */
1921 void
1922 OP_16087E0 ()
1923 {
1924 trace_input ("ei", OP_NONE, 0);
1925 State.sregs[5] &= ~PSW_ID;
1926 trace_output (OP_NONE);
1927 }
1928
1929 /* halt, not supported */
1930 void
1931 OP_12007E0 ()
1932 {
1933 trace_input ("halt", OP_NONE, 0);
1934 State.exception = SIGQUIT;
1935 trace_output (OP_NONE);
1936 }
1937
1938 /* reti, not supported */
1939 void
1940 OP_14007E0 ()
1941 {
1942 trace_input ("reti", OP_NONE, 0);
1943 trace_output (OP_NONE);
1944
1945 if ((State.sregs[5] & (PSW_NP | PSW_EP)) == PSW_NP)
1946 { /* Only NP is on */
1947 PC = State.sregs[2] - 4; /* FEPC */
1948 State.sregs[5] = State.sregs[3]; /* FEPSW */
1949 }
1950 else
1951 {
1952 PC = State.sregs[0] - 4; /* EIPC */
1953 State.sregs[5] = State.sregs[1]; /* EIPSW */
1954 }
1955 }
1956
1957 /* trap, not supportd */
1958 void
1959 OP_10007E0 ()
1960 {
1961 trace_input ("trap", OP_TRAP, 0);
1962 trace_output (OP_TRAP);
1963
1964 /* Trap 31 is used for simulating OS I/O functions */
1965
1966 if (OP[0] == 31)
1967 {
1968 int save_errno = errno;
1969 errno = 0;
1970
1971 /* Registers passed to trap 0 */
1972
1973 #define FUNC State.regs[6] /* function number, return value */
1974 #define PARM1 State.regs[7] /* optional parm 1 */
1975 #define PARM2 State.regs[8] /* optional parm 2 */
1976 #define PARM3 State.regs[9] /* optional parm 3 */
1977
1978 /* Registers set by trap 0 */
1979
1980 #define RETVAL State.regs[10] /* return value */
1981 #define RETERR State.regs[11] /* return error code */
1982
1983 /* Turn a pointer in a register into a pointer into real memory. */
1984
1985 #define MEMPTR(x) (map (x))
1986
1987 switch (FUNC)
1988 {
1989 #if !defined(__GO32__) && !defined(_WIN32)
1990 case SYS_fork:
1991 RETVAL = fork ();
1992 break;
1993 case SYS_execve:
1994 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
1995 (char **)MEMPTR (PARM3));
1996 break;
1997 case SYS_execv:
1998 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
1999 break;
2000 #if 0
2001 case SYS_pipe:
2002 {
2003 reg_t buf;
2004 int host_fd[2];
2005
2006 buf = PARM1;
2007 RETVAL = pipe (host_fd);
2008 SW (buf, host_fd[0]);
2009 buf += sizeof(uint16);
2010 SW (buf, host_fd[1]);
2011 }
2012 break;
2013
2014 case SYS_wait:
2015 {
2016 int status;
2017
2018 RETVAL = wait (&status);
2019 SW (PARM1, status);
2020 }
2021 break;
2022 #endif
2023 #endif
2024
2025 case SYS_read:
2026 RETVAL = v850_callback->read (v850_callback, PARM1, MEMPTR (PARM2),
2027 PARM3);
2028 break;
2029 case SYS_write:
2030 if (PARM1 == 1)
2031 RETVAL = (int)v850_callback->write_stdout (v850_callback,
2032 MEMPTR (PARM2), PARM3);
2033 else
2034 RETVAL = (int)v850_callback->write (v850_callback, PARM1,
2035 MEMPTR (PARM2), PARM3);
2036 break;
2037 case SYS_lseek:
2038 RETVAL = v850_callback->lseek (v850_callback, PARM1, PARM2, PARM3);
2039 break;
2040 case SYS_close:
2041 RETVAL = v850_callback->close (v850_callback, PARM1);
2042 break;
2043 case SYS_open:
2044 RETVAL = v850_callback->open (v850_callback, MEMPTR (PARM1), PARM2);
2045 break;
2046 case SYS_exit:
2047 /* EXIT - caller can look in PARM1 to work out the
2048 reason */
2049 if (PARM1 == 0xdead || PARM1 == 0x1)
2050 State.exception = SIGABRT;
2051 else
2052 State.exception = SIGQUIT;
2053 break;
2054
2055 case SYS_stat: /* added at hmsi */
2056 /* stat system call */
2057 {
2058 struct stat host_stat;
2059 reg_t buf;
2060
2061 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2062
2063 buf = PARM2;
2064
2065 /* Just wild-assed guesses. */
2066 store_mem (buf, 2, host_stat.st_dev);
2067 store_mem (buf + 2, 2, host_stat.st_ino);
2068 store_mem (buf + 4, 4, host_stat.st_mode);
2069 store_mem (buf + 8, 2, host_stat.st_nlink);
2070 store_mem (buf + 10, 2, host_stat.st_uid);
2071 store_mem (buf + 12, 2, host_stat.st_gid);
2072 store_mem (buf + 14, 2, host_stat.st_rdev);
2073 store_mem (buf + 16, 4, host_stat.st_size);
2074 store_mem (buf + 20, 4, host_stat.st_atime);
2075 store_mem (buf + 28, 4, host_stat.st_mtime);
2076 store_mem (buf + 36, 4, host_stat.st_ctime);
2077 }
2078 break;
2079
2080 case SYS_chown:
2081 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2082 break;
2083 case SYS_chmod:
2084 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2085 break;
2086 case SYS_utime:
2087 /* Cast the second argument to void *, to avoid type mismatch
2088 if a prototype is present. */
2089 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2090 break;
2091 default:
2092 abort ();
2093 }
2094 RETERR = errno;
2095 errno = save_errno;
2096 }
2097 else
2098 { /* Trap 0 -> 30 */
2099 State.sregs[0] = PC + 4; /* EIPC */
2100 State.sregs[1] = State.sregs[5]; /* EIPSW */
2101 State.sregs[4] &= 0xffff0000; /* Mask out EICC */
2102 State.sregs[4] |= 0x40 + OP[0]; /* EICC */
2103 State.sregs[5] |= PSW_EP | PSW_ID; /* Now doing exception processing */
2104 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
2105 }
2106 }
2107
2108 /* ldsr, reg,reg */
2109 void
2110 OP_2007E0 ()
2111 {
2112 unsigned int op0;
2113
2114 trace_input ("ldsr", OP_LDSR, 0);
2115 op0 = State.regs[OP[0]];
2116 State.sregs[OP[1]] = op0;
2117 trace_output (OP_LDSR);
2118 }
2119
2120 /* stsr, not supported */
2121 void
2122 OP_4007E0 ()
2123 {
2124 unsigned int op0;
2125
2126 trace_input ("stsr", OP_STSR, 0);
2127 op0 = State.sregs[OP[1]];
2128 State.regs[OP[0]] = op0;
2129 trace_output (OP_STSR);
2130 }