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Replace memory model with one from sim/common directory.
[binutils-gdb.git] / sim / v850 / simops.c
1 #include <signal.h>
2 #include "sim-main.h"
3 #include "v850_sim.h"
4 #include "simops.h"
5
6 #ifdef HAVE_UTIME_H
7 #include <utime.h>
8 #endif
9
10 #ifdef HAVE_TIME_H
11 #include <time.h>
12 #endif
13
14 #ifdef HAVE_UNISTD_H
15 #include <unistd.h>
16 #endif
17
18 /* FIXME - should be including a version of syscall.h that does not
19 pollute the name space */
20 #include "../../libgloss/v850/sys/syscall.h"
21
22 #include "bfd.h"
23 #include "libiberty.h"
24
25 #include <errno.h>
26 #if !defined(__GO32__) && !defined(_WIN32)
27 #include <sys/stat.h>
28 #include <sys/times.h>
29 #include <sys/time.h>
30 #endif
31
32 enum op_types
33 {
34 OP_UNKNOWN,
35 OP_NONE,
36 OP_TRAP,
37 OP_REG,
38 OP_REG_REG,
39 OP_REG_REG_CMP,
40 OP_REG_REG_MOVE,
41 OP_IMM_REG,
42 OP_IMM_REG_CMP,
43 OP_IMM_REG_MOVE,
44 OP_COND_BR,
45 OP_LOAD16,
46 OP_STORE16,
47 OP_LOAD32,
48 OP_STORE32,
49 OP_JUMP,
50 OP_IMM_REG_REG,
51 OP_UIMM_REG_REG,
52 OP_BIT,
53 OP_EX1,
54 OP_EX2,
55 OP_LDSR,
56 OP_STSR,
57 /* start-sanitize-v850e */
58 OP_BIT_CHANGE,
59 OP_REG_REG_REG,
60 OP_REG_REG3,
61 /* end-sanitize-v850e */
62 /* start-sanitize-v850eq */
63 OP_IMM_REG_REG_REG,
64 OP_PUSHPOP1,
65 OP_PUSHPOP2,
66 OP_PUSHPOP3,
67 /* end-sanitize-v850eq */
68 };
69
70 /* start-sanitize-v850e */
71 /* This is an array of the bit positions of registers r20 .. r31 in that order in a prepare/dispose instruction. */
72 static int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
73 /* end-sanitize-v850e */
74 /* start-sanitize-v850eq */
75 /* This is an array of the bit positions of registers r16 .. r31 in that order in a push/pop instruction. */
76 static int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
77 /* This is an array of the bit positions of registers r1 .. r15 in that order in a push/pop instruction. */
78 static int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
79 /* end-sanitize-v850eq */
80
81 #ifdef DEBUG
82 static void trace_input PARAMS ((char *name, enum op_types type, int size));
83 static void trace_output PARAMS ((enum op_types result));
84 static int init_text_p = 0;
85 static asection *text;
86 static bfd_vma text_start;
87 static bfd_vma text_end;
88 extern bfd *prog_bfd;
89
90 #ifndef SIZE_INSTRUCTION
91 #define SIZE_INSTRUCTION 6
92 #endif
93
94 #ifndef SIZE_OPERANDS
95 #define SIZE_OPERANDS 16
96 #endif
97
98 #ifndef SIZE_VALUES
99 #define SIZE_VALUES 11
100 #endif
101
102 #ifndef SIZE_LOCATION
103 #define SIZE_LOCATION 40
104 #endif
105
106
107 static void
108 trace_input (name, type, size)
109 char *name;
110 enum op_types type;
111 int size;
112 {
113 char buf[1024];
114 char *p;
115 uint32 values[3];
116 int num_values, i;
117 char *cond;
118 asection *s;
119 const char *filename;
120 const char *functionname;
121 unsigned int linenumber;
122
123 if ((v850_debug & DEBUG_TRACE) == 0)
124 return;
125
126 buf[0] = '\0';
127 if (!init_text_p)
128 {
129 init_text_p = 1;
130 for (s = prog_bfd->sections; s; s = s->next)
131 if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
132 {
133 text = s;
134 text_start = bfd_get_section_vma (prog_bfd, s);
135 text_end = text_start + bfd_section_size (prog_bfd, s);
136 break;
137 }
138 }
139
140 if (text && PC >= text_start && PC < text_end)
141 {
142 filename = (const char *)0;
143 functionname = (const char *)0;
144 linenumber = 0;
145 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
146 &filename, &functionname, &linenumber))
147 {
148 p = buf;
149 if (linenumber)
150 {
151 sprintf (p, "Line %5d ", linenumber);
152 p += strlen (p);
153 }
154
155 if (functionname)
156 {
157 sprintf (p, "Func %s ", functionname);
158 p += strlen (p);
159 }
160 else if (filename)
161 {
162 char *q = (char *) strrchr (filename, '/');
163 sprintf (p, "File %s ", (q) ? q+1 : filename);
164 p += strlen (p);
165 }
166
167 if (*p == ' ')
168 *p = '\0';
169 }
170 }
171
172 (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
173 (unsigned)PC,
174 SIZE_LOCATION, SIZE_LOCATION, buf,
175 SIZE_INSTRUCTION, name);
176
177 switch (type)
178 {
179 default:
180 case OP_UNKNOWN:
181 case OP_NONE:
182 strcpy (buf, "unknown");
183 break;
184
185 case OP_TRAP:
186 sprintf (buf, "%d", OP[0]);
187 break;
188
189 case OP_REG:
190 sprintf (buf, "r%d", OP[0]);
191 break;
192
193 case OP_REG_REG:
194 case OP_REG_REG_CMP:
195 case OP_REG_REG_MOVE:
196 sprintf (buf, "r%d,r%d", OP[0], OP[1]);
197 break;
198
199 case OP_IMM_REG:
200 case OP_IMM_REG_CMP:
201 case OP_IMM_REG_MOVE:
202 sprintf (buf, "%d,r%d", OP[0], OP[1]);
203 break;
204
205 case OP_COND_BR:
206 sprintf (buf, "%d", SEXT9 (OP[0]));
207 break;
208
209 case OP_LOAD16:
210 sprintf (buf, "%d[r30],r%d", OP[1] * size, OP[0]);
211 break;
212
213 case OP_STORE16:
214 sprintf (buf, "r%d,%d[r30]", OP[0], OP[1] * size);
215 break;
216
217 case OP_LOAD32:
218 sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
219 break;
220
221 case OP_STORE32:
222 sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
223 break;
224
225 case OP_JUMP:
226 sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
227 break;
228
229 case OP_IMM_REG_REG:
230 sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
231 break;
232
233 case OP_UIMM_REG_REG:
234 sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
235 break;
236
237 case OP_BIT:
238 sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
239 break;
240
241 case OP_EX1:
242 switch (OP[0] & 0xf)
243 {
244 default: cond = "?"; break;
245 case 0x0: cond = "v"; break;
246 case 0x1: cond = "c"; break;
247 case 0x2: cond = "z"; break;
248 case 0x3: cond = "nh"; break;
249 case 0x4: cond = "s"; break;
250 case 0x5: cond = "t"; break;
251 case 0x6: cond = "lt"; break;
252 case 0x7: cond = "le"; break;
253 case 0x8: cond = "nv"; break;
254 case 0x9: cond = "nc"; break;
255 case 0xa: cond = "nz"; break;
256 case 0xb: cond = "h"; break;
257 case 0xc: cond = "ns"; break;
258 case 0xd: cond = "sa"; break;
259 case 0xe: cond = "ge"; break;
260 case 0xf: cond = "gt"; break;
261 }
262
263 sprintf (buf, "%s,r%d", cond, OP[1]);
264 break;
265
266 case OP_EX2:
267 strcpy (buf, "EX2");
268 break;
269
270 case OP_LDSR:
271 case OP_STSR:
272 sprintf (buf, "r%d,s%d", OP[0], OP[1]);
273 break;
274
275 case OP_PUSHPOP1:
276 for (i = 0; i < 12; i++)
277 if (OP[3] & (1 << type1_regs[i]))
278 strcat (buf, "r%d ", i + 20);
279 break;
280
281 case OP_PUSHPOP2:
282 for (i = 0; i < 16; i++)
283 if (OP[3] & (1 << type2_regs[i]))
284 strcat (buf, "r%d ", i + 16);
285 if (OP[3] & (1 << 19))
286 strcat (buf, "F/EIPC, F/EIPSW " );
287 break;
288
289 case OP_PUSHPOP3:
290 for (i = 0; i < 15; i++)
291 if (OP[3] & (1 << type3_regs[i]))
292 strcat (buf, "r%d ", i + 1);
293 if (OP[3] & (1 << 3))
294 strcat (buf, "PSW " );
295 if (OP[3] & (1 << 19))
296 strcat (buf, "F/EIPC, F/EIPSW " );
297 break;
298
299 case OP_BIT_CHANGE:
300 sprintf (buf, "r%d, [r%d]", OP[1], OP[0] );
301 break;
302 }
303
304 if ((v850_debug & DEBUG_VALUES) == 0)
305 {
306 (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
307 }
308 else
309 {
310 (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
311 switch (type)
312 {
313 default:
314 case OP_UNKNOWN:
315 case OP_NONE:
316 case OP_TRAP:
317 num_values = 0;
318 break;
319
320 case OP_REG:
321 case OP_REG_REG_MOVE:
322 values[0] = State.regs[OP[0]];
323 num_values = 1;
324 break;
325
326 case OP_BIT_CHANGE:
327 case OP_REG_REG:
328 case OP_REG_REG_CMP:
329 values[0] = State.regs[OP[1]];
330 values[1] = State.regs[OP[0]];
331 num_values = 2;
332 break;
333
334 case OP_IMM_REG:
335 case OP_IMM_REG_CMP:
336 values[0] = SEXT5 (OP[0]);
337 values[1] = OP[1];
338 num_values = 2;
339 break;
340
341 case OP_IMM_REG_MOVE:
342 values[0] = SEXT5 (OP[0]);
343 num_values = 1;
344 break;
345
346 case OP_COND_BR:
347 values[0] = State.pc;
348 values[1] = SEXT9 (OP[0]);
349 values[2] = PSW;
350 num_values = 3;
351 break;
352
353 case OP_LOAD16:
354 values[0] = OP[1] * size;
355 values[1] = State.regs[30];
356 num_values = 2;
357 break;
358
359 case OP_STORE16:
360 values[0] = State.regs[OP[0]];
361 values[1] = OP[1] * size;
362 values[2] = State.regs[30];
363 num_values = 3;
364 break;
365
366 case OP_LOAD32:
367 values[0] = SEXT16 (OP[2]);
368 values[1] = State.regs[OP[0]];
369 num_values = 2;
370 break;
371
372 case OP_STORE32:
373 values[0] = State.regs[OP[1]];
374 values[1] = SEXT16 (OP[2]);
375 values[2] = State.regs[OP[0]];
376 num_values = 3;
377 break;
378
379 case OP_JUMP:
380 values[0] = SEXT22 (OP[0]);
381 values[1] = State.pc;
382 num_values = 2;
383 break;
384
385 case OP_IMM_REG_REG:
386 values[0] = SEXT16 (OP[0]) << size;
387 values[1] = State.regs[OP[1]];
388 num_values = 2;
389 break;
390
391 case OP_UIMM_REG_REG:
392 values[0] = (OP[0] & 0xffff) << size;
393 values[1] = State.regs[OP[1]];
394 num_values = 2;
395 break;
396
397 case OP_BIT:
398 num_values = 0;
399 break;
400
401 case OP_EX1:
402 values[0] = PSW;
403 num_values = 1;
404 break;
405
406 case OP_EX2:
407 num_values = 0;
408 break;
409
410 case OP_LDSR:
411 values[0] = State.regs[OP[0]];
412 num_values = 1;
413 break;
414
415 case OP_STSR:
416 values[0] = State.sregs[OP[1]];
417 num_values = 1;
418 }
419
420 for (i = 0; i < num_values; i++)
421 (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
422
423 while (i++ < 3)
424 (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
425 }
426 }
427
428 static void
429 trace_output (result)
430 enum op_types result;
431 {
432 if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
433 {
434 switch (result)
435 {
436 default:
437 case OP_UNKNOWN:
438 case OP_NONE:
439 case OP_TRAP:
440 case OP_REG:
441 case OP_REG_REG_CMP:
442 case OP_IMM_REG_CMP:
443 case OP_COND_BR:
444 case OP_STORE16:
445 case OP_STORE32:
446 case OP_BIT:
447 case OP_EX2:
448 break;
449
450 case OP_LOAD16:
451 case OP_STSR:
452 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
453 (unsigned long)State.regs[OP[0]]);
454 break;
455
456 case OP_REG_REG:
457 case OP_REG_REG_MOVE:
458 case OP_IMM_REG:
459 case OP_IMM_REG_MOVE:
460 case OP_LOAD32:
461 case OP_EX1:
462 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
463 (unsigned long)State.regs[OP[1]]);
464 break;
465
466 case OP_IMM_REG_REG:
467 case OP_UIMM_REG_REG:
468 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
469 (unsigned long)State.regs[OP[2]]);
470 break;
471
472 case OP_JUMP:
473 if (OP[1] != 0)
474 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
475 (unsigned long)State.regs[OP[1]]);
476 break;
477
478 case OP_LDSR:
479 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
480 (unsigned long)State.sregs[OP[1]]);
481 break;
482 }
483
484 (*v850_callback->printf_filtered) (v850_callback, "\n");
485 }
486 }
487
488 #else
489 #define trace_input(NAME, IN1, IN2)
490 #define trace_output(RESULT)
491
492 //#define trace_input(NAME, IN1, IN2) fprintf (stderr, NAME "\n" );
493
494 #endif
495
496 \f
497 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
498 static unsigned int
499 condition_met (unsigned code)
500 {
501 unsigned int psw = PSW;
502
503 switch (code & 0xf)
504 {
505 case 0x0: return ((psw & PSW_OV) != 0);
506 case 0x1: return ((psw & PSW_CY) != 0);
507 case 0x2: return ((psw & PSW_Z) != 0);
508 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
509 case 0x4: return ((psw & PSW_S) != 0);
510 /*case 0x5: return 1;*/
511 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
512 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
513 case 0x8: return ((psw & PSW_OV) == 0);
514 case 0x9: return ((psw & PSW_CY) == 0);
515 case 0xa: return ((psw & PSW_Z) == 0);
516 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
517 case 0xc: return ((psw & PSW_S) == 0);
518 case 0xd: return ((psw & PSW_SAT) != 0);
519 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
520 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
521 }
522
523 return 1;
524 }
525
526 static unsigned long
527 Add32 (unsigned long a1, unsigned long a2, int * carry)
528 {
529 unsigned long result = (a1 + a2);
530
531 * carry = (result < a1);
532
533 return result;
534 }
535
536 static void
537 Multiply64 (boolean sign, unsigned long op0)
538 {
539 unsigned long op1;
540 unsigned long lo;
541 unsigned long mid1;
542 unsigned long mid2;
543 unsigned long hi;
544 unsigned long RdLo;
545 unsigned long RdHi;
546 int carry;
547
548 op1 = State.regs[ OP[1] ];
549
550 if (sign)
551 {
552 /* Compute sign of result and adjust operands if necessary. */
553
554 sign = (op0 ^ op1) & 0x80000000;
555
556 if (((signed long) op0) < 0)
557 op0 = - op0;
558
559 if (((signed long) op1) < 0)
560 op1 = - op1;
561 }
562
563 /* We can split the 32x32 into four 16x16 operations. This ensures
564 that we do not lose precision on 32bit only hosts: */
565 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
566 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
567 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
568 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
569
570 /* We now need to add all of these results together, taking care
571 to propogate the carries from the additions: */
572 RdLo = Add32 (lo, (mid1 << 16), & carry);
573 RdHi = carry;
574 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
575 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
576
577 if (sign)
578 {
579 /* Negate result if necessary. */
580
581 RdLo = ~ RdLo;
582 RdHi = ~ RdHi;
583 if (RdLo == 0xFFFFFFFF)
584 {
585 RdLo = 0;
586 RdHi += 1;
587 }
588 else
589 RdLo += 1;
590 }
591
592 State.regs[ OP[1] ] = RdLo;
593 State.regs[ OP[2] >> 11 ] = RdHi;
594
595 return;
596 }
597
598 \f
599 /* Read a null terminated string from memory, return in a buffer */
600 static char *
601 fetch_str (sd, addr)
602 SIM_DESC sd;
603 address_word addr;
604 {
605 char *buf;
606 int nr = 0;
607 while (sim_core_read_1 (STATE_CPU (sd, 0),
608 PC, sim_core_read_map, addr + nr) != 0)
609 nr++;
610 buf = NZALLOC (char, nr + 1);
611 sim_read (simulator, addr, buf, nr);
612 return buf;
613 }
614
615 /* Read a null terminated argument vector from memory, return in a
616 buffer */
617 static char **
618 fetch_argv (sd, addr)
619 SIM_DESC sd;
620 address_word addr;
621 {
622 int max_nr = 64;
623 int nr = 0;
624 char **buf = xmalloc (max_nr * sizeof (char*));
625 while (1)
626 {
627 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
628 PC, sim_core_read_map, addr + nr * 4);
629 if (a == 0) break;
630 buf[nr] = fetch_str (sd, a);
631 nr ++;
632 if (nr == max_nr - 1)
633 {
634 max_nr += 50;
635 buf = xrealloc (buf, max_nr * sizeof (char*));
636 }
637 }
638 buf[nr] = 0;
639 return buf;
640 }
641
642 \f
643 /* sld.b */
644 int
645 OP_300 ()
646 {
647 unsigned long result;
648
649 result = load_mem (State.regs[30] + (OP[3] & 0x7f), 1);
650
651 /* start-sanitize-v850eq */
652 #ifdef ARCH_v850eq
653 trace_input ("sld.bu", OP_LOAD16, 1);
654
655 State.regs[ OP[1] ] = result;
656 #else
657 /* end-sanitize-v850eq */
658 trace_input ("sld.b", OP_LOAD16, 1);
659
660 State.regs[ OP[1] ] = SEXT8 (result);
661 /* start-sanitize-v850eq */
662 #endif
663 /* end-sanitize-v850eq */
664
665 trace_output (OP_LOAD16);
666
667 return 2;
668 }
669
670 /* sld.h */
671 int
672 OP_400 ()
673 {
674 unsigned long result;
675
676 result = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2);
677
678 /* start-sanitize-v850eq */
679 #ifdef ARCH_v850eq
680 trace_input ("sld.hu", OP_LOAD16, 2);
681
682 State.regs[ OP[1] ] = result;
683 #else
684 /* end-sanitize-v850eq */
685 trace_input ("sld.h", OP_LOAD16, 2);
686
687 State.regs[ OP[1] ] = SEXT16 (result);
688 /* start-sanitize-v850eq */
689 #endif
690 /* end-sanitize-v850eq */
691
692 trace_output (OP_LOAD16);
693
694 return 2;
695 }
696
697 /* sld.w */
698 int
699 OP_500 ()
700 {
701 trace_input ("sld.w", OP_LOAD16, 4);
702
703 State.regs[ OP[1] ] = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 4);
704
705 trace_output (OP_LOAD16);
706
707 return 2;
708 }
709
710 /* sst.b */
711 int
712 OP_380 ()
713 {
714 trace_input ("sst.b", OP_STORE16, 1);
715
716 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
717
718 trace_output (OP_STORE16);
719
720 return 2;
721 }
722
723 /* sst.h */
724 int
725 OP_480 ()
726 {
727 trace_input ("sst.h", OP_STORE16, 2);
728
729 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
730
731 trace_output (OP_STORE16);
732
733 return 2;
734 }
735
736 /* sst.w */
737 int
738 OP_501 ()
739 {
740 trace_input ("sst.w", OP_STORE16, 4);
741
742 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
743
744 trace_output (OP_STORE16);
745
746 return 2;
747 }
748
749 /* ld.b */
750 int
751 OP_700 ()
752 {
753 int adr;
754
755 trace_input ("ld.b", OP_LOAD32, 1);
756
757 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
758
759 State.regs[ OP[1] ] = SEXT8 (load_mem (adr, 1));
760
761 trace_output (OP_LOAD32);
762
763 return 4;
764 }
765
766 /* ld.h */
767 int
768 OP_720 ()
769 {
770 int adr;
771
772 trace_input ("ld.h", OP_LOAD32, 2);
773
774 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
775 adr &= ~0x1;
776
777 State.regs[ OP[1] ] = SEXT16 (load_mem (adr, 2));
778
779 trace_output (OP_LOAD32);
780
781 return 4;
782 }
783
784 /* ld.w */
785 int
786 OP_10720 ()
787 {
788 int adr;
789
790 trace_input ("ld.w", OP_LOAD32, 4);
791
792 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
793 adr &= ~0x3;
794
795 State.regs[ OP[1] ] = load_mem (adr, 4);
796
797 trace_output (OP_LOAD32);
798
799 return 4;
800 }
801
802 /* st.b */
803 int
804 OP_740 ()
805 {
806 trace_input ("st.b", OP_STORE32, 1);
807
808 store_mem (State.regs[ OP[0] ] + SEXT16 (OP[2]), 1, State.regs[ OP[1] ]);
809
810 trace_output (OP_STORE32);
811
812 return 4;
813 }
814
815 /* st.h */
816 int
817 OP_760 ()
818 {
819 int adr;
820
821 trace_input ("st.h", OP_STORE32, 2);
822
823 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
824 adr &= ~1;
825
826 store_mem (adr, 2, State.regs[ OP[1] ]);
827
828 trace_output (OP_STORE32);
829
830 return 4;
831 }
832
833 /* st.w */
834 int
835 OP_10760 ()
836 {
837 int adr;
838
839 trace_input ("st.w", OP_STORE32, 4);
840
841 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
842 adr &= ~3;
843
844 store_mem (adr, 4, State.regs[ OP[1] ]);
845
846 trace_output (OP_STORE32);
847
848 return 4;
849 }
850
851 static int
852 branch (int code)
853 {
854 trace_input ("Bcond", OP_COND_BR, 0);
855 trace_output (OP_COND_BR);
856
857 if (condition_met (code))
858 return SEXT9 (((OP[3] & 0x70) >> 3) | ((OP[3] & 0xf800) >> 7));
859 else
860 return 2;
861 }
862
863 /* bv disp9 */
864 int
865 OP_580 ()
866 {
867 return branch (0);
868 }
869
870 /* bl disp9 */
871 int
872 OP_581 ()
873 {
874 return branch (1);
875 }
876
877 /* be disp9 */
878 int
879 OP_582 ()
880 {
881 return branch (2);
882 }
883
884 /* bnh disp 9*/
885 int
886 OP_583 ()
887 {
888 return branch (3);
889 }
890
891 /* bn disp9 */
892 int
893 OP_584 ()
894 {
895 return branch (4);
896 }
897
898 /* br disp9 */
899 int
900 OP_585 ()
901 {
902 return branch (5);
903 }
904
905 /* blt disp9 */
906 int
907 OP_586 ()
908 {
909 return branch (6);
910 }
911
912 /* ble disp9 */
913 int
914 OP_587 ()
915 {
916 return branch (7);
917 }
918
919 /* bnv disp9 */
920 int
921 OP_588 ()
922 {
923 return branch (8);
924 }
925
926 /* bnl disp9 */
927 int
928 OP_589 ()
929 {
930 return branch (9);
931 }
932
933 /* bne disp9 */
934 int
935 OP_58A ()
936 {
937 return branch (10);
938 }
939
940 /* bh disp9 */
941 int
942 OP_58B ()
943 {
944 return branch (11);
945 }
946
947 /* bp disp9 */
948 int
949 OP_58C ()
950 {
951 return branch (12);
952 }
953
954 /* bsa disp9 */
955 int
956 OP_58D ()
957 {
958 return branch (13);
959 }
960
961 /* bge disp9 */
962 int
963 OP_58E ()
964 {
965 return branch (14);
966 }
967
968 /* bgt disp9 */
969 int
970 OP_58F ()
971 {
972 return branch (15);
973 }
974
975 /* jmp [reg1] */
976 /* sld.bu disp4[ep], reg2 */
977 int
978 OP_60 ()
979 {
980 if (OP[1] == 0)
981 {
982 trace_input ("jmp", OP_REG, 0);
983
984 PC = State.regs[ OP[0] ];
985
986 trace_output (OP_REG);
987
988 return 0; /* Add nothing to the PC, we have already done it. */
989 }
990 /* start-sanitize-v850e */
991 else
992 {
993 unsigned long result;
994
995 result = load_mem (State.regs[30] + (OP[3] & 0xf), 1);
996
997 /* start-sanitize-v850eq */
998 #ifdef ARCH_v850eq
999 trace_input ("sld.b", OP_LOAD16, 1);
1000
1001 State.regs[ OP[1] ] = SEXT8 (result);
1002 #else
1003 /* end-sanitize-v850eq */
1004 trace_input ("sld.bu", OP_LOAD16, 1);
1005
1006 State.regs[ OP[1] ] = result;
1007 /* start-sanitize-v850eq */
1008 #endif
1009 /* end-sanitize-v850eq */
1010
1011 trace_output (OP_LOAD16);
1012
1013 return 2;
1014 }
1015 /* end-sanitize-v850e */
1016 }
1017
1018 /* jarl/jr disp22, reg */
1019 int
1020 OP_780 ()
1021 {
1022 trace_input ("jarl/jr", OP_JUMP, 0);
1023
1024 if (OP[ 1 ] != 0)
1025 State.regs[ OP[1] ] = PC + 4;
1026
1027 trace_output (OP_JUMP);
1028
1029 return SEXT22 (((OP[3] & 0x3f) << 16) | OP[2]);
1030 }
1031
1032 /* add reg, reg */
1033 int
1034 OP_1C0 ()
1035 {
1036 unsigned int op0, op1, result, z, s, cy, ov;
1037
1038 trace_input ("add", OP_REG_REG, 0);
1039
1040 /* Compute the result. */
1041
1042 op0 = State.regs[ OP[0] ];
1043 op1 = State.regs[ OP[1] ];
1044
1045 result = op0 + op1;
1046
1047 /* Compute the condition codes. */
1048 z = (result == 0);
1049 s = (result & 0x80000000);
1050 cy = (result < op0 || result < op1);
1051 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1052 && (op0 & 0x80000000) != (result & 0x80000000));
1053
1054 /* Store the result and condition codes. */
1055 State.regs[OP[1]] = result;
1056 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1057 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1058 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1059 trace_output (OP_REG_REG);
1060
1061 return 2;
1062 }
1063
1064 /* add sign_extend(imm5), reg */
1065 int
1066 OP_240 ()
1067 {
1068 unsigned int op0, op1, result, z, s, cy, ov;
1069 int temp;
1070
1071 trace_input ("add", OP_IMM_REG, 0);
1072
1073 /* Compute the result. */
1074 temp = SEXT5 (OP[0]);
1075 op0 = temp;
1076 op1 = State.regs[OP[1]];
1077 result = op0 + op1;
1078
1079 /* Compute the condition codes. */
1080 z = (result == 0);
1081 s = (result & 0x80000000);
1082 cy = (result < op0 || result < op1);
1083 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1084 && (op0 & 0x80000000) != (result & 0x80000000));
1085
1086 /* Store the result and condition codes. */
1087 State.regs[OP[1]] = result;
1088 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1089 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1090 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1091 trace_output (OP_IMM_REG);
1092
1093 return 2;
1094 }
1095
1096 /* addi sign_extend(imm16), reg, reg */
1097 int
1098 OP_600 ()
1099 {
1100 unsigned int op0, op1, result, z, s, cy, ov;
1101
1102 trace_input ("addi", OP_IMM_REG_REG, 0);
1103
1104 /* Compute the result. */
1105
1106 op0 = SEXT16 (OP[2]);
1107 op1 = State.regs[ OP[0] ];
1108 result = op0 + op1;
1109
1110 /* Compute the condition codes. */
1111 z = (result == 0);
1112 s = (result & 0x80000000);
1113 cy = (result < op0 || result < op1);
1114 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1115 && (op0 & 0x80000000) != (result & 0x80000000));
1116
1117 /* Store the result and condition codes. */
1118 State.regs[OP[1]] = result;
1119 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1120 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1121 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1122 trace_output (OP_IMM_REG_REG);
1123
1124 return 4;
1125 }
1126
1127 /* sub reg1, reg2 */
1128 int
1129 OP_1A0 ()
1130 {
1131 unsigned int op0, op1, result, z, s, cy, ov;
1132
1133 trace_input ("sub", OP_REG_REG, 0);
1134 /* Compute the result. */
1135 op0 = State.regs[ OP[0] ];
1136 op1 = State.regs[ OP[1] ];
1137 result = op1 - op0;
1138
1139 /* Compute the condition codes. */
1140 z = (result == 0);
1141 s = (result & 0x80000000);
1142 cy = (op1 < op0);
1143 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1144 && (op1 & 0x80000000) != (result & 0x80000000));
1145
1146 /* Store the result and condition codes. */
1147 State.regs[OP[1]] = result;
1148 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1149 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1150 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1151 trace_output (OP_REG_REG);
1152
1153 return 2;
1154 }
1155
1156 /* subr reg1, reg2 */
1157 int
1158 OP_180 ()
1159 {
1160 unsigned int op0, op1, result, z, s, cy, ov;
1161
1162 trace_input ("subr", OP_REG_REG, 0);
1163 /* Compute the result. */
1164 op0 = State.regs[ OP[0] ];
1165 op1 = State.regs[ OP[1] ];
1166 result = op0 - op1;
1167
1168 /* Compute the condition codes. */
1169 z = (result == 0);
1170 s = (result & 0x80000000);
1171 cy = (op0 < op1);
1172 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1173 && (op0 & 0x80000000) != (result & 0x80000000));
1174
1175 /* Store the result and condition codes. */
1176 State.regs[OP[1]] = result;
1177 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1178 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1179 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1180 trace_output (OP_REG_REG);
1181
1182 return 2;
1183 }
1184
1185 /* sxh reg1 */
1186 /* mulh reg1, reg2 */
1187 int
1188 OP_E0 ()
1189 {
1190 /* start-sanitize-v850e */
1191 if (OP[1] == 0)
1192 {
1193 trace_input ("sxh", OP_REG, 0);
1194
1195 State.regs[ OP[0] ] = SEXT16 (State.regs[ OP[0] ]);
1196
1197 trace_output (OP_REG);
1198 }
1199 else
1200 /* end-sanitize-v850e */
1201 {
1202 trace_input ("mulh", OP_REG_REG, 0);
1203
1204 State.regs[ OP[1] ] = (SEXT16 (State.regs[ OP[1] ]) * SEXT16 (State.regs[ OP[0] ]));
1205
1206 trace_output (OP_REG_REG);
1207 }
1208
1209 return 2;
1210 }
1211
1212 /* mulh sign_extend(imm5), reg2 */
1213 int
1214 OP_2E0 ()
1215 {
1216 trace_input ("mulh", OP_IMM_REG, 0);
1217
1218 State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
1219
1220 trace_output (OP_IMM_REG);
1221
1222 return 2;
1223 }
1224
1225 /* mulhi imm16, reg1, reg2 */
1226 int
1227 OP_6E0 ()
1228 {
1229 if (OP[1] == 0)
1230 {
1231 }
1232 else
1233 {
1234 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1235
1236 State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[0] ]) * SEXT16 (OP[2]);
1237
1238 trace_output (OP_IMM_REG_REG);
1239 }
1240
1241 return 4;
1242 }
1243
1244 /* divh reg1, reg2 */
1245 /* switch reg1 */
1246 int
1247 OP_40 ()
1248 {
1249 /* start-sanitize-v850e */
1250 if (OP[1] == 0)
1251 {
1252 unsigned long adr;
1253
1254 trace_input ("switch", OP_REG, 0);
1255
1256 adr = State.pc + 2 + (State.regs[ OP[0] ] << 1);
1257 State.pc = State.pc + 2 + (SEXT16 (load_mem (adr, 2)) << 1);
1258
1259 trace_output (OP_REG);
1260 }
1261 else
1262 /* end-sanitize-v850e */
1263 {
1264 unsigned int op0, op1, result, ov, s, z;
1265 int temp;
1266
1267 trace_input ("divh", OP_REG_REG, 0);
1268
1269 /* Compute the result. */
1270 temp = SEXT16 (State.regs[ OP[0] ]);
1271 op0 = temp;
1272 op1 = State.regs[OP[1]];
1273
1274 if (op0 == 0xffffffff && op1 == 0x80000000)
1275 {
1276 result = 0x80000000;
1277 ov = 1;
1278 }
1279 else if (op0 != 0)
1280 {
1281 result = op1 / op0;
1282 ov = 0;
1283 }
1284 else
1285 {
1286 result = 0x0;
1287 ov = 1;
1288 }
1289
1290 /* Compute the condition codes. */
1291 z = (result == 0);
1292 s = (result & 0x80000000);
1293
1294 /* Store the result and condition codes. */
1295 State.regs[OP[1]] = result;
1296 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1297 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1298 | (ov ? PSW_OV : 0));
1299 trace_output (OP_REG_REG);
1300 }
1301
1302 return 2;
1303 }
1304
1305 /* cmp reg, reg */
1306 int
1307 OP_1E0 ()
1308 {
1309 unsigned int op0, op1, result, z, s, cy, ov;
1310
1311 trace_input ("cmp", OP_REG_REG_CMP, 0);
1312 /* Compute the result. */
1313 op0 = State.regs[ OP[0] ];
1314 op1 = State.regs[ OP[1] ];
1315 result = op1 - op0;
1316
1317 /* Compute the condition codes. */
1318 z = (result == 0);
1319 s = (result & 0x80000000);
1320 cy = (op1 < op0);
1321 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1322 && (op1 & 0x80000000) != (result & 0x80000000));
1323
1324 /* Set condition codes. */
1325 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1326 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1327 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1328 trace_output (OP_REG_REG_CMP);
1329
1330 return 2;
1331 }
1332
1333 /* cmp sign_extend(imm5), reg */
1334 int
1335 OP_260 ()
1336 {
1337 unsigned int op0, op1, result, z, s, cy, ov;
1338 int temp;
1339
1340 /* Compute the result. */
1341 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1342 temp = SEXT5 (OP[0]);
1343 op0 = temp;
1344 op1 = State.regs[OP[1]];
1345 result = op1 - op0;
1346
1347 /* Compute the condition codes. */
1348 z = (result == 0);
1349 s = (result & 0x80000000);
1350 cy = (op1 < op0);
1351 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1352 && (op1 & 0x80000000) != (result & 0x80000000));
1353
1354 /* Set condition codes. */
1355 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1356 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1357 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1358 trace_output (OP_IMM_REG_CMP);
1359
1360 return 2;
1361 }
1362
1363 /* setf cccc,reg2 */
1364 int
1365 OP_7E0 ()
1366 {
1367 trace_input ("setf", OP_EX1, 0);
1368
1369 State.regs[ OP[1] ] = condition_met (OP[0]);
1370
1371 trace_output (OP_EX1);
1372
1373 return 4;
1374 }
1375
1376 /* zxh reg1 */
1377 /* satadd reg,reg */
1378 int
1379 OP_C0 ()
1380 {
1381 /* start-sanitize-v850e */
1382 if (OP[1] == 0)
1383 {
1384 trace_input ("zxh", OP_REG, 0);
1385
1386 State.regs[ OP[0] ] &= 0xffff;
1387
1388 trace_output (OP_REG);
1389 }
1390 else
1391 /* end-sanitize-v850e */
1392 {
1393 unsigned int op0, op1, result, z, s, cy, ov, sat;
1394
1395 trace_input ("satadd", OP_REG_REG, 0);
1396 /* Compute the result. */
1397 op0 = State.regs[ OP[0] ];
1398 op1 = State.regs[ OP[1] ];
1399 result = op0 + op1;
1400
1401 /* Compute the condition codes. */
1402 z = (result == 0);
1403 s = (result & 0x80000000);
1404 cy = (result < op0 || result < op1);
1405 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1406 && (op0 & 0x80000000) != (result & 0x80000000));
1407 sat = ov;
1408
1409 /* Store the result and condition codes. */
1410 State.regs[OP[1]] = result;
1411 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1412 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1413 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1414 | (sat ? PSW_SAT : 0));
1415
1416 /* Handle saturated results. */
1417 if (sat && s)
1418 State.regs[OP[1]] = 0x80000000;
1419 else if (sat)
1420 State.regs[OP[1]] = 0x7fffffff;
1421 trace_output (OP_REG_REG);
1422 }
1423
1424 return 2;
1425 }
1426
1427 /* satadd sign_extend(imm5), reg */
1428 int
1429 OP_220 ()
1430 {
1431 unsigned int op0, op1, result, z, s, cy, ov, sat;
1432
1433 int temp;
1434
1435 trace_input ("satadd", OP_IMM_REG, 0);
1436
1437 /* Compute the result. */
1438 temp = SEXT5 (OP[0]);
1439 op0 = temp;
1440 op1 = State.regs[OP[1]];
1441 result = op0 + op1;
1442
1443 /* Compute the condition codes. */
1444 z = (result == 0);
1445 s = (result & 0x80000000);
1446 cy = (result < op0 || result < op1);
1447 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1448 && (op0 & 0x80000000) != (result & 0x80000000));
1449 sat = ov;
1450
1451 /* Store the result and condition codes. */
1452 State.regs[OP[1]] = result;
1453 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1454 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1455 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1456 | (sat ? PSW_SAT : 0));
1457
1458 /* Handle saturated results. */
1459 if (sat && s)
1460 State.regs[OP[1]] = 0x80000000;
1461 else if (sat)
1462 State.regs[OP[1]] = 0x7fffffff;
1463 trace_output (OP_IMM_REG);
1464
1465 return 2;
1466 }
1467
1468 /* satsub reg1, reg2 */
1469 /* sxb reg1 */
1470 int
1471 OP_A0 ()
1472 {
1473 /* start-sanitize-v850e */
1474 if (OP[1] == 0)
1475 {
1476 trace_input ("sxb", OP_REG, 0);
1477
1478 State.regs[ OP[0] ] = SEXT8 (State.regs[ OP[0] ]);
1479
1480 trace_output (OP_REG);
1481 }
1482 else
1483 /* end-sanitize-v850e */
1484 {
1485 unsigned int op0, op1, result, z, s, cy, ov, sat;
1486
1487 trace_input ("satsub", OP_REG_REG, 0);
1488
1489 /* Compute the result. */
1490 op0 = State.regs[ OP[0] ];
1491 op1 = State.regs[ OP[1] ];
1492 result = op1 - op0;
1493
1494 /* Compute the condition codes. */
1495 z = (result == 0);
1496 s = (result & 0x80000000);
1497 cy = (op1 < op0);
1498 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1499 && (op1 & 0x80000000) != (result & 0x80000000));
1500 sat = ov;
1501
1502 /* Store the result and condition codes. */
1503 State.regs[OP[1]] = result;
1504 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1505 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1506 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1507 | (sat ? PSW_SAT : 0));
1508
1509 /* Handle saturated results. */
1510 if (sat && s)
1511 State.regs[OP[1]] = 0x80000000;
1512 else if (sat)
1513 State.regs[OP[1]] = 0x7fffffff;
1514 trace_output (OP_REG_REG);
1515 }
1516
1517 return 2;
1518 }
1519
1520 /* satsubi sign_extend(imm16), reg */
1521 int
1522 OP_660 ()
1523 {
1524 unsigned int op0, op1, result, z, s, cy, ov, sat;
1525 int temp;
1526
1527 trace_input ("satsubi", OP_IMM_REG, 0);
1528
1529 /* Compute the result. */
1530 temp = SEXT16 (OP[2]);
1531 op0 = temp;
1532 op1 = State.regs[ OP[0] ];
1533 result = op1 - op0;
1534
1535 /* Compute the condition codes. */
1536 z = (result == 0);
1537 s = (result & 0x80000000);
1538 cy = (op1 < op0);
1539 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1540 && (op1 & 0x80000000) != (result & 0x80000000));
1541 sat = ov;
1542
1543 /* Store the result and condition codes. */
1544 State.regs[OP[1]] = result;
1545 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1546 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1547 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1548 | (sat ? PSW_SAT : 0));
1549
1550 /* Handle saturated results. */
1551 if (sat && s)
1552 State.regs[OP[1]] = 0x80000000;
1553 else if (sat)
1554 State.regs[OP[1]] = 0x7fffffff;
1555 trace_output (OP_IMM_REG);
1556
1557 return 4;
1558 }
1559
1560 /* satsubr reg,reg */
1561 /* zxb reg1 */
1562 int
1563 OP_80 ()
1564 {
1565 /* start-sanitize-v850e */
1566 if (OP[1] == 0)
1567 {
1568 trace_input ("zxb", OP_REG, 0);
1569
1570 State.regs[ OP[0] ] &= 0xff;
1571
1572 trace_output (OP_REG);
1573 }
1574 else
1575 /* end-sanitize-v850e */
1576 {
1577 unsigned int op0, op1, result, z, s, cy, ov, sat;
1578
1579 trace_input ("satsubr", OP_REG_REG, 0);
1580
1581 /* Compute the result. */
1582 op0 = State.regs[ OP[0] ];
1583 op1 = State.regs[ OP[1] ];
1584 result = op0 - op1;
1585
1586 /* Compute the condition codes. */
1587 z = (result == 0);
1588 s = (result & 0x80000000);
1589 cy = (result < op0);
1590 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1591 && (op1 & 0x80000000) != (result & 0x80000000));
1592 sat = ov;
1593
1594 /* Store the result and condition codes. */
1595 State.regs[OP[1]] = result;
1596 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1597 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1598 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1599 | (sat ? PSW_SAT : 0));
1600
1601 /* Handle saturated results. */
1602 if (sat && s)
1603 State.regs[OP[1]] = 0x80000000;
1604 else if (sat)
1605 State.regs[OP[1]] = 0x7fffffff;
1606 trace_output (OP_REG_REG);
1607 }
1608
1609 return 2;
1610 }
1611
1612 /* tst reg,reg */
1613 int
1614 OP_160 ()
1615 {
1616 unsigned int op0, op1, result, z, s;
1617
1618 trace_input ("tst", OP_REG_REG_CMP, 0);
1619
1620 /* Compute the result. */
1621 op0 = State.regs[ OP[0] ];
1622 op1 = State.regs[ OP[1] ];
1623 result = op0 & op1;
1624
1625 /* Compute the condition codes. */
1626 z = (result == 0);
1627 s = (result & 0x80000000);
1628
1629 /* Store the condition codes. */
1630 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1631 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1632 trace_output (OP_REG_REG_CMP);
1633
1634 return 2;
1635 }
1636
1637 /* mov reg, reg */
1638 int
1639 OP_0 ()
1640 {
1641 trace_input ("mov", OP_REG_REG_MOVE, 0);
1642
1643 State.regs[ OP[1] ] = State.regs[ OP[0] ];
1644
1645 trace_output (OP_REG_REG_MOVE);
1646
1647 return 2;
1648 }
1649
1650 /* mov sign_extend(imm5), reg */
1651 /* callt imm6 */
1652 int
1653 OP_200 ()
1654 {
1655 /* start-sanitize-v850e */
1656 if (OP[1] == 0)
1657 {
1658 unsigned long adr;
1659
1660 trace_input ("callt", OP_LOAD16, 1);
1661
1662 CTPC = PC + 2;
1663 CTPSW = PSW;
1664
1665 adr = CTBP + ((OP[3] & 0x3f) << 1);
1666
1667 PC = CTBP + load_mem (adr, 1);
1668
1669 trace_output (OP_LOAD16);
1670
1671 return 0;
1672 }
1673 else
1674 /* end-sanitize-v850e */
1675 {
1676 int value = SEXT5 (OP[0]);
1677
1678 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1679
1680 State.regs[ OP[1] ] = value;
1681
1682 trace_output (OP_IMM_REG_MOVE);
1683
1684 return 2;
1685 }
1686 }
1687
1688 /* mov imm32, reg1 */
1689 /* movea sign_extend(imm16), reg, reg */
1690 int
1691 OP_620 ()
1692 {
1693 /* start-sanitize-v850e */
1694 if (OP[1] == 0)
1695 {
1696 trace_input ("mov", OP_IMM32_REG, 4);
1697
1698 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
1699
1700 trace_output (OP_IMM32_REG);
1701
1702 return 6;
1703 }
1704 else
1705 /* end-sanitize-v850e */
1706 {
1707 trace_input ("movea", OP_IMM_REG_REG, 0);
1708
1709 State.regs[ OP[1] ] = State.regs[ OP[0] ] + SEXT16 (OP[2]);
1710
1711 trace_output (OP_IMM_REG_REG);
1712
1713 return 4;
1714 }
1715 }
1716
1717 /* dispose imm5, list12 [, reg1] */
1718 /* movhi imm16, reg, reg */
1719 int
1720 OP_640 ()
1721 {
1722 /* start-sanitize-v850e */
1723
1724 if (OP[1] == 0)
1725 {
1726 int i;
1727
1728 trace_input ("dispose", OP_PUSHPOP1, 0);
1729
1730 SP += (OP[3] & 0x3e) << 1;
1731
1732 /* Load the registers with lower number registers being retrieved from higher addresses. */
1733 for (i = 12; i--;)
1734 if ((OP[3] & (1 << type1_regs[ i ])))
1735 {
1736 State.regs[ 20 + i ] = load_mem (SP, 4);
1737 SP += 4;
1738 }
1739
1740 if ((OP[3] & 0x1f0000) != 0)
1741 {
1742 PC = State.regs[ (OP[3] >> 16) & 0x1f];
1743 return 0;
1744 }
1745
1746 trace_output (OP_PUSHPOP1);
1747 }
1748 else
1749 /* end-sanitize-v850e */
1750 {
1751 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1752
1753 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1754
1755 trace_output (OP_UIMM_REG_REG);
1756 }
1757
1758 return 4;
1759 }
1760
1761 /* sar zero_extend(imm5),reg1 */
1762 int
1763 OP_2A0 ()
1764 {
1765 unsigned int op0, op1, result, z, s, cy;
1766
1767 trace_input ("sar", OP_IMM_REG, 0);
1768 op0 = OP[0];
1769 op1 = State.regs[ OP[1] ];
1770 result = (signed)op1 >> op0;
1771
1772 /* Compute the condition codes. */
1773 z = (result == 0);
1774 s = (result & 0x80000000);
1775 cy = (op1 & (1 << (op0 - 1)));
1776
1777 /* Store the result and condition codes. */
1778 State.regs[ OP[1] ] = result;
1779 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1780 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1781 | (cy ? PSW_CY : 0));
1782 trace_output (OP_IMM_REG);
1783
1784 return 2;
1785 }
1786
1787 /* sar reg1, reg2 */
1788 int
1789 OP_A007E0 ()
1790 {
1791 unsigned int op0, op1, result, z, s, cy;
1792
1793 trace_input ("sar", OP_REG_REG, 0);
1794
1795 op0 = State.regs[ OP[0] ] & 0x1f;
1796 op1 = State.regs[ OP[1] ];
1797 result = (signed)op1 >> op0;
1798
1799 /* Compute the condition codes. */
1800 z = (result == 0);
1801 s = (result & 0x80000000);
1802 cy = (op1 & (1 << (op0 - 1)));
1803
1804 /* Store the result and condition codes. */
1805 State.regs[OP[1]] = result;
1806 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1807 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1808 | (cy ? PSW_CY : 0));
1809 trace_output (OP_REG_REG);
1810
1811 return 4;
1812 }
1813
1814 /* shl zero_extend(imm5),reg1 */
1815 int
1816 OP_2C0 ()
1817 {
1818 unsigned int op0, op1, result, z, s, cy;
1819
1820 trace_input ("shl", OP_IMM_REG, 0);
1821 op0 = OP[0];
1822 op1 = State.regs[ OP[1] ];
1823 result = op1 << op0;
1824
1825 /* Compute the condition codes. */
1826 z = (result == 0);
1827 s = (result & 0x80000000);
1828 cy = (op1 & (1 << (32 - op0)));
1829
1830 /* Store the result and condition codes. */
1831 State.regs[OP[1]] = result;
1832 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1833 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1834 | (cy ? PSW_CY : 0));
1835 trace_output (OP_IMM_REG);
1836
1837 return 2;
1838 }
1839
1840 /* shl reg1, reg2 */
1841 int
1842 OP_C007E0 ()
1843 {
1844 unsigned int op0, op1, result, z, s, cy;
1845
1846 trace_input ("shl", OP_REG_REG, 0);
1847 op0 = State.regs[ OP[0] ] & 0x1f;
1848 op1 = State.regs[ OP[1] ];
1849 result = op1 << op0;
1850
1851 /* Compute the condition codes. */
1852 z = (result == 0);
1853 s = (result & 0x80000000);
1854 cy = (op1 & (1 << (32 - op0)));
1855
1856 /* Store the result and condition codes. */
1857 State.regs[OP[1]] = result;
1858 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1859 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1860 | (cy ? PSW_CY : 0));
1861 trace_output (OP_REG_REG);
1862
1863 return 4;
1864 }
1865
1866 /* shr zero_extend(imm5),reg1 */
1867 int
1868 OP_280 ()
1869 {
1870 unsigned int op0, op1, result, z, s, cy;
1871
1872 trace_input ("shr", OP_IMM_REG, 0);
1873 op0 = OP[0];
1874 op1 = State.regs[ OP[1] ];
1875 result = op1 >> op0;
1876
1877 /* Compute the condition codes. */
1878 z = (result == 0);
1879 s = (result & 0x80000000);
1880 cy = (op1 & (1 << (op0 - 1)));
1881
1882 /* Store the result and condition codes. */
1883 State.regs[OP[1]] = result;
1884 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1885 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1886 | (cy ? PSW_CY : 0));
1887 trace_output (OP_IMM_REG);
1888
1889 return 2;
1890 }
1891
1892 /* shr reg1, reg2 */
1893 int
1894 OP_8007E0 ()
1895 {
1896 unsigned int op0, op1, result, z, s, cy;
1897
1898 trace_input ("shr", OP_REG_REG, 0);
1899 op0 = State.regs[ OP[0] ] & 0x1f;
1900 op1 = State.regs[ OP[1] ];
1901 result = op1 >> op0;
1902
1903 /* Compute the condition codes. */
1904 z = (result == 0);
1905 s = (result & 0x80000000);
1906 cy = (op1 & (1 << (op0 - 1)));
1907
1908 /* Store the result and condition codes. */
1909 State.regs[OP[1]] = result;
1910 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1911 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1912 | (cy ? PSW_CY : 0));
1913 trace_output (OP_REG_REG);
1914
1915 return 4;
1916 }
1917
1918 /* or reg, reg */
1919 int
1920 OP_100 ()
1921 {
1922 unsigned int op0, op1, result, z, s;
1923
1924 trace_input ("or", OP_REG_REG, 0);
1925
1926 /* Compute the result. */
1927 op0 = State.regs[ OP[0] ];
1928 op1 = State.regs[ OP[1] ];
1929 result = op0 | op1;
1930
1931 /* Compute the condition codes. */
1932 z = (result == 0);
1933 s = (result & 0x80000000);
1934
1935 /* Store the result and condition codes. */
1936 State.regs[OP[1]] = result;
1937 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1938 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1939 trace_output (OP_REG_REG);
1940
1941 return 2;
1942 }
1943
1944 /* ori zero_extend(imm16), reg, reg */
1945 int
1946 OP_680 ()
1947 {
1948 unsigned int op0, op1, result, z, s;
1949
1950 trace_input ("ori", OP_UIMM_REG_REG, 0);
1951 op0 = OP[2];
1952 op1 = State.regs[ OP[0] ];
1953 result = op0 | op1;
1954
1955 /* Compute the condition codes. */
1956 z = (result == 0);
1957 s = (result & 0x80000000);
1958
1959 /* Store the result and condition codes. */
1960 State.regs[OP[1]] = result;
1961 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1962 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1963 trace_output (OP_UIMM_REG_REG);
1964
1965 return 4;
1966 }
1967
1968 /* and reg, reg */
1969 int
1970 OP_140 ()
1971 {
1972 unsigned int op0, op1, result, z, s;
1973
1974 trace_input ("and", OP_REG_REG, 0);
1975
1976 /* Compute the result. */
1977 op0 = State.regs[ OP[0] ];
1978 op1 = State.regs[ OP[1] ];
1979 result = op0 & op1;
1980
1981 /* Compute the condition codes. */
1982 z = (result == 0);
1983 s = (result & 0x80000000);
1984
1985 /* Store the result and condition codes. */
1986 State.regs[OP[1]] = result;
1987 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1988 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1989 trace_output (OP_REG_REG);
1990
1991 return 2;
1992 }
1993
1994 /* andi zero_extend(imm16), reg, reg */
1995 int
1996 OP_6C0 ()
1997 {
1998 unsigned int result, z;
1999
2000 trace_input ("andi", OP_UIMM_REG_REG, 0);
2001
2002 result = OP[2] & State.regs[ OP[0] ];
2003
2004 /* Compute the condition codes. */
2005 z = (result == 0);
2006
2007 /* Store the result and condition codes. */
2008 State.regs[ OP[1] ] = result;
2009
2010 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2011 PSW |= (z ? PSW_Z : 0);
2012
2013 trace_output (OP_UIMM_REG_REG);
2014
2015 return 4;
2016 }
2017
2018 /* xor reg, reg */
2019 int
2020 OP_120 ()
2021 {
2022 unsigned int op0, op1, result, z, s;
2023
2024 trace_input ("xor", OP_REG_REG, 0);
2025
2026 /* Compute the result. */
2027 op0 = State.regs[ OP[0] ];
2028 op1 = State.regs[ OP[1] ];
2029 result = op0 ^ op1;
2030
2031 /* Compute the condition codes. */
2032 z = (result == 0);
2033 s = (result & 0x80000000);
2034
2035 /* Store the result and condition codes. */
2036 State.regs[OP[1]] = result;
2037 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2038 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2039 trace_output (OP_REG_REG);
2040
2041 return 2;
2042 }
2043
2044 /* xori zero_extend(imm16), reg, reg */
2045 int
2046 OP_6A0 ()
2047 {
2048 unsigned int op0, op1, result, z, s;
2049
2050 trace_input ("xori", OP_UIMM_REG_REG, 0);
2051 op0 = OP[2];
2052 op1 = State.regs[ OP[0] ];
2053 result = op0 ^ op1;
2054
2055 /* Compute the condition codes. */
2056 z = (result == 0);
2057 s = (result & 0x80000000);
2058
2059 /* Store the result and condition codes. */
2060 State.regs[OP[1]] = result;
2061 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2062 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2063 trace_output (OP_UIMM_REG_REG);
2064
2065 return 4;
2066 }
2067
2068 /* not reg1, reg2 */
2069 int
2070 OP_20 ()
2071 {
2072 unsigned int op0, result, z, s;
2073
2074 trace_input ("not", OP_REG_REG_MOVE, 0);
2075 /* Compute the result. */
2076 op0 = State.regs[ OP[0] ];
2077 result = ~op0;
2078
2079 /* Compute the condition codes. */
2080 z = (result == 0);
2081 s = (result & 0x80000000);
2082
2083 /* Store the result and condition codes. */
2084 State.regs[OP[1]] = result;
2085 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2086 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2087 trace_output (OP_REG_REG_MOVE);
2088
2089 return 2;
2090 }
2091
2092 /* set1 */
2093 int
2094 OP_7C0 ()
2095 {
2096 unsigned int op0, op1, op2;
2097 int temp;
2098
2099 trace_input ("set1", OP_BIT, 0);
2100 op0 = State.regs[ OP[0] ];
2101 op1 = OP[1] & 0x7;
2102 temp = SEXT16 (OP[2]);
2103 op2 = temp;
2104 temp = load_mem (op0 + op2, 1);
2105 PSW &= ~PSW_Z;
2106 if ((temp & (1 << op1)) == 0)
2107 PSW |= PSW_Z;
2108 temp |= (1 << op1);
2109 store_mem (op0 + op2, 1, temp);
2110 trace_output (OP_BIT);
2111
2112 return 4;
2113 }
2114
2115 /* not1 */
2116 int
2117 OP_47C0 ()
2118 {
2119 unsigned int op0, op1, op2;
2120 int temp;
2121
2122 trace_input ("not1", OP_BIT, 0);
2123 op0 = State.regs[ OP[0] ];
2124 op1 = OP[1] & 0x7;
2125 temp = SEXT16 (OP[2]);
2126 op2 = temp;
2127 temp = load_mem (op0 + op2, 1);
2128 PSW &= ~PSW_Z;
2129 if ((temp & (1 << op1)) == 0)
2130 PSW |= PSW_Z;
2131 temp ^= (1 << op1);
2132 store_mem (op0 + op2, 1, temp);
2133 trace_output (OP_BIT);
2134
2135 return 4;
2136 }
2137
2138 /* clr1 */
2139 int
2140 OP_87C0 ()
2141 {
2142 unsigned int op0, op1, op2;
2143 int temp;
2144
2145 trace_input ("clr1", OP_BIT, 0);
2146 op0 = State.regs[ OP[0] ];
2147 op1 = OP[1] & 0x7;
2148 temp = SEXT16 (OP[2]);
2149 op2 = temp;
2150 temp = load_mem (op0 + op2, 1);
2151 PSW &= ~PSW_Z;
2152 if ((temp & (1 << op1)) == 0)
2153 PSW |= PSW_Z;
2154 temp &= ~(1 << op1);
2155 store_mem (op0 + op2, 1, temp);
2156 trace_output (OP_BIT);
2157
2158 return 4;
2159 }
2160
2161 /* tst1 */
2162 int
2163 OP_C7C0 ()
2164 {
2165 unsigned int op0, op1, op2;
2166 int temp;
2167
2168 trace_input ("tst1", OP_BIT, 0);
2169 op0 = State.regs[ OP[0] ];
2170 op1 = OP[1] & 0x7;
2171 temp = SEXT16 (OP[2]);
2172 op2 = temp;
2173 temp = load_mem (op0 + op2, 1);
2174 PSW &= ~PSW_Z;
2175 if ((temp & (1 << op1)) == 0)
2176 PSW |= PSW_Z;
2177 trace_output (OP_BIT);
2178
2179 return 4;
2180 }
2181
2182 /* breakpoint */
2183 int
2184 OP_FFFF ()
2185 {
2186 State.exception = SIGTRAP;
2187 return -4;
2188 }
2189
2190 /* di */
2191 int
2192 OP_16007E0 ()
2193 {
2194 trace_input ("di", OP_NONE, 0);
2195 PSW |= PSW_ID;
2196 trace_output (OP_NONE);
2197
2198 return 4;
2199 }
2200
2201 /* ei */
2202 int
2203 OP_16087E0 ()
2204 {
2205 trace_input ("ei", OP_NONE, 0);
2206 PSW &= ~PSW_ID;
2207 trace_output (OP_NONE);
2208
2209 return 4;
2210 }
2211
2212 /* halt */
2213 int
2214 OP_12007E0 ()
2215 {
2216 trace_input ("halt", OP_NONE, 0);
2217 /* FIXME this should put processor into a mode where NMI still handled */
2218 State.exception = SIGQUIT;
2219 trace_output (OP_NONE);
2220
2221 return 4;
2222 }
2223
2224 /* reti */
2225 int
2226 OP_14007E0 ()
2227 {
2228 trace_input ("reti", OP_NONE, 0);
2229 trace_output (OP_NONE);
2230
2231 /* Restore for NMI if only NP on, otherwise is interrupt or exception. */
2232 if ((PSW & (PSW_NP | PSW_EP)) == PSW_NP)
2233 {
2234 PC = FEPC - 4;
2235 PSW = FEPSW;
2236 }
2237 else
2238 {
2239 PC = EIPC - 4;
2240 PSW = EIPSW;
2241 }
2242
2243 return 0;
2244 }
2245
2246 /* trap */
2247 int
2248 OP_10007E0 ()
2249 {
2250 trace_input ("trap", OP_TRAP, 0);
2251 trace_output (OP_TRAP);
2252
2253 /* Trap 31 is used for simulating OS I/O functions */
2254
2255 if (OP[0] == 31)
2256 {
2257 int save_errno = errno;
2258 errno = 0;
2259
2260 /* Registers passed to trap 0 */
2261
2262 #define FUNC State.regs[6] /* function number, return value */
2263 #define PARM1 State.regs[7] /* optional parm 1 */
2264 #define PARM2 State.regs[8] /* optional parm 2 */
2265 #define PARM3 State.regs[9] /* optional parm 3 */
2266
2267 /* Registers set by trap 0 */
2268
2269 #define RETVAL State.regs[10] /* return value */
2270 #define RETERR State.regs[11] /* return error code */
2271
2272 /* Turn a pointer in a register into a pointer into real memory. */
2273
2274 #define MEMPTR(x) (map (x))
2275
2276 switch (FUNC)
2277 {
2278
2279 #ifdef HAVE_FORK
2280 #ifdef SYS_fork
2281 case SYS_fork:
2282 RETVAL = fork ();
2283 break;
2284 #endif
2285 #endif
2286
2287 #ifdef HAVE_EXECVE
2288 #ifdef SYS_execv
2289 case SYS_execve:
2290 {
2291 char *path = fetch_str (simulator, PARM1);
2292 char **argv = fetch_argv (simulator, PARM2);
2293 char **envp = fetch_argv (simulator, PARM3);
2294 RETVAL = execve (path, argv, envp);
2295 zfree (path);
2296 freeargv (argv);
2297 freeargv (envp);
2298 break;
2299 }
2300 #endif
2301 #endif
2302
2303 #if HAVE_EXECV
2304 #ifdef SYS_execv
2305 case SYS_execv:
2306 {
2307 char *path = fetch_str (simulator, PARM1);
2308 char **argv = fetch_argv (simulator, PARM2);
2309 RETVAL = execv (path, argv);
2310 zfree (path);
2311 freeargv (argv);
2312 break;
2313 }
2314 #endif
2315 #endif
2316
2317 #if 0
2318 #ifdef SYS_pipe
2319 case SYS_pipe:
2320 {
2321 reg_t buf;
2322 int host_fd[2];
2323
2324 buf = PARM1;
2325 RETVAL = pipe (host_fd);
2326 SW (buf, host_fd[0]);
2327 buf += sizeof(uint16);
2328 SW (buf, host_fd[1]);
2329 }
2330 break;
2331 #endif
2332 #endif
2333
2334 #if 0
2335 #ifdef SYS_wait
2336 case SYS_wait:
2337 {
2338 int status;
2339
2340 RETVAL = wait (&status);
2341 SW (PARM1, status);
2342 }
2343 break;
2344 #endif
2345 #endif
2346
2347 #ifdef SYS_read
2348 case SYS_read:
2349 {
2350 char *buf = zalloc (PARM3);
2351 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
2352 sim_write (simulator, PARM2, buf, PARM3);
2353 zfree (buf);
2354 break;
2355 }
2356 #endif
2357
2358 #ifdef SYS_write
2359 case SYS_write:
2360 {
2361 char *buf = zalloc (PARM3);
2362 sim_read (simulator, PARM2, buf, PARM3);
2363 if (PARM1 == 1)
2364 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
2365 else
2366 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
2367 zfree (buf);
2368 break;
2369 }
2370 #endif
2371
2372 #ifdef SYS_lseek
2373 case SYS_lseek:
2374 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
2375 break;
2376 #endif
2377
2378 #ifdef SYS_close
2379 case SYS_close:
2380 RETVAL = sim_io_close (simulator, PARM1);
2381 break;
2382 #endif
2383
2384 #ifdef SYS_open
2385 case SYS_open:
2386 {
2387 char *buf = fetch_str (simulator, PARM1);
2388 RETVAL = sim_io_open (simulator, buf, PARM2);
2389 zfree (buf);
2390 break;
2391 }
2392 #endif
2393
2394 #ifdef SYS_exit
2395 case SYS_exit:
2396 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
2397 State.exception = PARM1 & 0xffff; /* get signal encoded by kill */
2398 else if (PARM1 == 0xdead)
2399 State.exception = SIGABRT; /* old libraries */
2400 else
2401 State.exception = SIG_V850_EXIT; /* PARM1 has exit status encoded */
2402 break;
2403 #endif
2404
2405 #if !defined(__GO32__) && !defined(_WIN32)
2406 #ifdef SYS_stat
2407 case SYS_stat: /* added at hmsi */
2408 /* stat system call */
2409 {
2410 struct stat host_stat;
2411 reg_t buf;
2412 char *path = fetch_str (simulator, PARM1);
2413
2414 RETVAL = stat (path, &host_stat);
2415
2416 zfree (path);
2417 buf = PARM2;
2418
2419 /* Just wild-assed guesses. */
2420 store_mem (buf, 2, host_stat.st_dev);
2421 store_mem (buf + 2, 2, host_stat.st_ino);
2422 store_mem (buf + 4, 4, host_stat.st_mode);
2423 store_mem (buf + 8, 2, host_stat.st_nlink);
2424 store_mem (buf + 10, 2, host_stat.st_uid);
2425 store_mem (buf + 12, 2, host_stat.st_gid);
2426 store_mem (buf + 14, 2, host_stat.st_rdev);
2427 store_mem (buf + 16, 4, host_stat.st_size);
2428 store_mem (buf + 20, 4, host_stat.st_atime);
2429 store_mem (buf + 28, 4, host_stat.st_mtime);
2430 store_mem (buf + 36, 4, host_stat.st_ctime);
2431 }
2432 break;
2433 #endif
2434 #endif
2435
2436 #ifdef HAVE_CHOWN
2437 #ifdef SYS_chown
2438 case SYS_chown:
2439 {
2440 char *path = fetch_str (simulator, PARM1);
2441 RETVAL = chown (path, PARM2, PARM3);
2442 zfree (path);
2443 }
2444 break;
2445 #endif
2446 #endif
2447
2448 #if HAVE_CHMOD
2449 #ifdef SYS_chmod
2450 case SYS_chmod:
2451 {
2452 char *path = fetch_str (simulator, PARM1);
2453 RETVAL = chmod (path, PARM2);
2454 zfree (path);
2455 }
2456 break;
2457 #endif
2458 #endif
2459
2460 #ifdef SYS_time
2461 #if HAVE_TIME
2462 case SYS_time:
2463 {
2464 time_t now;
2465 RETVAL = time (&now);
2466 store_mem (PARM1, 4, now);
2467 }
2468 break;
2469 #endif
2470 #endif
2471
2472 #if !defined(__GO32__) && !defined(_WIN32)
2473 #ifdef SYS_times
2474 case SYS_times:
2475 {
2476 struct tms tms;
2477 RETVAL = times (&tms);
2478 store_mem (PARM1, 4, tms.tms_utime);
2479 store_mem (PARM1 + 4, 4, tms.tms_stime);
2480 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2481 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2482 break;
2483 }
2484 #endif
2485 #endif
2486
2487 #ifdef SYS_gettimeofday
2488 #if !defined(__GO32__) && !defined(_WIN32)
2489 case SYS_gettimeofday:
2490 {
2491 struct timeval t;
2492 struct timezone tz;
2493 RETVAL = gettimeofday (&t, &tz);
2494 store_mem (PARM1, 4, t.tv_sec);
2495 store_mem (PARM1 + 4, 4, t.tv_usec);
2496 store_mem (PARM2, 4, tz.tz_minuteswest);
2497 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2498 break;
2499 }
2500 #endif
2501 #endif
2502
2503 #ifdef SYS_utime
2504 #if HAVE_UTIME
2505 case SYS_utime:
2506 {
2507 /* Cast the second argument to void *, to avoid type mismatch
2508 if a prototype is present. */
2509 sim_io_error (simulator, "Utime not supported");
2510 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
2511 }
2512 break;
2513 #endif
2514 #endif
2515
2516 default:
2517 abort ();
2518 }
2519 RETERR = errno;
2520 errno = save_errno;
2521
2522 return 4;
2523 }
2524 else
2525 { /* Trap 0 -> 30 */
2526 EIPC = PC + 4;
2527 EIPSW = PSW;
2528 /* Mask out EICC */
2529 ECR &= 0xffff0000;
2530 ECR |= 0x40 + OP[0];
2531 /* Flag that we are now doing exception processing. */
2532 PSW |= PSW_EP | PSW_ID;
2533 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
2534
2535 return 0;
2536 }
2537 }
2538
2539 /* ldsr, reg,reg */
2540 int
2541 OP_2007E0 ()
2542 {
2543 trace_input ("ldsr", OP_LDSR, 0);
2544
2545 State.sregs[ OP[1] ] = State.regs[ OP[0] ];
2546
2547 trace_output (OP_LDSR);
2548
2549 return 4;
2550 }
2551
2552 /* stsr */
2553 int
2554 OP_4007E0 ()
2555 {
2556 trace_input ("stsr", OP_STSR, 0);
2557
2558 State.regs[ OP[1] ] = State.sregs[ OP[0] ];
2559
2560 trace_output (OP_STSR);
2561
2562 return 4;
2563 }
2564
2565 /* tst1 reg2, [reg1] */
2566 int
2567 OP_E607E0 (void)
2568 {
2569 int temp;
2570
2571 trace_input ("tst1", OP_BIT_LOAD, 1);
2572
2573 temp = load_mem (State.regs[ OP[0] ], 1);
2574
2575 PSW &= ~PSW_Z;
2576 if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
2577 PSW |= PSW_Z;
2578
2579 trace_output (OP_BIT_LOAD);
2580
2581 return 4;
2582 }
2583
2584 /* mulu reg1, reg2, reg3 */
2585 int
2586 OP_22207E0 (void)
2587 {
2588 trace_input ("mulu", OP_REG_REG_REG, 0);
2589
2590 Multiply64 (false, State.regs[ OP[0] ]);
2591
2592 trace_output (OP_REG_REG_REG);
2593
2594 return 4;
2595 }
2596
2597 /* start-sanitize-v850e */
2598
2599 #define BIT_CHANGE_OP( name, binop ) \
2600 unsigned int bit; \
2601 unsigned int temp; \
2602 \
2603 trace_input (name, OP_BIT_CHANGE, 0); \
2604 \
2605 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
2606 temp = load_mem (State.regs[ OP[0] ], 1); \
2607 \
2608 PSW &= ~PSW_Z; \
2609 if ((temp & bit) == 0) \
2610 PSW |= PSW_Z; \
2611 temp binop bit; \
2612 \
2613 store_mem (State.regs[ OP[0] ], 1, temp); \
2614 \
2615 trace_output (OP_BIT_CHANGE); \
2616 \
2617 return 4;
2618
2619 /* clr1 reg2, [reg1] */
2620 int
2621 OP_E407E0 (void)
2622 {
2623 BIT_CHANGE_OP ("clr1", &= ~ );
2624 }
2625
2626 /* not1 reg2, [reg1] */
2627 int
2628 OP_E207E0 (void)
2629 {
2630 BIT_CHANGE_OP ("not1", ^= );
2631 }
2632
2633 /* set1 */
2634 int
2635 OP_E007E0 (void)
2636 {
2637 BIT_CHANGE_OP ("set1", |= );
2638 }
2639
2640 /* sasf */
2641 int
2642 OP_20007E0 (void)
2643 {
2644 trace_input ("sasf", OP_EX1, 0);
2645
2646 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2647
2648 trace_output (OP_EX1);
2649
2650 return 4;
2651 }
2652 /* end-sanitize-v850e */
2653
2654 /* start-sanitize-v850eq */
2655 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2656 static void
2657 divun
2658 (
2659 unsigned int N,
2660 unsigned long int als,
2661 unsigned long int sfi,
2662 unsigned long int * quotient_ptr,
2663 unsigned long int * remainder_ptr,
2664 boolean * overflow_ptr
2665 )
2666 {
2667 unsigned long ald = sfi >> (N - 1);
2668 unsigned long alo = als;
2669 unsigned int Q = 1;
2670 unsigned int C;
2671 unsigned int S = 0;
2672 unsigned int i;
2673 unsigned int R1 = 1;
2674 unsigned int DBZ = (als == 0) ? 1 : 0;
2675 unsigned long alt = Q ? ~als : als;
2676
2677 /* 1st Loop */
2678 alo = ald + alt + Q;
2679 C = (((alt >> 31) & (ald >> 31))
2680 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2681 C = C ^ Q;
2682 Q = ~(C ^ S) & 1;
2683 R1 = (alo == 0) ? 0 : (R1 & Q);
2684 if ((S ^ (alo>>31)) && !C)
2685 {
2686 DBZ = 1;
2687 }
2688 S = alo >> 31;
2689 sfi = (sfi << (32-N+1)) | Q;
2690 ald = (alo << 1) | (sfi >> 31);
2691
2692 /* 2nd - N-1th Loop */
2693 for (i = 2; i < N; i++)
2694 {
2695 alt = Q ? ~als : als;
2696 alo = ald + alt + Q;
2697 C = (((alt >> 31) & (ald >> 31))
2698 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2699 C = C ^ Q;
2700 Q = ~(C ^ S) & 1;
2701 R1 = (alo == 0) ? 0 : (R1 & Q);
2702 if ((S ^ (alo>>31)) && !C && !DBZ)
2703 {
2704 DBZ = 1;
2705 }
2706 S = alo >> 31;
2707 sfi = (sfi << 1) | Q;
2708 ald = (alo << 1) | (sfi >> 31);
2709 }
2710
2711 /* Nth Loop */
2712 alt = Q ? ~als : als;
2713 alo = ald + alt + Q;
2714 C = (((alt >> 31) & (ald >> 31))
2715 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2716 C = C ^ Q;
2717 Q = ~(C ^ S) & 1;
2718 R1 = (alo == 0) ? 0 : (R1 & Q);
2719 if ((S ^ (alo>>31)) && !C)
2720 {
2721 DBZ = 1;
2722 }
2723
2724 * quotient_ptr = (sfi << 1) | Q;
2725 * remainder_ptr = Q ? alo : (alo + als);
2726 * overflow_ptr = DBZ | R1;
2727 }
2728
2729 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2730 static void
2731 divn
2732 (
2733 unsigned int N,
2734 unsigned long int als,
2735 unsigned long int sfi,
2736 signed long int * quotient_ptr,
2737 signed long int * remainder_ptr,
2738 boolean * overflow_ptr
2739 )
2740 {
2741 unsigned long ald = (signed long) sfi >> (N - 1);
2742 unsigned long alo = als;
2743 unsigned int SS = als >> 31;
2744 unsigned int SD = sfi >> 31;
2745 unsigned int R1 = 1;
2746 unsigned int OV;
2747 unsigned int DBZ = als == 0 ? 1 : 0;
2748 unsigned int Q = ~(SS ^ SD) & 1;
2749 unsigned int C;
2750 unsigned int S;
2751 unsigned int i;
2752 unsigned long alt = Q ? ~als : als;
2753
2754
2755 /* 1st Loop */
2756
2757 alo = ald + alt + Q;
2758 C = (((alt >> 31) & (ald >> 31))
2759 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2760 Q = C ^ SS;
2761 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2762 S = alo >> 31;
2763 sfi = (sfi << (32-N+1)) | Q;
2764 ald = (alo << 1) | (sfi >> 31);
2765 if ((alo >> 31) ^ (ald >> 31))
2766 {
2767 DBZ = 1;
2768 }
2769
2770 /* 2nd - N-1th Loop */
2771
2772 for (i = 2; i < N; i++)
2773 {
2774 alt = Q ? ~als : als;
2775 alo = ald + alt + Q;
2776 C = (((alt >> 31) & (ald >> 31))
2777 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2778 Q = C ^ SS;
2779 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2780 S = alo >> 31;
2781 sfi = (sfi << 1) | Q;
2782 ald = (alo << 1) | (sfi >> 31);
2783 if ((alo >> 31) ^ (ald >> 31))
2784 {
2785 DBZ = 1;
2786 }
2787 }
2788
2789 /* Nth Loop */
2790 alt = Q ? ~als : als;
2791 alo = ald + alt + Q;
2792 C = (((alt >> 31) & (ald >> 31))
2793 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2794 Q = C ^ SS;
2795 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2796 sfi = (sfi << (32-N+1));
2797 ald = alo;
2798
2799 /* End */
2800 if (alo != 0)
2801 {
2802 alt = Q ? ~als : als;
2803 alo = ald + alt + Q;
2804 }
2805 R1 = R1 & ((~alo >> 31) ^ SD);
2806 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2807 if (N != 32)
2808 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2809 else
2810 ald = sfi = sfi | Q;
2811
2812 OV = DBZ | ((alo == 0) ? 0 : R1);
2813
2814 * remainder_ptr = alo;
2815
2816 /* Adj */
2817 if (((alo != 0) && ((SS ^ SD) ^ R1))
2818 || ((alo == 0) && (SS ^ R1)))
2819 alo = ald + 1;
2820 else
2821 alo = ald;
2822
2823 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2824
2825 * quotient_ptr = alo;
2826 * overflow_ptr = OV;
2827 }
2828
2829 /* sdivun imm5, reg1, reg2, reg3 */
2830 int
2831 OP_1C207E0 (void)
2832 {
2833 unsigned long int quotient;
2834 unsigned long int remainder;
2835 unsigned long int divide_by;
2836 unsigned long int divide_this;
2837 boolean overflow = false;
2838 unsigned int imm5;
2839
2840 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2841
2842 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2843
2844 divide_by = State.regs[ OP[0] ];
2845 divide_this = State.regs[ OP[1] ] << imm5;
2846
2847 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2848
2849 State.regs[ OP[1] ] = quotient;
2850 State.regs[ OP[2] >> 11 ] = remainder;
2851
2852 /* Set condition codes. */
2853 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2854
2855 if (overflow) PSW |= PSW_OV;
2856 if (quotient == 0) PSW |= PSW_Z;
2857 if (quotient & 0x80000000) PSW |= PSW_S;
2858
2859 trace_output (OP_IMM_REG_REG_REG);
2860
2861 return 4;
2862 }
2863
2864 /* sdivn imm5, reg1, reg2, reg3 */
2865 int
2866 OP_1C007E0 (void)
2867 {
2868 signed long int quotient;
2869 signed long int remainder;
2870 signed long int divide_by;
2871 signed long int divide_this;
2872 boolean overflow = false;
2873 unsigned int imm5;
2874
2875 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2876
2877 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2878
2879 divide_by = State.regs[ OP[0] ];
2880 divide_this = State.regs[ OP[1] ] << imm5;
2881
2882 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2883
2884 State.regs[ OP[1] ] = quotient;
2885 State.regs[ OP[2] >> 11 ] = remainder;
2886
2887 /* Set condition codes. */
2888 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2889
2890 if (overflow) PSW |= PSW_OV;
2891 if (quotient == 0) PSW |= PSW_Z;
2892 if (quotient < 0) PSW |= PSW_S;
2893
2894 trace_output (OP_IMM_REG_REG_REG);
2895
2896 return 4;
2897 }
2898
2899 /* sdivhun imm5, reg1, reg2, reg3 */
2900 int
2901 OP_18207E0 (void)
2902 {
2903 unsigned long int quotient;
2904 unsigned long int remainder;
2905 unsigned long int divide_by;
2906 unsigned long int divide_this;
2907 boolean overflow = false;
2908 unsigned int imm5;
2909
2910 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2911
2912 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2913
2914 divide_by = State.regs[ OP[0] ] & 0xffff;
2915 divide_this = State.regs[ OP[1] ] << imm5;
2916
2917 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2918
2919 State.regs[ OP[1] ] = quotient;
2920 State.regs[ OP[2] >> 11 ] = remainder;
2921
2922 /* Set condition codes. */
2923 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2924
2925 if (overflow) PSW |= PSW_OV;
2926 if (quotient == 0) PSW |= PSW_Z;
2927 if (quotient & 0x80000000) PSW |= PSW_S;
2928
2929 trace_output (OP_IMM_REG_REG_REG);
2930
2931 return 4;
2932 }
2933
2934 /* sdivhn imm5, reg1, reg2, reg3 */
2935 int
2936 OP_18007E0 (void)
2937 {
2938 signed long int quotient;
2939 signed long int remainder;
2940 signed long int divide_by;
2941 signed long int divide_this;
2942 boolean overflow = false;
2943 unsigned int imm5;
2944
2945 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2946
2947 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2948
2949 divide_by = SEXT16 (State.regs[ OP[0] ]);
2950 divide_this = State.regs[ OP[1] ] << imm5;
2951
2952 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2953
2954 State.regs[ OP[1] ] = quotient;
2955 State.regs[ OP[2] >> 11 ] = remainder;
2956
2957 /* Set condition codes. */
2958 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2959
2960 if (overflow) PSW |= PSW_OV;
2961 if (quotient == 0) PSW |= PSW_Z;
2962 if (quotient < 0) PSW |= PSW_S;
2963
2964 trace_output (OP_IMM_REG_REG_REG);
2965
2966 return 4;
2967 }
2968 /* end-sanitize-v850eq */
2969
2970 /* start-sanitize-v850e */
2971 /* divu reg1, reg2, reg3 */
2972 int
2973 OP_2C207E0 (void)
2974 {
2975 unsigned long int quotient;
2976 unsigned long int remainder;
2977 unsigned long int divide_by;
2978 unsigned long int divide_this;
2979 boolean overflow = false;
2980
2981 if ((OP[3] & 0x3c0000) == 0)
2982 {
2983 trace_input ("divu", OP_REG_REG_REG, 0);
2984
2985 /* Compute the result. */
2986
2987 divide_by = State.regs[ OP[0] ];
2988 divide_this = State.regs[ OP[1] ];
2989
2990 if (divide_by == 0)
2991 {
2992 overflow = true;
2993 divide_by = 1;
2994 }
2995
2996 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2997 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2998
2999 /* Set condition codes. */
3000 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3001
3002 if (overflow) PSW |= PSW_OV;
3003 if (quotient == 0) PSW |= PSW_Z;
3004 if (quotient & 0x80000000) PSW |= PSW_S;
3005
3006 trace_output (OP_REG_REG_REG);
3007 }
3008 /* start-sanitize-v850eq */
3009 /* divun imm5, reg1, reg2, reg3 */
3010 else
3011 {
3012 unsigned int imm5;
3013
3014 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
3015
3016 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3017
3018 divide_by = State.regs[ OP[0] ];
3019 divide_this = State.regs[ OP[1] ];
3020
3021 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3022
3023 State.regs[ OP[1] ] = quotient;
3024 State.regs[ OP[2] >> 11 ] = remainder;
3025
3026 /* Set condition codes. */
3027 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3028
3029 if (overflow) PSW |= PSW_OV;
3030 if (quotient == 0) PSW |= PSW_Z;
3031 if (quotient & 0x80000000) PSW |= PSW_S;
3032
3033 trace_output (OP_IMM_REG_REG_REG);
3034 }
3035 /* end-sanitize-v850eq */
3036
3037 return 4;
3038 }
3039
3040 /* div reg1, reg2, reg3 */
3041 int
3042 OP_2C007E0 (void)
3043 {
3044 signed long int quotient;
3045 signed long int remainder;
3046 signed long int divide_by;
3047 signed long int divide_this;
3048 boolean overflow = false;
3049
3050 if ((OP[3] & 0x3c0000) == 0)
3051 {
3052 trace_input ("div", OP_REG_REG_REG, 0);
3053
3054 /* Compute the result. */
3055
3056 divide_by = State.regs[ OP[0] ];
3057 divide_this = State.regs[ OP[1] ];
3058
3059 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3060 {
3061 overflow = true;
3062 divide_by = 1;
3063 }
3064
3065 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3066 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3067
3068 /* Set condition codes. */
3069 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3070
3071 if (overflow) PSW |= PSW_OV;
3072 if (quotient == 0) PSW |= PSW_Z;
3073 if (quotient < 0) PSW |= PSW_S;
3074
3075 trace_output (OP_REG_REG_REG);
3076 }
3077 /* start-sanitize-v850eq */
3078 /* divn imm5, reg1, reg2, reg3 */
3079 else
3080 {
3081 unsigned int imm5;
3082
3083 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
3084
3085 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3086
3087 divide_by = State.regs[ OP[0] ];
3088 divide_this = State.regs[ OP[1] ];
3089
3090 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3091
3092 State.regs[ OP[1] ] = quotient;
3093 State.regs[ OP[2] >> 11 ] = remainder;
3094
3095 /* Set condition codes. */
3096 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3097
3098 if (overflow) PSW |= PSW_OV;
3099 if (quotient == 0) PSW |= PSW_Z;
3100 if (quotient < 0) PSW |= PSW_S;
3101
3102 trace_output (OP_IMM_REG_REG_REG);
3103 }
3104 /* end-sanitize-v850eq */
3105
3106 return 4;
3107 }
3108
3109 /* divhu reg1, reg2, reg3 */
3110 int
3111 OP_28207E0 (void)
3112 {
3113 unsigned long int quotient;
3114 unsigned long int remainder;
3115 unsigned long int divide_by;
3116 unsigned long int divide_this;
3117 boolean overflow = false;
3118
3119 if ((OP[3] & 0x3c0000) == 0)
3120 {
3121 trace_input ("divhu", OP_REG_REG_REG, 0);
3122
3123 /* Compute the result. */
3124
3125 divide_by = State.regs[ OP[0] ] & 0xffff;
3126 divide_this = State.regs[ OP[1] ];
3127
3128 if (divide_by == 0)
3129 {
3130 overflow = true;
3131 divide_by = 1;
3132 }
3133
3134 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3135 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3136
3137 /* Set condition codes. */
3138 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3139
3140 if (overflow) PSW |= PSW_OV;
3141 if (quotient == 0) PSW |= PSW_Z;
3142 if (quotient & 0x80000000) PSW |= PSW_S;
3143
3144 trace_output (OP_REG_REG_REG);
3145 }
3146 /* start-sanitize-v850eq */
3147 /* divhun imm5, reg1, reg2, reg3 */
3148 else
3149 {
3150 unsigned int imm5;
3151
3152 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
3153
3154 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3155
3156 divide_by = State.regs[ OP[0] ] & 0xffff;
3157 divide_this = State.regs[ OP[1] ];
3158
3159 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3160
3161 State.regs[ OP[1] ] = quotient;
3162 State.regs[ OP[2] >> 11 ] = remainder;
3163
3164 /* Set condition codes. */
3165 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3166
3167 if (overflow) PSW |= PSW_OV;
3168 if (quotient == 0) PSW |= PSW_Z;
3169 if (quotient & 0x80000000) PSW |= PSW_S;
3170
3171 trace_output (OP_IMM_REG_REG_REG);
3172 }
3173 /* end-sanitize-v850eq */
3174
3175 return 4;
3176 }
3177
3178 /* divh reg1, reg2, reg3 */
3179 int
3180 OP_28007E0 (void)
3181 {
3182 signed long int quotient;
3183 signed long int remainder;
3184 signed long int divide_by;
3185 signed long int divide_this;
3186 boolean overflow = false;
3187
3188 if ((OP[3] & 0x3c0000) == 0)
3189 {
3190 trace_input ("divh", OP_REG_REG_REG, 0);
3191
3192 /* Compute the result. */
3193
3194 divide_by = State.regs[ OP[0] ];
3195 divide_this = SEXT16 (State.regs[ OP[1] ]);
3196
3197 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3198 {
3199 overflow = true;
3200 divide_by = 1;
3201 }
3202
3203 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3204 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3205
3206 /* Set condition codes. */
3207 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3208
3209 if (overflow) PSW |= PSW_OV;
3210 if (quotient == 0) PSW |= PSW_Z;
3211 if (quotient < 0) PSW |= PSW_S;
3212
3213 trace_output (OP_REG_REG_REG);
3214 }
3215 /* start-sanitize-v850eq */
3216 /* divhn imm5, reg1, reg2, reg3 */
3217 else
3218 {
3219 unsigned int imm5;
3220
3221 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
3222
3223 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3224
3225 divide_by = SEXT16 (State.regs[ OP[0] ]);
3226 divide_this = State.regs[ OP[1] ];
3227
3228 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3229
3230 State.regs[ OP[1] ] = quotient;
3231 State.regs[ OP[2] >> 11 ] = remainder;
3232
3233 /* Set condition codes. */
3234 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3235
3236 if (overflow) PSW |= PSW_OV;
3237 if (quotient == 0) PSW |= PSW_Z;
3238 if (quotient < 0) PSW |= PSW_S;
3239
3240 trace_output (OP_IMM_REG_REG_REG);
3241 }
3242 /* end-sanitize-v850eq */
3243
3244 return 4;
3245 }
3246
3247 /* mulu imm9, reg2, reg3 */
3248 int
3249 OP_24207E0 (void)
3250 {
3251 trace_input ("mulu", OP_IMM_REG_REG, 0);
3252
3253 Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
3254
3255 trace_output (OP_IMM_REG_REG);
3256
3257 return 4;
3258 }
3259
3260 /* mul imm9, reg2, reg3 */
3261 int
3262 OP_24007E0 (void)
3263 {
3264 trace_input ("mul", OP_IMM_REG_REG, 0);
3265
3266 Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
3267
3268 trace_output (OP_IMM_REG_REG);
3269
3270 return 4;
3271 }
3272
3273 /* cmov imm5, reg2, reg3 */
3274 int
3275 OP_30007E0 (void)
3276 {
3277 trace_input ("cmov", OP_IMM_REG_REG, 0);
3278
3279 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? SEXT5( OP[0] ) : State.regs[ OP[1] ];
3280
3281 trace_output (OP_IMM_REG_REG);
3282
3283 return 4;
3284
3285 }
3286
3287 /* ctret */
3288 int
3289 OP_14407E0 (void)
3290 {
3291 trace_input ("ctret", OP_NONE, 0);
3292
3293 PC = CTPC;
3294 PSW = CTPSW;
3295
3296 trace_output (OP_NONE);
3297
3298 return 0;
3299 }
3300
3301 /* hsw */
3302 int
3303 OP_34407E0 (void)
3304 {
3305 unsigned long value;
3306
3307 trace_input ("hsw", OP_REG_REG3, 0);
3308
3309 value = State.regs[ OP[ 1 ] ];
3310 value >>= 16;
3311 value |= (State.regs[ OP[ 1 ] ] << 16);
3312
3313 State.regs[ OP[2] >> 11 ] = value;
3314
3315 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3316
3317 if (value == 0) PSW |= PSW_Z;
3318 if (value & 0x80000000) PSW |= PSW_S;
3319 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
3320
3321 trace_output (OP_REG_REG3);
3322
3323 return 4;
3324 }
3325
3326 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
3327
3328 /* bsw */
3329 int
3330 OP_34007E0 (void)
3331 {
3332 unsigned long value;
3333
3334 trace_input ("bsw", OP_REG_REG3, 0);
3335
3336 value = State.regs[ OP[ 1 ] ];
3337 value >>= 24;
3338 value |= (State.regs[ OP[ 1 ] ] << 24);
3339 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0x00ff0000);
3340 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x0000ff00);
3341
3342 State.regs[ OP[2] >> 11 ] = value;
3343
3344 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3345
3346 if (value == 0) PSW |= PSW_Z;
3347 if (value & 0x80000000) PSW |= PSW_S;
3348 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
3349
3350 trace_output (OP_REG_REG3);
3351
3352 return 4;
3353 }
3354
3355 /* bsh */
3356 int
3357 OP_34207E0 (void)
3358 {
3359 unsigned long value;
3360
3361 trace_input ("bsh", OP_REG_REG3, 0);
3362
3363 value = State.regs[ OP[ 1 ] ];
3364 value >>= 8;
3365 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0xff00ff00);
3366 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x000000ff);
3367
3368 State.regs[ OP[2] >> 11 ] = value;
3369
3370 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3371
3372 if (value == 0) PSW |= PSW_Z;
3373 if (value & 0x80000000) PSW |= PSW_S;
3374 if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
3375
3376 trace_output (OP_REG_REG3);
3377
3378 return 4;
3379 }
3380
3381 /* pushml list18 */
3382 /* ld.hu */
3383 int
3384 OP_107E0 (void)
3385 {
3386 if (OP[ 1 ] == 0)
3387 {
3388 int i;
3389
3390 trace_input ("pushml", OP_PUSHPOP3, 0);
3391
3392 /* Store the registers with lower number registers being placed at higher addresses. */
3393 for (i = 0; i < 15; i++)
3394 if ((OP[3] & (1 << type3_regs[ i ])))
3395 {
3396 SP -= 4;
3397 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
3398 }
3399
3400 if (OP[3] & (1 << 3))
3401 {
3402 SP -= 4;
3403
3404 store_mem (SP & ~ 3, 4, PSW);
3405 }
3406
3407 if (OP[3] & (1 << 19))
3408 {
3409 SP -= 8;
3410
3411 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3412 {
3413 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3414 store_mem ( SP & ~ 3, 4, FEPSW);
3415 }
3416 else
3417 {
3418 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3419 store_mem ( SP & ~ 3, 4, EIPSW);
3420 }
3421 }
3422
3423 trace_output (OP_PUSHPOP2);
3424 }
3425 else
3426 {
3427 int adr;
3428
3429 trace_input ("ld.hu", OP_LOAD32, 2);
3430
3431 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
3432 adr &= ~0x1;
3433
3434 State.regs[ OP[1] ] = load_mem (adr, 2);
3435
3436 trace_output (OP_LOAD32);
3437 }
3438
3439 return 4;
3440 }
3441
3442 /* prepare list12, imm5 */
3443 /* ld.bu */
3444 int
3445 OP_10780 (void)
3446 {
3447 if (OP[ 1 ] == 0)
3448 {
3449 int i;
3450
3451 trace_input ("prepare", OP_PUSHPOP1, 0);
3452
3453 /* Store the registers with lower number registers being placed at higher addresses. */
3454 for (i = 0; i < 12; i++)
3455 if ((OP[3] & (1 << type1_regs[ i ])))
3456 {
3457 SP -= 4;
3458 store_mem (SP, 4, State.regs[ 20 + i ]);
3459 }
3460
3461 SP -= (OP[3] & 0x3e) << 1;
3462
3463 trace_output (OP_PUSHPOP1);
3464 }
3465 else
3466 {
3467 int adr;
3468
3469 trace_input ("ld.bu", OP_LOAD32, 1);
3470
3471 adr = (State.regs[ OP[0] ]
3472 + (SEXT16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
3473
3474 State.regs[ OP[1] ] = load_mem (adr, 1);
3475
3476 trace_output (OP_LOAD32);
3477 }
3478
3479 return 4;
3480 }
3481
3482 /* prepare list12, imm5, imm32 */
3483 int
3484 OP_1B0780 (void)
3485 {
3486 int i;
3487
3488 trace_input ("prepare", OP_PUSHPOP1, 0);
3489
3490 /* Store the registers with lower number registers being placed at higher addresses. */
3491 for (i = 0; i < 12; i++)
3492 if ((OP[3] & (1 << type1_regs[ i ])))
3493 {
3494 SP -= 4;
3495 store_mem (SP, 4, State.regs[ 20 + i ]);
3496 }
3497
3498 SP -= (OP[3] & 0x3e) << 1;
3499
3500 EP = load_mem (PC + 4, 4);
3501
3502 trace_output (OP_PUSHPOP1);
3503
3504 return 8;
3505 }
3506
3507 /* prepare list12, imm5, imm16-32 */
3508 int
3509 OP_130780 (void)
3510 {
3511 int i;
3512
3513 trace_input ("prepare", OP_PUSHPOP1, 0);
3514
3515 /* Store the registers with lower number registers being placed at higher addresses. */
3516 for (i = 0; i < 12; i++)
3517 if ((OP[3] & (1 << type1_regs[ i ])))
3518 {
3519 SP -= 4;
3520 store_mem (SP, 4, State.regs[ 20 + i ]);
3521 }
3522
3523 SP -= (OP[3] & 0x3e) << 1;
3524
3525 EP = load_mem (PC + 4, 2) << 16;
3526
3527 trace_output (OP_PUSHPOP1);
3528
3529 return 6;
3530 }
3531
3532 /* prepare list12, imm5, imm16 */
3533 int
3534 OP_B0780 (void)
3535 {
3536 int i;
3537
3538 trace_input ("prepare", OP_PUSHPOP1, 0);
3539
3540 /* Store the registers with lower number registers being placed at higher addresses. */
3541 for (i = 0; i < 12; i++)
3542 if ((OP[3] & (1 << type1_regs[ i ])))
3543 {
3544 SP -= 4;
3545 store_mem (SP, 4, State.regs[ 20 + i ]);
3546 }
3547
3548 SP -= (OP[3] & 0x3e) << 1;
3549
3550 EP = SEXT16 (load_mem (PC + 4, 2));
3551
3552 trace_output (OP_PUSHPOP1);
3553
3554 return 6;
3555 }
3556
3557 /* prepare list12, imm5, sp */
3558 int
3559 OP_30780 (void)
3560 {
3561 int i;
3562
3563 trace_input ("prepare", OP_PUSHPOP1, 0);
3564
3565 /* Store the registers with lower number registers being placed at higher addresses. */
3566 for (i = 0; i < 12; i++)
3567 if ((OP[3] & (1 << type1_regs[ i ])))
3568 {
3569 SP -= 4;
3570 store_mem (SP, 4, State.regs[ 20 + i ]);
3571 }
3572
3573 SP -= (OP[3] & 0x3e) << 1;
3574
3575 EP = SP;
3576
3577 trace_output (OP_PUSHPOP1);
3578
3579 return 4;
3580 }
3581
3582 /* sld.hu */
3583 int
3584 OP_70 (void)
3585 {
3586 unsigned long result;
3587
3588 result = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
3589
3590 /* start-sanitize-v850eq */
3591 #ifdef ARCH_v850eq
3592 trace_input ("sld.h", OP_LOAD16, 2);
3593
3594 State.regs[ OP[1] ] = SEXT16 (result);
3595 #else
3596 /* end-sanitize-v850eq */
3597 trace_input ("sld.hu", OP_LOAD16, 2);
3598
3599 State.regs[ OP[1] ] = result;
3600 /* start-sanitize-v850eq */
3601 #endif
3602 /* end-sanitize-v850eq */
3603
3604 trace_output (OP_LOAD16);
3605
3606 return 2;
3607 }
3608
3609 /* cmov reg1, reg2, reg3 */
3610 int
3611 OP_32007E0 (void)
3612 {
3613 trace_input ("cmov", OP_REG_REG_REG, 0);
3614
3615 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
3616
3617 trace_output (OP_REG_REG_REG);
3618
3619 return 4;
3620 }
3621
3622 /* mul reg1, reg2, reg3 */
3623 int
3624 OP_22007E0 (void)
3625 {
3626 trace_input ("mul", OP_REG_REG_REG, 0);
3627
3628 Multiply64 (true, State.regs[ OP[0] ]);
3629
3630 trace_output (OP_REG_REG_REG);
3631
3632 return 4;
3633 }
3634
3635 /* end-sanitize-v850e */
3636 /* start-sanitize-v850eq */
3637
3638 /* popmh list18 */
3639 int
3640 OP_307F0 (void)
3641 {
3642 int i;
3643
3644 trace_input ("popmh", OP_PUSHPOP2, 0);
3645
3646 if (OP[3] & (1 << 19))
3647 {
3648 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3649 {
3650 FEPSW = load_mem ( SP & ~ 3, 4);
3651 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3652 }
3653 else
3654 {
3655 EIPSW = load_mem ( SP & ~ 3, 4);
3656 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3657 }
3658
3659 SP += 8;
3660 }
3661
3662 /* Load the registers with lower number registers being retrieved from higher addresses. */
3663 for (i = 16; i--;)
3664 if ((OP[3] & (1 << type2_regs[ i ])))
3665 {
3666 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
3667 SP += 4;
3668 }
3669
3670 trace_output (OP_PUSHPOP2);
3671
3672 return 4;
3673 }
3674
3675 /* popml lsit18 */
3676 int
3677 OP_107F0 (void)
3678 {
3679 int i;
3680
3681 trace_input ("popml", OP_PUSHPOP3, 0);
3682
3683 if (OP[3] & (1 << 19))
3684 {
3685 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3686 {
3687 FEPSW = load_mem ( SP & ~ 3, 4);
3688 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3689 }
3690 else
3691 {
3692 EIPSW = load_mem ( SP & ~ 3, 4);
3693 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3694 }
3695
3696 SP += 8;
3697 }
3698
3699 if (OP[3] & (1 << 3))
3700 {
3701 PSW = load_mem (SP & ~ 3, 4);
3702 SP += 4;
3703 }
3704
3705 /* Load the registers with lower number registers being retrieved from higher addresses. */
3706 for (i = 15; i--;)
3707 if ((OP[3] & (1 << type3_regs[ i ])))
3708 {
3709 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
3710 SP += 4;
3711 }
3712
3713 trace_output (OP_PUSHPOP2);
3714
3715 return 4;
3716 }
3717
3718 /* pushmh list18 */
3719 int
3720 OP_307E0 (void)
3721 {
3722 int i;
3723
3724 trace_input ("pushmh", OP_PUSHPOP2, 0);
3725
3726 /* Store the registers with lower number registers being placed at higher addresses. */
3727 for (i = 0; i < 16; i++)
3728 if ((OP[3] & (1 << type2_regs[ i ])))
3729 {
3730 SP -= 4;
3731 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
3732 }
3733
3734 if (OP[3] & (1 << 19))
3735 {
3736 SP -= 8;
3737
3738 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3739 {
3740 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3741 store_mem ( SP & ~ 3, 4, FEPSW);
3742 }
3743 else
3744 {
3745 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3746 store_mem ( SP & ~ 3, 4, EIPSW);
3747 }
3748 }
3749
3750 trace_output (OP_PUSHPOP2);
3751
3752 return 4;
3753 }
3754
3755 /* end-sanitize-v850eq */