sim/v850/simops.c

   1 #include <signal.h>
   2 #include "v850_sim.h"
   3 #include "simops.h"
   4
   5 void
   6 OP_220 ()
   7 {
   8 }
   9
  10 void
  11 OP_10760 ()
  12 {
  13 }
  14
  15 void
  16 OP_C7C0 ()
  17 {
  18 }
  19
  20 void
  21 OP_760 ()
  22 {
  23 }
  24
  25 /* bv disp9 */
  26 void
  27 OP_580 ()
  28 {
  29   unsigned int op0, psw;
  30   int temp;
  31
  32   temp = (State.regs[OP[0]] << 23) >> 23;
  33   op0 = temp;
  34   psw = State.psw;
  35
  36   if ((psw & PSW_OV) != 0)
  37     State.pc += op0;
  38   else
  39     State.pc += 2;
  40 }
  41
  42 /* bl disp9 */
  43 void
  44 OP_581 ()
  45 {
  46   unsigned int op0, psw;
  47   int temp;
  48
  49   temp = (State.regs[OP[0]] << 23) >> 23;
  50   op0 = temp;
  51   psw = State.psw;
  52
  53   if ((psw & PSW_CY) != 0)
  54     State.pc += op0;
  55   else
  56     State.pc += 2;
  57 }
  58
  59 /* be disp9 */
  60 void
  61 OP_582 ()
  62 {
  63   unsigned int op0, psw;
  64   int temp;
  65
  66   temp = (State.regs[OP[0]] << 23) >> 23;
  67   op0 = temp;
  68   psw = State.psw;
  69
  70   if ((psw & PSW_Z) != 0)
  71     State.pc += op0;
  72   else
  73     State.pc += 2;
  74 }
  75
  76 /* bnh disp 9*/
  77 void
  78 OP_583 ()
  79 {
  80   unsigned int op0, psw;
  81   int temp;
  82
  83   temp = (State.regs[OP[0]] << 23) >> 23;
  84   op0 = temp;
  85   psw = State.psw;
  86
  87   if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
  88     State.pc += op0;
  89   else
  90     State.pc += 2;
  91 }
  92
  93 /* bn disp9 */
  94 void
  95 OP_584 ()
  96 {
  97   unsigned int op0, psw;
  98   int temp;
  99
 100   temp = (State.regs[OP[0]] << 23) >> 23;
 101   op0 = temp;
 102   psw = State.psw;
 103
 104   if ((psw & PSW_S) != 0)
 105     State.pc += op0;
 106   else
 107     State.pc += 2;
 108 }
 109
 110 /* br disp9 */
 111 void
 112 OP_585 ()
 113 {
 114   unsigned int op0;
 115   int temp;
 116
 117   temp = (State.regs[OP[0]] << 23) >> 23;
 118   op0 = temp;
 119   State.pc += op0;
 120 }
 121
 122 /* blt disp9 */
 123 void
 124 OP_586 ()
 125 {
 126   unsigned int op0, psw;
 127   int temp;
 128
 129   temp = (State.regs[OP[0]] << 23) >> 23;
 130   op0 = temp;
 131   psw = State.psw;
 132
 133   if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
 134     State.pc += op0;
 135   else
 136     State.pc += 2;
 137 }
 138
 139 /* ble disp9 */
 140 void
 141 OP_587 ()
 142 {
 143   unsigned int op0, psw;
 144   int temp;
 145
 146   temp = (State.regs[OP[0]] << 23) >> 23;
 147   op0 = temp;
 148   psw = State.psw;
 149
 150   if ((((psw & PSW_Z) != 0)
 151        || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
 152     State.pc += op0;
 153   else
 154     State.pc += 2;
 155 }
 156
 157 /* bnv disp9 */
 158 void
 159 OP_588 ()
 160 {
 161   unsigned int op0, psw;
 162   int temp;
 163
 164   temp = (State.regs[OP[0]] << 23) >> 23;
 165   op0 = temp;
 166   psw = State.psw;
 167
 168   if ((psw & PSW_OV) == 0)
 169     State.pc += op0;
 170   else
 171     State.pc += 2;
 172 }
 173
 174 /* bnl disp9 */
 175 void
 176 OP_589 ()
 177 {
 178   unsigned int op0, psw;
 179   int temp;
 180
 181   temp = (State.regs[OP[0]] << 23) >> 23;
 182   op0 = temp;
 183   psw = State.psw;
 184
 185   if ((psw & PSW_CY) == 0)
 186     State.pc += op0;
 187   else
 188     State.pc += 2;
 189 }
 190
 191 /* bne disp9 */
 192 void
 193 OP_58A ()
 194 {
 195   unsigned int op0, psw;
 196   int temp;
 197
 198   temp = (State.regs[OP[0]] << 23) >> 23;
 199   op0 = temp;
 200   psw = State.psw;
 201
 202   if ((psw & PSW_Z) == 0)
 203     State.pc += op0;
 204   else
 205     State.pc += 2;
 206 }
 207
 208 /* bh disp9 */
 209 void
 210 OP_58B ()
 211 {
 212   unsigned int op0, psw;
 213   int temp;
 214
 215   temp = (State.regs[OP[0]] << 23) >> 23;
 216   op0 = temp;
 217   psw = State.psw;
 218
 219   if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
 220     State.pc += op0;
 221   else
 222     State.pc += 2;
 223 }
 224
 225 /* bp disp9 */
 226 void
 227 OP_58C ()
 228 {
 229   unsigned int op0, psw;
 230   int temp;
 231
 232   temp = (State.regs[OP[0]] << 23) >> 23;
 233   op0 = temp;
 234   psw = State.psw;
 235
 236   if ((psw & PSW_S) == 0)
 237     State.pc += op0;
 238   else
 239     State.pc += 2;
 240 }
 241
 242 /* bsa disp9 */
 243 void
 244 OP_58D ()
 245 {
 246   unsigned int op0, psw;
 247   int temp;
 248
 249   temp = (State.regs[OP[0]] << 23) >> 23;
 250   op0 = temp;
 251   psw = State.psw;
 252
 253   if ((psw & PSW_SAT) != 0)
 254     State.pc += op0;
 255   else
 256     State.pc += 2;
 257 }
 258
 259 /* bge disp9 */
 260 void
 261 OP_58E ()
 262 {
 263   unsigned int op0, psw;
 264   int temp;
 265
 266   temp = (State.regs[OP[0]] << 23) >> 23;
 267   op0 = temp;
 268   psw = State.psw;
 269
 270   if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
 271     State.pc += op0;
 272   else
 273     State.pc += 2;
 274 }
 275
 276 /* bgt disp9 */
 277 void
 278 OP_58F ()
 279 {
 280   unsigned int op0, psw;
 281   int temp;
 282
 283   temp = (State.regs[OP[0]] << 23) >> 23;
 284   op0 = temp;
 285   psw = State.psw;
 286
 287   if ((((psw & PSW_Z) != 0)
 288        || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
 289     State.pc += op0;
 290   else
 291     State.pc += 2;
 292 }
 293
 294 /* jmp [reg1] */
 295 void
 296 OP_60 ()
 297 {
 298   /* interp.c will bump this by +2, so correct for it here.  */
 299   State.pc = State.regs[OP[0]] - 2;
 300 }
 301
 302 /* jarl disp22, reg */
 303 void
 304 OP_780 ()
 305 {
 306   unsigned int op0, opc;
 307   int temp;
 308
 309   temp = OP[0];
 310   temp = (temp << 10) >> 10;
 311   op0 = temp;
 312   opc = State.pc;
 313
 314   State.pc += temp;
 315
 316   /* Gross.  jarl X,r0 is really jr and doesn't save its result.  */
 317   if (OP[1] != 0)
 318     State.regs[OP[1]] = opc + 4;
 319 }
 320
 321 /* add reg, reg */
 322 void
 323 OP_1C0 ()
 324 {
 325   unsigned int op0, op1, result, z, s, cy, ov;
 326
 327   /* Compute the result.  */
 328   op0 = State.regs[OP[0]];
 329   op1 = State.regs[OP[1]];
 330   result = op0 + op1;
 331
 332   /* Compute the condition codes.  */
 333   z = (result == 0);
 334   s = (result & 0x80000000);
 335   cy = (result < op0 || result < op1);
 336   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 337         && (op0 & 0x80000000) != (result & 0x80000000));
 338
 339   /* Store the result and condition codes.  */
 340   State.regs[OP[1]] = result;
 341   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 342   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 343                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 344 }
 345
 346 /* add sign_extend(imm5), reg */
 347 void
 348 OP_240 ()
 349 {
 350   unsigned int op0, op1, result, z, s, cy, ov;
 351   int temp;
 352
 353   /* Compute the result.  */
 354   temp = (OP[0] & 0x1f);
 355   temp = (temp << 27) >> 27;
 356   op0 = temp;
 357   op1 = State.regs[OP[1]];
 358   result = op0 + op1;
 359
 360   /* Compute the condition codes.  */
 361   z = (result == 0);
 362   s = (result & 0x80000000);
 363   cy = (result < op0 || result < op1);
 364   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 365         && (op0 & 0x80000000) != (result & 0x80000000));
 366
 367   /* Store the result and condition codes.  */
 368   State.regs[OP[1]] = result;
 369   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 370   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 371                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 372 }
 373
 374 /* addi sign_extend(imm16), reg, reg */
 375 void
 376 OP_600 ()
 377 {
 378   unsigned int op0, op1, result, z, s, cy, ov;
 379   int temp;
 380
 381   /* Compute the result.  */
 382   temp = (OP[0] & 0xffff);
 383   temp = (temp << 16) >> 16;
 384   op0 = temp;
 385   op1 = State.regs[OP[1]];
 386   result = op0 + op1;
 387
 388   /* Compute the condition codes.  */
 389   z = (result == 0);
 390   s = (result & 0x80000000);
 391   cy = (result < op0 || result < op1);
 392   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 393         && (op0 & 0x80000000) != (result & 0x80000000));
 394
 395   /* Store the result and condition codes.  */
 396   State.regs[OP[2]] = result;
 397   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 398   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 399                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 400 }
 401
 402 /* sub reg1, reg2 */
 403 void
 404 OP_1A0 ()
 405 {
 406   unsigned int op0, op1, result, z, s, cy, ov;
 407
 408   /* Compute the result.  */
 409   op0 = State.regs[OP[0]];
 410   op1 = State.regs[OP[1]];
 411   result = op1 - op0;
 412
 413   /* Compute the condition codes.  */
 414   z = (result == 0);
 415   s = (result & 0x80000000);
 416   cy = (result < -op0);
 417   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 418         && (op1 & 0x80000000) != (result & 0x80000000));
 419
 420   /* Store the result and condition codes.  */
 421   State.regs[OP[1]] = result;
 422   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 423   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 424                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 425 }
 426
 427 /* subr reg1, reg2 */
 428 void
 429 OP_180 ()
 430 {
 431   unsigned int op0, op1, result, z, s, cy, ov;
 432
 433   /* Compute the result.  */
 434   op0 = State.regs[OP[0]];
 435   op1 = State.regs[OP[1]];
 436   result = op0 - op1;
 437
 438   /* Compute the condition codes.  */
 439   z = (result == 0);
 440   s = (result & 0x80000000);
 441   cy = (result < -op1);
 442   ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
 443         && (op0 & 0x80000000) != (result & 0x80000000));
 444
 445   /* Store the result and condition codes.  */
 446   State.regs[OP[1]] = result;
 447   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 448   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 449                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 450 }
 451
 452 /* mulh reg1, reg2 */
 453 void
 454 OP_E0 ()
 455 {
 456   State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
 457                        * (State.regs[OP[0]] & 0xffff));
 458 }
 459
 460 /* mulh sign_extend(imm5), reg2
 461
 462    Condition codes */
 463 void
 464 OP_2E0 ()
 465 {
 466   int value = OP[0];
 467
 468   value = (value << 27) >> 27;
 469
 470   State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
 471 }
 472
 473 /* mulhi imm16, reg1, reg2 */
 474 void
 475 OP_6E0 ()
 476 {
 477   int value = OP[0];
 478
 479   value = value & 0xffff;
 480
 481   State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
 482 }
 483
 484 /* divh reg1, reg2 */
 485 void
 486 OP_40 ()
 487 {
 488   unsigned int op0, op1, result, z, s, cy, ov;
 489   int temp;
 490
 491   /* Compute the result.  */
 492   temp = State.regs[OP[0]] & 0xffff;
 493   temp = (temp << 16) >> 16;
 494   op0 = temp;
 495   op1 = State.regs[OP[1]];
 496
 497   if (op0 == 0xffffffff && op1 == 0x80000000)
 498     {
 499       result = 0x80000000;
 500       ov = 1;
 501     }
 502   else if (op0 != 0)
 503     {
 504       result = op1 / op0;
 505       ov = 0;
 506     }
 507   else
 508     ov = 1;
 509
 510   /* Compute the condition codes.  */
 511   z = (result == 0);
 512   s = (result & 0x80000000);
 513
 514   /* Store the result and condition codes.  */
 515   State.regs[OP[1]] = result;
 516   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 517   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 518                 | (ov ? PSW_OV : 0));
 519 }
 520
 521 /* cmp reg, reg */
 522 void
 523 OP_1E0 ()
 524 {
 525   unsigned int op0, op1, result, z, s, cy, ov;
 526
 527   /* Compute the result.  */
 528   op0 = State.regs[OP[0]];
 529   op1 = State.regs[OP[1]];
 530   result = op1 - op0;
 531
 532   /* Compute the condition codes.  */
 533   z = (result == 0);
 534   s = (result & 0x80000000);
 535   cy = (result < -op0);
 536   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 537         && (op1 & 0x80000000) != (result & 0x80000000));
 538
 539   /* Set condition codes.  */
 540   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 541   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 542                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 543 }
 544
 545 /* cmp sign_extend(imm5), reg */
 546 void
 547 OP_260 ()
 548 {
 549   unsigned int op0, op1, result, z, s, cy, ov;
 550   int temp;
 551
 552   /* Compute the result.  */
 553   temp = OP[0];
 554   temp = (temp << 27) >> 27;
 555   op0 = temp;
 556   op1 = State.regs[OP[1]];
 557   result = op1 - op0;
 558
 559   /* Compute the condition codes.  */
 560   z = (result == 0);
 561   s = (result & 0x80000000);
 562   cy = (result < -op0);
 563   ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
 564         && (op1 & 0x80000000) != (result & 0x80000000));
 565
 566   /* Set condition codes.  */
 567   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 568   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 569                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 570 }
 571
 572 /* setf cccc,reg2 */
 573 void
 574 OP_7E0 ()
 575 {
 576   /* Hack alert.  We turn off a bit in op0 since we really only
 577      wanted 4 bits.  */
 578   unsigned int op0, psw, result;
 579
 580   op0 = OP[0] & 0xf;
 581   psw = State.psw;
 582
 583   switch (op0)
 584     {
 585       case 0x0:
 586         result = ((psw & PSW_OV) != 0);
 587         break;
 588       case 0x1:
 589         result = ((psw & PSW_CY) != 0);
 590         break;
 591       case 0x2:
 592         result = ((psw & PSW_Z) != 0);
 593         break;
 594       case 0x3:
 595         result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
 596         break;
 597       case 0x4:
 598         result = ((psw & PSW_S) != 0);
 599         break;
 600       case 0x5:
 601         result = 1;
 602         break;
 603       case 0x6:
 604         result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
 605         break;
 606       case 0x7:
 607         result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
 608                   || ((psw & PSW_Z) != 0)) != 0);
 609         break;
 610       case 0x8:
 611         result = ((psw & PSW_OV) == 0);
 612         break;
 613       case 0x9:
 614         result = ((psw & PSW_CY) == 0);
 615         break;
 616       case 0xa:
 617         result = ((psw & PSW_Z) == 0);
 618         break;
 619       case 0xb:
 620         result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
 621         break;
 622       case 0xc:
 623         result = ((psw & PSW_S) == 0);
 624         break;
 625       case 0xd:
 626         result = ((psw & PSW_SAT) != 0);
 627         break;
 628       case 0xe:
 629         result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
 630         break;
 631       case 0xf:
 632         result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
 633                   || ((psw & PSW_Z) != 0)) == 0);
 634         break;
 635     }
 636
 637   State.regs[OP[1]] = result;
 638 }
 639
 640 /* tst reg,reg */
 641 void
 642 OP_160 ()
 643 {
 644   unsigned int op0, op1, result, z, s, cy, ov;
 645
 646   /* Compute the result.  */
 647   op0 = State.regs[OP[0]];
 648   op1 = State.regs[OP[1]];
 649   result = op0 & op1;
 650
 651   /* Compute the condition codes.  */
 652   z = (result == 0);
 653   s = (result & 0x80000000);
 654
 655   /* Store the condition codes.  */
 656   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 657   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 658 }
 659
 660 void
 661 OP_10720 ()
 662 {
 663 }
 664
 665 void
 666 OP_720 ()
 667 {
 668 }
 669
 670 void
 671 OP_87C0 ()
 672 {
 673 }
 674
 675 void
 676 OP_300 ()
 677 {
 678 }
 679
 680 /* mov reg, reg */
 681 void
 682 OP_0 ()
 683 {
 684   State.regs[OP[1]] = State.regs[OP[0]];
 685 }
 686
 687 /* mov sign_extend(imm5), reg */
 688 void
 689 OP_200 ()
 690 {
 691   int value = OP[0];
 692
 693   value = (value << 27) >> 27;
 694   State.regs[OP[1]] = value;
 695 }
 696
 697 /* movea sign_extend(imm16), reg, reg  */
 698
 699 void
 700 OP_620 ()
 701 {
 702   int value = OP[0];
 703
 704   value = (value << 16) >> 16;
 705
 706   State.regs[OP[2]] = State.regs[OP[1]] + value;
 707 }
 708
 709 /* movhi imm16, reg, reg */
 710 void
 711 OP_640 ()
 712 {
 713   int value = OP[0];
 714
 715   value = (value & 0xffff) << 16;
 716
 717   State.regs[OP[2]] = State.regs[OP[1]] + value;
 718 }
 719
 720 void
 721 OP_7C0 ()
 722 {
 723 }
 724
 725 void
 726 OP_1687E0 ()
 727 {
 728 }
 729
 730 void
 731 OP_A0 ()
 732 {
 733 }
 734
 735 void
 736 OP_740 ()
 737 {
 738 }
 739
 740 void
 741 OP_80 ()
 742 {
 743 }
 744
 745 /* sar zero_extend(imm5),reg1 */
 746 void
 747 OP_2A0 ()
 748 {
 749   unsigned int op0, op1, result, z, s, cy, ov;
 750
 751   op0 = OP[0] & 0x1f;
 752   op1 = State.regs[OP[1]];
 753   result = (signed)op1 >> op0;
 754
 755   /* Compute the condition codes.  */
 756   z = (result == 0);
 757   s = (result & 0x80000000);
 758   cy = (op1 & (1 << (op0 - 1)));
 759
 760   /* Store the result and condition codes.  */
 761   State.regs[OP[1]] = result;
 762   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 763   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 764                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 765 }
 766
 767 /* sar reg1, reg2 */
 768 void
 769 OP_A007E0 ()
 770 {
 771   unsigned int op0, op1, result, z, s, cy, ov;
 772
 773   op0 = State.regs[OP[0]] & 0x1f;
 774   op1 = State.regs[OP[1]];
 775   result = (signed)op1 >> op0;
 776
 777   /* Compute the condition codes.  */
 778   z = (result == 0);
 779   s = (result & 0x80000000);
 780   cy = (op1 & (1 << (op0 - 1)));
 781
 782   /* Store the result and condition codes.  */
 783   State.regs[OP[1]] = result;
 784   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 785   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 786                 | (cy ? PSW_CY : 0));
 787 }
 788
 789 /* shl zero_extend(imm5),reg1 */
 790 void
 791 OP_2C0 ()
 792 {
 793   unsigned int op0, op1, result, z, s, cy, ov;
 794
 795   op0 = OP[0] & 0x1f;
 796   op1 = State.regs[OP[1]];
 797   result = op1 << op0;
 798
 799   /* Compute the condition codes.  */
 800   z = (result == 0);
 801   s = (result & 0x80000000);
 802   cy = (op1 & (1 << (32 - op0)));
 803
 804   /* Store the result and condition codes.  */
 805   State.regs[OP[1]] = result;
 806   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 807   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 808                 | (cy ? PSW_CY : 0));
 809 }
 810
 811 /* shl reg1, reg2 */
 812 void
 813 OP_C007E0 ()
 814 {
 815   unsigned int op0, op1, result, z, s, cy, ov;
 816
 817   op0 = State.regs[OP[0]] & 0x1f;
 818   op1 = State.regs[OP[1]];
 819   result = op1 << op0;
 820
 821   /* Compute the condition codes.  */
 822   z = (result == 0);
 823   s = (result & 0x80000000);
 824   cy = (op1 & (1 << (32 - op0)));
 825
 826   /* Store the result and condition codes.  */
 827   State.regs[OP[1]] = result;
 828   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 829   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 830                 | (cy ? PSW_CY : 0));
 831 }
 832
 833 /* shr zero_extend(imm5),reg1 */
 834 void
 835 OP_280 ()
 836 {
 837   unsigned int op0, op1, result, z, s, cy, ov;
 838
 839   op0 = OP[0] & 0x1f;
 840   op1 = State.regs[OP[1]];
 841   result = op1 >> op0;
 842
 843   /* Compute the condition codes.  */
 844   z = (result == 0);
 845   s = (result & 0x80000000);
 846   cy = (op1 & (1 << (op0 - 1)));
 847
 848   /* Store the result and condition codes.  */
 849   State.regs[OP[1]] = result;
 850   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 851   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 852                 | (cy ? PSW_CY : 0));
 853 }
 854
 855 /* shr reg1, reg2 */
 856 void
 857 OP_8007E0 ()
 858 {
 859   unsigned int op0, op1, result, z, s, cy, ov;
 860
 861   op0 = State.regs[OP[0]] & 0x1f;
 862   op1 = State.regs[OP[1]];
 863   result = op1 >> op0;
 864
 865   /* Compute the condition codes.  */
 866   z = (result == 0);
 867   s = (result & 0x80000000);
 868   cy = (op1 & (1 << (op0 - 1)));
 869
 870   /* Store the result and condition codes.  */
 871   State.regs[OP[1]] = result;
 872   State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
 873   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 874                 | (cy ? PSW_CY : 0));
 875 }
 876
 877 void
 878 OP_500 ()
 879 {
 880 }
 881
 882 void
 883 OP_47C0 ()
 884 {
 885 }
 886
 887 /* or reg, reg */
 888 void
 889 OP_100 ()
 890 {
 891   unsigned int op0, op1, result, z, s, cy, ov;
 892
 893   /* Compute the result.  */
 894   op0 = State.regs[OP[0]];
 895   op1 = State.regs[OP[1]];
 896   result = op0 | op1;
 897
 898   /* Compute the condition codes.  */
 899   z = (result == 0);
 900   s = (result & 0x80000000);
 901
 902   /* Store the result and condition codes.  */
 903   State.regs[OP[1]] = result;
 904   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 905   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 906 }
 907
 908 /* ori zero_extend(imm16), reg, reg */
 909 void
 910 OP_680 ()
 911 {
 912   unsigned int op0, op1, result, z, s, cy, ov;
 913
 914   op0 = OP[0] & 0xffff;
 915   op1 = State.regs[OP[1]];
 916   result = op0 | op1;
 917
 918   /* Compute the condition codes.  */
 919   z = (result == 0);
 920   s = (result & 0x80000000);
 921
 922   /* Store the result and condition codes.  */
 923   State.regs[OP[2]] = result;
 924   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 925   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 926 }
 927
 928 /* and reg, reg */
 929 void
 930 OP_140 ()
 931 {
 932   unsigned int op0, op1, result, z, s, cy, ov;
 933
 934   /* Compute the result.  */
 935   op0 = State.regs[OP[0]];
 936   op1 = State.regs[OP[1]];
 937   result = op0 & op1;
 938
 939   /* Compute the condition codes.  */
 940   z = (result == 0);
 941   s = (result & 0x80000000);
 942
 943   /* Store the result and condition codes.  */
 944   State.regs[OP[1]] = result;
 945   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 946   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 947 }
 948
 949 /* andi zero_extend(imm16), reg, reg */
 950 void
 951 OP_6C0 ()
 952 {
 953   unsigned int op0, op1, result, z, s, cy, ov;
 954
 955   op0 = OP[0] & 0xffff;
 956   op1 = State.regs[OP[1]];
 957   result = op0 & op1;
 958
 959   /* Compute the condition codes.  */
 960   z = (result == 0);
 961
 962   /* Store the result and condition codes.  */
 963   State.regs[OP[2]] = result;
 964   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 965   State.psw |= (z ? PSW_Z : 0);
 966 }
 967
 968 /* xor reg, reg */
 969 void
 970 OP_120 ()
 971 {
 972   unsigned int op0, op1, result, z, s, cy, ov;
 973
 974   /* Compute the result.  */
 975   op0 = State.regs[OP[0]];
 976   op1 = State.regs[OP[1]];
 977   result = op0 ^ op1;
 978
 979   /* Compute the condition codes.  */
 980   z = (result == 0);
 981   s = (result & 0x80000000);
 982
 983   /* Store the result and condition codes.  */
 984   State.regs[OP[1]] = result;
 985   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 986   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 987 }
 988
 989 /* xori zero_extend(imm16), reg, reg */
 990 void
 991 OP_6A0 ()
 992 {
 993   unsigned int op0, op1, result, z, s, cy, ov;
 994
 995   op0 = OP[0] & 0xffff;
 996   op1 = State.regs[OP[1]];
 997   result = op0 ^ op1;
 998
 999   /* Compute the condition codes.  */
1000   z = (result == 0);
1001   s = (result & 0x80000000);
1002
1003   /* Store the result and condition codes.  */
1004   State.regs[OP[2]] = result;
1005   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1006   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1007 }
1008
1009 /* not reg1, reg2 */
1010 void
1011 OP_20 ()
1012 {
1013   unsigned int op0, result, z, s, cy, ov;
1014
1015   /* Compute the result.  */
1016   op0 = State.regs[OP[0]];
1017   result = ~op0;
1018
1019   /* Compute the condition codes.  */
1020   z = (result == 0);
1021   s = (result & 0x80000000);
1022
1023   /* Store the result and condition codes.  */
1024   State.regs[OP[1]] = result;
1025   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1026   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1027 }
1028
1029 void
1030 OP_C0 ()
1031 {
1032 }
1033
1034 void
1035 OP_480 ()
1036 {
1037 }
1038
1039 void
1040 OP_380 ()
1041 {
1042 }
1043
1044 void
1045 OP_501 ()
1046 {
1047 }
1048
1049 /* di */
1050 void
1051 OP_16007E0 ()
1052 {
1053   State.psw |= PSW_ID;
1054 }
1055
1056 /* ei */
1057 void
1058 OP_16087E0 ()
1059 {
1060   State.psw &= ~PSW_ID;
1061 }
1062
1063 /* halt, not supported */
1064 void
1065 OP_12007E0 ()
1066 {
1067   abort ();
1068 }
1069
1070 /* reti, not supported */
1071 void
1072 OP_14007E0 ()
1073 {
1074   abort ();
1075 }
1076
1077 /* trap, not supportd */
1078 void
1079 OP_10007E0 ()
1080 {
1081   abort ();
1082 }
1083
1084 /* ldsr, not supported */
1085 void
1086 OP_2007E0 ()
1087 {
1088   abort ();
1089 }
1090
1091 /* stsr, not supported */
1092 void
1093 OP_4007E0 ()
1094 {
1095   abort ();
1096 }
1097
1098 void
1099 OP_400 ()
1100 {
1101 }
1102
1103 void
1104 OP_700 ()
1105 {
1106 }
1107
1108 void
1109 OP_660 ()
1110 {
1111 }
1112