1 :option:::insn-bit-size:16
5 :option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
6 :option:::format-names:XI,XII,XIII
7 :option:::format-names:XIV,XV
8 :option:::format-names:Z
13 :option:::multi-sim:true
18 :cache:::unsigned:reg1:RRRRR:(RRRRR)
19 :cache:::unsigned:reg2:rrrrr:(rrrrr)
20 :cache:::unsigned:reg3:wwwww:(wwwww)
22 :cache:::unsigned:disp4:dddd:(dddd)
23 :cache:::unsigned:disp5:dddd:(dddd << 1)
24 :cache:::unsigned:disp7:ddddddd:ddddddd
25 :cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
26 :cache:::unsigned:disp8:dddddd:(dddddd << 2)
27 :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
28 :cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
29 :cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
30 :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
32 :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
33 :cache:::unsigned:imm6:iiiiii:iiiiii
34 :cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
35 :cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
36 :cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
37 :cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
38 :cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
39 :cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
41 :cache:::unsigned:vector:iiiii:iiiii
43 :cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
44 :cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
46 :cache:::unsigned:bit3:bbb:bbb
49 // What do we do with an illegal instruction?
52 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
54 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
61 rrrrr,001110,RRRRR:I:::add
62 "add r<reg1>, r<reg2>"
67 rrrrr,010010,iiiii:II:::add
76 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
77 "addi <simm16>, r<reg1>, r<reg2>"
85 rrrrr,001010,RRRRR:I:::and
86 "and r<reg1>, r<reg2>"
94 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
95 "andi <uimm16>, r<reg1>, r<reg2>"
102 // Map condition code to a string
107 case 0xf: return "gt";
108 case 0xe: return "ge";
109 case 0x6: return "lt";
111 case 0x7: return "le";
113 case 0xb: return "h";
114 case 0x9: return "nl";
115 case 0x1: return "l";
117 case 0x3: return "nh";
119 case 0x2: return "e";
121 case 0xa: return "ne";
123 case 0x0: return "v";
124 case 0x8: return "nv";
125 case 0x4: return "n";
126 case 0xc: return "p";
127 /* case 0x1: return "c"; */
128 /* case 0x9: return "nc"; */
129 /* case 0x2: return "z"; */
130 /* case 0xa: return "nz"; */
131 case 0x5: return "r"; /* always */
132 case 0xd: return "sa";
139 ddddd,1011,ddd,cccc:III:::Bcond
143 if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
144 // Special case - treat "br *" like illegal instruction
145 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
147 cond = condition_met (cccc);
150 TRACE_BRANCH1 (cond);
157 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
159 "bsh r<reg2>, r<reg3>"
162 TRACE_ALU_INPUT1 (GR[reg2]);
164 value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
165 | MOVED32 (GR[reg2], 31, 24, 23, 16)
166 | MOVED32 (GR[reg2], 7, 0, 15, 8)
167 | MOVED32 (GR[reg2], 15, 8, 7, 0));
170 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
171 if (value == 0) PSW |= PSW_Z;
172 if (value & 0x80000000) PSW |= PSW_S;
173 if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
175 TRACE_ALU_RESULT (GR[reg3]);
179 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
181 "bsw r<reg2>, r<reg3>"
183 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
185 TRACE_ALU_INPUT1 (GR[reg2]);
189 value |= (GR[reg2] << 24);
190 value |= ((GR[reg2] << 8) & 0x00ff0000);
191 value |= ((GR[reg2] >> 8) & 0x0000ff00);
194 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
196 if (value == 0) PSW |= PSW_Z;
197 if (value & 0x80000000) PSW |= PSW_S;
198 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
200 TRACE_ALU_RESULT (GR[reg3]);
204 0000001000,iiiiii:II:::callt
212 adr = (CTBP & ~1) + (imm6 << 1);
213 off = load_mem (adr, 2) & ~1; /* Force alignment */
214 nia = (CTBP & ~1) + off;
215 TRACE_BRANCH3 (adr, CTBP, off);
220 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
221 "clr1 <bit3>, <disp16>[r<reg1>]"
223 COMPAT_2 (OP_87C0 ());
226 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
228 "clr1 r<reg2>, [r<reg1>]"
230 COMPAT_2 (OP_E407E0 ());
235 0000011111100000 + 0000000101000100:X:::ctret
240 PSW = (CTPSW & (CPU)->psw_mask);
245 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
247 "cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
249 int cond = condition_met (cccc);
250 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
251 GR[reg3] = cond ? GR[reg1] : GR[reg2];
252 TRACE_ALU_RESULT (GR[reg3]);
255 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
257 "cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
259 int cond = condition_met (cccc);
260 TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
261 GR[reg3] = cond ? imm5 : GR[reg2];
262 TRACE_ALU_RESULT (GR[reg3]);
266 rrrrr,001111,RRRRR:I:::cmp
267 "cmp r<reg1>, r<reg2>"
269 COMPAT_1 (OP_1E0 ());
272 rrrrr,010011,iiiii:II:::cmp
273 "cmp <imm5>, r<reg2>"
275 COMPAT_1 (OP_260 ());
281 0000011111100000 + 0000000101100000:X:::di
284 COMPAT_2 (OP_16007E0 ());
290 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
291 // "dispose <imm5>, <list12>"
292 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
294 "dispose <imm5>, <list12>":RRRRR == 0
295 "dispose <imm5>, <list12>, [reg1]"
300 trace_input ("dispose", OP_PUSHPOP1, 0);
302 SP += (OP[3] & 0x3e) << 1;
304 /* Load the registers with lower number registers being retrieved
305 from higher addresses. */
307 if ((OP[3] & (1 << type1_regs[ i ])))
309 State.regs[ 20 + i ] = load_mem (SP, 4);
313 if ((OP[3] & 0x1f0000) != 0)
315 nia = State.regs[ (OP[3] >> 16) & 0x1f];
318 trace_output (OP_PUSHPOP1);
323 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
325 "div r<reg1>, r<reg2>, r<reg3>"
327 COMPAT_2 (OP_2C007E0 ());
332 rrrrr!0,000010,RRRRR!0:I:::divh
333 "divh r<reg1>, r<reg2>"
338 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
340 "divh r<reg1>, r<reg2>, r<reg3>"
342 COMPAT_2 (OP_28007E0 ());
347 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
349 "divhu r<reg1>, r<reg2>, r<reg3>"
351 COMPAT_2 (OP_28207E0 ());
356 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
358 "divu r<reg1>, r<reg2>, r<reg3>"
360 COMPAT_2 (OP_2C207E0 ());
365 1000011111100000 + 0000000101100000:X:::ei
368 COMPAT_2 (OP_16087E0 ());
374 0000011111100000 + 0000000100100000:X:::halt
377 COMPAT_2 (OP_12007E0 ());
383 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
385 "hsw r<reg2>, r<reg3>"
388 TRACE_ALU_INPUT1 (GR[reg2]);
392 value |= (GR[reg2] << 16);
396 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
398 if (value == 0) PSW |= PSW_Z;
399 if (value & 0x80000000) PSW |= PSW_S;
400 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
402 TRACE_ALU_RESULT (GR[reg3]);
408 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
409 "jarl <disp22>, r<reg2>"
413 TRACE_BRANCH1 (GR[reg2]);
419 00000000011,RRRRR:I:::jmp
429 0000011110,dddddd + ddddddddddddddd,0:V:::jr
439 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
440 "ld.b <disp16>[r<reg1>], r<reg2>"
442 COMPAT_2 (OP_700 ());
445 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
446 "ld.h <disp16>[r<reg1>], r<reg2>"
448 COMPAT_2 (OP_720 ());
451 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
452 "ld.w <disp16>[r<reg1>], r<reg2>"
454 COMPAT_2 (OP_10720 ());
457 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
459 "ld.bu <disp16>[r<reg1>], r<reg2>"
461 COMPAT_2 (OP_10780 ());
464 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
466 "ld.hu <disp16>[r<reg1>], r<reg2>"
468 COMPAT_2 (OP_107E0 ());
473 regID,111111,RRRRR + 0000000000100000:IX:::ldsr
474 "ldsr r<reg1>, s<regID>"
476 TRACE_ALU_INPUT1 (GR[reg1]);
478 if (&PSW == &SR[regID])
479 PSW = (GR[reg1] & (CPU)->psw_mask);
481 SR[regID] = GR[reg1];
483 TRACE_ALU_RESULT (SR[regID]);
489 rrrrr!0,000000,RRRRR:I:::mov
490 "mov r<reg1>, r<reg2>"
494 TRACE_ALU_RESULT (GR[reg2]);
498 rrrrr!0,010000,iiiii:II:::mov
499 "mov <imm5>, r<reg2>"
501 COMPAT_1 (OP_200 ());
504 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
506 "mov <imm32>, r<reg1>"
509 trace_input ("mov", OP_IMM_REG, 4);
510 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
511 trace_output (OP_IMM_REG);
517 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
518 "movea <simm16>, r<reg1>, r<reg2>"
520 TRACE_ALU_INPUT2 (GR[reg1], simm16);
521 GR[reg2] = GR[reg1] + simm16;
522 TRACE_ALU_RESULT (GR[reg2]);
528 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
529 "movhi <uimm16>, r<reg1>, r<reg2>"
531 COMPAT_2 (OP_640 ());
537 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
539 "mul r<reg1>, r<reg2>, r<reg3>"
541 COMPAT_2 (OP_22007E0 ());
544 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
546 "mul <imm9>, r<reg2>, r<reg3>"
548 COMPAT_2 (OP_24007E0 ());
553 rrrrr!0,000111,RRRRR:I:::mulh
554 "mulh r<reg1>, r<reg2>"
559 rrrrr!0,010111,iiiii:II:::mulh
560 "mulh <imm5>, r<reg2>"
562 COMPAT_1 (OP_2E0 ());
568 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
569 "mulhi <uimm16>, r<reg1>, r<reg2>"
571 COMPAT_2 (OP_6E0 ());
577 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
579 "mulu r<reg1>, r<reg2>, r<reg3>"
581 COMPAT_2 (OP_22207E0 ());
584 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
586 "mulu <imm9>, r<reg2>, r<reg3>"
588 COMPAT_2 (OP_24207E0 ());
594 0000000000000000:I:::nop
597 /* do nothing, trace nothing */
603 rrrrr,000001,RRRRR:I:::not
604 "not r<reg1>, r<reg2>"
612 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
613 "not1 <bit3>, <disp16>[r<reg1>]"
615 COMPAT_2 (OP_47C0 ());
618 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
620 "not1 r<reg2>, r<reg1>"
622 COMPAT_2 (OP_E207E0 ());
628 rrrrr,001000,RRRRR:I:::or
629 "or r<reg1>, r<reg2>"
631 COMPAT_1 (OP_100 ());
637 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
638 "ori <uimm16>, r<reg1>, r<reg2>"
640 COMPAT_2 (OP_680 ());
646 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
648 "prepare <list12>, <imm5>"
653 trace_input ("prepare", OP_PUSHPOP1, 0);
655 /* Store the registers with lower number registers being placed at
657 for (i = 0; i < 12; i++)
658 if ((OP[3] & (1 << type1_regs[ i ])))
661 store_mem (SP, 4, State.regs[ 20 + i ]);
664 SP -= (OP[3] & 0x3e) << 1;
666 trace_output (OP_PUSHPOP1);
670 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
672 "prepare <list12>, <imm5>, sp"
674 COMPAT_2 (OP_30780 ());
677 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
679 "prepare <list12>, <imm5>, <uimm16>"
681 COMPAT_2 (OP_B0780 ());
684 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
686 "prepare <list12>, <imm5>, <uimm16>"
688 COMPAT_2 (OP_130780 ());
691 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
693 "prepare <list12>, <imm5>, <uimm32>"
695 COMPAT_2 (OP_1B0780 ());
701 0000011111100000 + 0000000101000000:X:::reti
709 else if ((PSW & PSW_NP))
725 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
726 "sar r<reg1>, r<reg2>"
728 COMPAT_2 (OP_A007E0 ());
731 rrrrr,010101,iiiii:II:::sar
732 "sar <imm5>, r<reg2>"
734 COMPAT_1 (OP_2A0 ());
740 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
742 "sasf %s<cccc>, r<reg2>"
744 COMPAT_2 (OP_20007E0 ());
751 rrrrr!0,000110,RRRRR:I:::satadd
752 "satadd r<reg1>, r<reg2>"
757 rrrrr!0,010001,iiiii:II:::satadd
758 "satadd <imm5>, r<reg2>"
760 COMPAT_1 (OP_220 ());
766 rrrrr!0,000101,RRRRR:I:::satsub
767 "satsub r<reg1>, r<reg2>"
775 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
776 "satsubi <simm16>, r<reg1>, r<reg2>"
778 COMPAT_2 (OP_660 ());
784 rrrrr!0,000100,RRRRR:I:::satsubr
785 "satsubr r<reg1>, r<reg2>"
793 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
794 "setf %s<cccc>, r<reg2>"
796 COMPAT_2 (OP_7E0 ());
802 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
803 "set1 <bit3>, <disp16>[r<reg1>]"
805 COMPAT_2 (OP_7C0 ());
808 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
810 "set1 r<reg2>, [r<reg1>]"
812 COMPAT_2 (OP_E007E0 ());
818 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
819 "shl r<reg1>, r<reg2>"
821 COMPAT_2 (OP_C007E0 ());
824 rrrrr,010110,iiiii:II:::shl
825 "shl <imm5>, r<reg2>"
827 COMPAT_1 (OP_2C0 ());
833 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
834 "shr r<reg1>, r<reg2>"
836 COMPAT_2 (OP_8007E0 ());
839 rrrrr,010100,iiiii:II:::shr
840 "shr <imm5>, r<reg2>"
842 COMPAT_1 (OP_280 ());
848 rrrrr,0110,ddddddd:IV:::sld.b
849 "sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
850 "sld.b <disp7>[ep], r<reg2>"
852 unsigned32 addr = EP + disp7;
853 unsigned32 result = load_mem (addr, 1);
857 TRACE_LD_NAME ("sld.bu", addr, result);
861 result = EXTEND8 (result);
863 TRACE_LD (addr, result);
867 rrrrr,1000,ddddddd:IV:::sld.h
868 "sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
869 "sld.h <disp8>[ep], r<reg2>"
871 unsigned32 addr = EP + disp8;
872 unsigned32 result = load_mem (addr, 2);
876 TRACE_LD_NAME ("sld.hu", addr, result);
880 result = EXTEND16 (result);
882 TRACE_LD (addr, result);
886 rrrrr,1010,dddddd,0:IV:::sld.w
887 "sld.w <disp8>[ep], r<reg2>"
889 unsigned32 addr = EP + disp8;
890 unsigned32 result = load_mem (addr, 4);
892 TRACE_LD (addr, result);
895 rrrrr!0,0000110,dddd:IV:::sld.bu
897 "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
898 "sld.bu <disp4>[ep], r<reg2>"
900 unsigned32 addr = EP + disp4;
901 unsigned32 result = load_mem (addr, 1);
904 result = EXTEND8 (result);
906 TRACE_LD_NAME ("sld.b", addr, result);
911 TRACE_LD (addr, result);
915 rrrrr!0,0000111,dddd:IV:::sld.hu
917 "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
918 "sld.hu <disp5>[ep], r<reg2>"
920 unsigned32 addr = EP + disp5;
921 unsigned32 result = load_mem (addr, 2);
924 result = EXTEND16 (result);
926 TRACE_LD_NAME ("sld.h", addr, result);
931 TRACE_LD (addr, result);
936 rrrrr,0111,ddddddd:IV:::sst.b
937 "sst.b r<reg2>, <disp7>[ep]"
939 COMPAT_1 (OP_380 ());
942 rrrrr,1001,ddddddd:IV:::sst.h
943 "sst.h r<reg2>, <disp8>[ep]"
945 COMPAT_1 (OP_480 ());
948 rrrrr,1010,dddddd,1:IV:::sst.w
949 "sst.w r<reg2>, <disp8>[ep]"
951 COMPAT_1 (OP_501 ());
955 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
956 "st.b r<reg2>, <disp16>[r<reg1>]"
958 COMPAT_2 (OP_740 ());
961 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
962 "st.h r<reg2>, <disp16>[r<reg1>]"
964 COMPAT_2 (OP_760 ());
967 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
968 "st.w r<reg2>, <disp16>[r<reg1>]"
970 COMPAT_2 (OP_10760 ());
974 rrrrr,111111,regID + 0000000001000000:IX:::stsr
975 "stsr s<regID>, r<reg2>"
977 TRACE_ALU_INPUT1 (SR[regID]);
978 GR[reg2] = SR[regID];
979 TRACE_ALU_RESULT (GR[reg2]);
983 rrrrr,001101,RRRRR:I:::sub
984 "sub r<reg1>, r<reg2>"
986 COMPAT_1 (OP_1A0 ());
990 rrrrr,001100,RRRRR:I:::subr
991 "subr r<reg1>, r<reg2>"
993 COMPAT_1 (OP_180 ());
997 00000000010,RRRRR:I:::switch
1003 trace_input ("switch", OP_REG, 0);
1004 adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1005 nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1006 trace_output (OP_REG);
1010 00000000101,RRRRR:I:::sxb
1014 TRACE_ALU_INPUT1 (GR[reg1]);
1015 GR[reg1] = EXTEND8 (GR[reg1]);
1016 TRACE_ALU_RESULT (GR[reg1]);
1020 00000000111,RRRRR:I:::sxh
1024 TRACE_ALU_INPUT1 (GR[reg1]);
1025 GR[reg1] = EXTEND16 (GR[reg1]);
1026 TRACE_ALU_RESULT (GR[reg1]);
1030 00000111111,iiiii + 0000000100000000:X:::trap
1033 COMPAT_2 (OP_10007E0 ());
1037 rrrrr,001011,RRRRR:I:::tst
1038 "tst r<reg1>, r<reg2>"
1040 COMPAT_1 (OP_160 ());
1044 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1045 "tst1 <bit3>, <disp16>[r<reg1>]"
1047 COMPAT_2 (OP_C7C0 ());
1050 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1052 "tst1 r<reg2>, [r<reg1>]"
1054 COMPAT_2 (OP_E607E0 ());
1058 rrrrr,001001,RRRRR:I:::xor
1059 "xor r<reg1>, r<reg2>"
1061 COMPAT_1 (OP_120 ());
1065 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1066 "xori <uimm16>, r<reg1>, r<reg2>"
1068 COMPAT_2 (OP_6A0 ());
1072 00000000100,RRRRR:I:::zxb
1076 TRACE_ALU_INPUT1 (GR[reg1]);
1077 GR[reg1] = GR[reg1] & 0xff;
1078 TRACE_ALU_RESULT (GR[reg1]);
1082 00000000110,RRRRR:I:::zxh
1086 TRACE_ALU_INPUT1 (GR[reg1]);
1087 GR[reg1] = GR[reg1] & 0xffff;
1088 TRACE_ALU_RESULT (GR[reg1]);
1091 // Right field must be zero so that it doesn't clash with DIVH
1092 // Left field must be non-zero so that it doesn't clash with SWITCH
1093 11111,000010,00000:I:::break
1095 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1098 // New breakpoint: 0x7E0 0x7E0
1099 00000,111111,00000 + 00000,11111,100000:X:::ilgop
1101 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);