sim/v850/v850.igen

   1 :option::insn-bit-size:16
   2 :option::hi-bit-nr:15
   3
   4
   5 :option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
   6 # start-sanitize-v850e
   7 :option::format-names:XI,XII,XIII
   8 # end-sanitize-v850e
   9 # start-sanitize-v850eq
  10 :option::format-names:XIV,XV
  11 # end-sanitize-v850eq
  12 :option::format-names:Z
  13
  14
  15 :model::v850:v850:
  16
  17 # start-sanitize-v850e
  18 :option::multi-sim:true
  19 :model::v850e:v850e:
  20 # end-sanitize-v850e
  21
  22 # start-sanitize-v850eq
  23 :option::multi-sim:true
  24 :model::v850eq:v850eq:
  25 # end-sanitize-v850eq
  26
  27
  28
  29 // Cache macros
  30
  31 :cache::unsigned:reg1:RRRRR:(RRRRR)
  32 :cache::unsigned:reg2:rrrrr:(rrrrr)
  33 :cache::unsigned:reg3:wwwww:(wwwww)
  34 :cache::unsigned:regID:rrrrr:(rrrrr)
  35
  36 :cache::unsigned:disp4:dddd:(dddd)
  37 # start-sanitize-v850e
  38 :cache::unsigned:disp5:dddd:(dddd << 1)
  39 # end-sanitize-v850e
  40 :cache::unsigned:disp7:ddddddd:ddddddd
  41 :cache::unsigned:disp8:ddddddd:(ddddddd << 1)
  42 :cache::unsigned:disp8:dddddd:(dddddd << 2)
  43 :cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
  44 :cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
  45 :cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
  46 :cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
  47 :cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
  48
  49 :cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
  50 :cache::unsigned:imm6:iiiiii:iiiiii
  51 :cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
  52 # start-sanitize-v850eq
  53 :cache::unsigned:imm5:iiii:(32 - (iiii << 1))
  54 # end-sanitize-v850eq
  55 :cache::unsigned:imm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  56 :cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
  57 # start-sanitize-v850e
  58 :cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  59 :cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
  60 # end-sanitize-v850e
  61
  62 :cache::unsigned:vector:iiiii:iiiii
  63
  64 # start-sanitize-v850e
  65 :cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
  66 :cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
  67 # end-sanitize-v850e
  68
  69 :cache::unsigned:bit3:bbb:bbb
  70
  71
  72 // What do we do with an illegal instruction?
  73 :internal:::illegal
  74 {
  75   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  76                   (unsigned long) cia);
  77   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  78 }
  79
  80
  81
  82 // Add
  83
  84 rrrrr,001110,RRRRR:I:::add
  85 "add r<reg1>, r<reg2>"
  86 {
  87   COMPAT_1 (OP_1C0 ());
  88 }
  89
  90 rrrrr,010010,iiiii:II:::add
  91 "add <imm5>,r<reg2>"
  92 {
  93   COMPAT_1 (OP_240 ());
  94 }
  95
  96
  97
  98 // ADDI
  99 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
 100 "addi <imm16>, r<reg1>, r<reg2>"
 101 {
 102   COMPAT_2 (OP_600 ());
 103 }
 104
 105
 106
 107 // AND
 108 rrrrr,001010,RRRRR:I:::and
 109 "and r<reg1>, r<reg2>"
 110 {
 111   COMPAT_1 (OP_140 ());
 112 }
 113
 114
 115
 116 // ANDI
 117 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
 118 "andi <imm16>, r<reg1>, r<reg2>"
 119 {
 120   COMPAT_2 (OP_6C0 ());
 121 }
 122
 123
 124
 125 // Bcond
 126 // ddddd,1011,ddd,cccc:III:::Bcond
 127 // "b<cond> disp9"
 128
 129 ddddd,1011,ddd,0000:III:::bv
 130 "bv <disp9>"
 131 {
 132   COMPAT_1 (OP_580 ());
 133 }
 134
 135 ddddd,1011,ddd,0001:III:::bl
 136 "bl <disp9>"
 137 {
 138   COMPAT_1 (OP_581 ());
 139 }
 140
 141 ddddd,1011,ddd,0010:III:::be
 142 "be <disp9>"
 143 {
 144   COMPAT_1 (OP_582 ());
 145 }
 146
 147 ddddd,1011,ddd,0011:III:::bnh
 148 "bnh <disp9>"
 149 {
 150   COMPAT_1 (OP_583 ());
 151 }
 152
 153 ddddd,1011,ddd,0100:III:::bn
 154 "bn <disp9>"
 155 {
 156   COMPAT_1 (OP_584 ());
 157 }
 158
 159 ddddd,1011,ddd,0101:III:::br
 160 "br <disp9>"
 161 {
 162   COMPAT_1 (OP_585 ());
 163 }
 164
 165 ddddd,1011,ddd,0110:III:::blt
 166 "blt <disp9>"
 167 {
 168   COMPAT_1 (OP_586 ());
 169 }
 170
 171 ddddd,1011,ddd,0111:III:::ble
 172 "ble <disp9>"
 173 {
 174   COMPAT_1 (OP_587 ());
 175 }
 176
 177 ddddd,1011,ddd,1000:III:::bnv
 178 "bnv <disp9>"
 179 {
 180   COMPAT_1 (OP_588 ());
 181 }
 182
 183 ddddd,1011,ddd,1001:III:::bnl
 184 "bnl <disp9>"
 185 {
 186   COMPAT_1 (OP_589 ());
 187 }
 188
 189 ddddd,1011,ddd,1010:III:::bne
 190 "bne <disp9>"
 191 {
 192   COMPAT_1 (OP_58A ());
 193 }
 194
 195 ddddd,1011,ddd,1011:III:::bh
 196 "bh <disp9>"
 197 {
 198   COMPAT_1 (OP_58B ());
 199 }
 200
 201 ddddd,1011,ddd,1100:III:::bp
 202 "bp <disp9>"
 203 {
 204   COMPAT_1 (OP_58C ());
 205 }
 206
 207 ddddd,1011,ddd,1101:III:::bsa
 208 "bsa <disp9>"
 209 {
 210   COMPAT_1 (OP_58D ());
 211 }
 212
 213 ddddd,1011,ddd,1110:III:::bge
 214 "bge <disp9>"
 215 {
 216   COMPAT_1 (OP_58E ());
 217 }
 218
 219 ddddd,1011,ddd,1111:III:::bgt
 220 "bgt <disp9>"
 221 {
 222   COMPAT_1 (OP_58F ());
 223 }
 224
 225
 226
 227 // start-sanitize-v850e
 228 // BSH
 229 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 230 *v850e
 231 // start-sanitize-v850eq
 232 *v850eq
 233 // end-sanitize-v850eq
 234 "bsh r<reg2>, r<reg3>"
 235 {
 236   COMPAT_2 (OP_34207E0 ());
 237 }
 238
 239
 240
 241 // end-sanitize-v850e
 242 // start-sanitize-v850e
 243 // BSW
 244 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 245 *v850e
 246 // start-sanitize-v850eq
 247 *v850eq
 248 // end-sanitize-v850eq
 249 "bsw r<reg2>, reg3>"
 250 {
 251   COMPAT_2 (OP_34007E0 ());
 252 }
 253
 254
 255
 256 // end-sanitize-v850e
 257 // start-sanitize-v850e
 258 // CALLT
 259 0000001000,iiiiii:II:::callt
 260 *v850e
 261 // start-sanitize-v850eq
 262 *v850eq
 263 // end-sanitize-v850eq
 264 "callt <imm6>"
 265 {
 266   COMPAT_1 (OP_200 ());
 267 }
 268
 269
 270
 271 // end-sanitize-v850e
 272 // CLR1
 273 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
 274 "clr1 <bit3>, <disp16>[r<reg1>]"
 275 {
 276   COMPAT_2 (OP_87C0 ());
 277 }
 278
 279 // start-sanitize-v850e
 280 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 281 *v850e
 282 // start-sanitize-v850eq
 283 *v850eq
 284 // end-sanitize-v850eq
 285 "clr1 r<reg2>, [r<reg1>]"
 286 {
 287   COMPAT_2 (OP_E407E0 ());
 288 }
 289
 290
 291
 292 // end-sanitize-v850e
 293 // start-sanitize-v850e
 294 // CTRET
 295 0000011111100000 + 0000000101000100:X:::ctret
 296 *v850e
 297 // start-sanitize-v850eq
 298 *v850eq
 299 // end-sanitize-v850eq
 300 "ctret"
 301 {
 302   COMPAT_2 (OP_14407E0 ());
 303 }
 304
 305
 306
 307 // end-sanitize-v850e
 308 // start-sanitize-v850e
 309 // CMOV
 310 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 311 *v850e
 312 // start-sanitize-v850eq
 313 *v850eq
 314 // end-sanitize-v850eq
 315 "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
 316 {
 317   COMPAT_2 (OP_32007E0 ());
 318 }
 319
 320 // end-sanitize-v850e
 321 // start-sanitize-v850e
 322 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 323 *v850e
 324 // start-sanitize-v850eq
 325 *v850eq
 326 // end-sanitize-v850eq
 327 "cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
 328 {
 329   COMPAT_2 (OP_30007E0 ());
 330 }
 331
 332
 333
 334 // end-sanitize-v850e
 335 // CMP
 336 rrrrr,001111,RRRRR:I:::cmp
 337 "cmp r<reg1>, r<reg2>"
 338 {
 339   COMPAT_1 (OP_1E0 ());
 340 }
 341
 342 rrrrr,010011,iiiii:II:::cmp
 343 "cmp <imm5>, r<reg2>"
 344 {
 345   COMPAT_1 (OP_260 ());
 346 }
 347
 348
 349
 350 // DI
 351 0000011111100000 + 0000000101100000:X:::di
 352 "di"
 353 {
 354   COMPAT_2 (OP_16007E0 ());
 355 }
 356
 357
 358
 359 // start-sanitize-v850e
 360 // DISPOSE
 361 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
 362 // "dispose <imm5>, <list12>"
 363 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
 364 *v850e
 365 // start-sanitize-v850eq
 366 *v850eq
 367 // end-sanitize-v850eq
 368 "dispose <imm5>, <list12>":RRRRR == 0
 369 "dispose <imm5>, <list12>, [reg1]"
 370 {
 371   COMPAT_2 (OP_640 ());
 372 }
 373
 374
 375
 376 // end-sanitize-v850e
 377 // start-sanitize-v850e
 378 // DIV
 379 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 380 *v850e
 381 "div r<reg1>, r<reg2>, r<reg3>"
 382 {
 383   COMPAT_2 (OP_2C007E0 ());
 384 }
 385
 386
 387
 388
 389 // end-sanitize-v850e
 390 // DIVH
 391 rrrrr!0,000010,RRRRR!0:I:::divh
 392 "divh r<reg1>, r<reg2>"
 393 {
 394   COMPAT_1 (OP_40 ());
 395 }
 396
 397 // start-sanitize-v850e
 398 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 399 *v850e
 400 "divh r<reg1>, r<reg2>, r<reg3>"
 401 {
 402   COMPAT_2 (OP_28007E0 ());
 403 }
 404
 405
 406
 407 // end-sanitize-v850e
 408 // start-sanitize-v850e
 409 // DIVHU
 410 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 411 *v850e
 412 "divhu r<reg1>, r<reg2>, r<reg3>"
 413 {
 414   COMPAT_2 (OP_28207E0 ());
 415 }
 416
 417
 418
 419 // end-sanitize-v850e
 420 // start-sanitize-v850e
 421 // DIVU
 422 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 423 *v850e
 424 "divu r<reg1>, r<reg2>, r<reg3>"
 425 {
 426   COMPAT_2 (OP_2C207E0 ());
 427 }
 428
 429
 430
 431 // end-sanitize-v850e
 432 // EI
 433 1000011111100000 + 0000000101100000:X:::ei
 434 "ei"
 435 {
 436   COMPAT_2 (OP_16087E0 ());
 437 }
 438
 439
 440
 441 // HALT
 442 0000011111100000 + 0000000100100000:X:::halt
 443 "halt"
 444 {
 445   COMPAT_2 (OP_12007E0 ());
 446 }
 447
 448
 449
 450 // start-sanitize-v850e
 451 // HSW
 452 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 453 *v850e
 454 // start-sanitize-v850eq
 455 *v850eq
 456 // end-sanitize-v850eq
 457 "hsw r<reg2>, r<reg3>"
 458 {
 459   COMPAT_2 (OP_34407E0 ());
 460 }
 461
 462
 463
 464 // end-sanitize-v850e
 465 // JARL
 466 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 467 "jarl <disp22>, r<reg2>"
 468 {
 469   COMPAT_2 (OP_780 ());
 470 }
 471
 472
 473
 474 // JMP
 475 00000000011,RRRRR:I:::jmp
 476 "jmp [r<reg1>]"
 477 {
 478   SAVE_1;
 479   trace_input ("jmp", OP_REG, 0);
 480   nia = State.regs[ reg1 ];
 481   trace_output (OP_REG);
 482 }
 483
 484
 485
 486 // JR
 487 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 488 "jr <disp22>"
 489 {
 490   COMPAT_2 (OP_780 ());
 491 }
 492
 493
 494
 495 // LD
 496 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 497 "ld.b <disp16>[r<reg1>, r<reg2>"
 498 {
 499   COMPAT_2 (OP_700 ());
 500 }
 501
 502 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 503 "ld.h <disp16>[r<reg1>], r<reg2>"
 504 {
 505   COMPAT_2 (OP_720 ());
 506 }
 507
 508 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 509 "ld.w <disp16>[r<reg1>], r<reg2>"
 510 {
 511   COMPAT_2 (OP_10720 ());
 512 }
 513
 514 // start-sanitize-v850e
 515 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 516 *v850e
 517 // start-sanitize-v850eq
 518 *v850eq
 519 // end-sanitize-v850eq
 520 "ld.bu <disp16>[r<reg1>], r<reg2>"
 521 {
 522   COMPAT_2 (OP_10780 ());
 523 }
 524
 525 // end-sanitize-v850e
 526 // start-sanitize-v850e
 527 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 528 *v850e
 529 // start-sanitize-v850eq
 530 *v850eq
 531 // end-sanitize-v850eq
 532 "ld.hu <disp16>[r<reg1>], r<reg2>"
 533 {
 534   COMPAT_2 (OP_107E0 ());
 535 }
 536
 537
 538 // end-sanitize-v850e
 539 // LDSR
 540 //rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 541 //"ldsr r<reg2>, r<regID>"
 542 //{
 543 //  COMPAT_2 (OP_2007E0 ());
 544 //}
 545 rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 546 "ldsr r<reg1>, r<regID>"
 547 {
 548   SAVE_2;
 549   trace_input ("ldsr", OP_LDSR, 0);
 550
 551   if (&PSW == &State.sregs[ regID ])
 552     PSW = (State.regs[ reg1 ] & (CPU)->psw_mask);
 553   else
 554     State.sregs[ regID ] = State.regs[ reg1 ];
 555
 556   trace_output (OP_LDSR);
 557 }
 558
 559
 560
 561 // MOV
 562 rrrrr!0,000000,RRRRR:I:::mov
 563 "mov r<reg1>, r<reg2>"
 564 {
 565   COMPAT_1 (OP_0 ());
 566 }
 567
 568 rrrrr!0,010000,iiiii:II:::mov
 569 "mov <imm5>, r<reg2>"
 570 {
 571   COMPAT_1 (OP_200 ());
 572 }
 573
 574 // start-sanitize-v850e
 575 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
 576 *v850e
 577 // start-sanitize-v850eq
 578 *v850eq
 579 // end-sanitize-v850eq
 580 "mov <imm32>, r<reg1>"
 581 {
 582   COMPAT_2 (OP_620 ());
 583 }
 584
 585
 586
 587 // end-sanitize-v850e
 588 // MOVEA
 589 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
 590 "movea <imm16>, r<reg1>, r<reg2>"
 591 {
 592   COMPAT_2 (OP_620 ());
 593 }
 594
 595
 596
 597 // MOVHI
 598 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
 599 "movhi <imm16>, r<reg1>, r<reg2>"
 600 {
 601   COMPAT_2 (OP_640 ());
 602 }
 603
 604
 605
 606 // start-sanitize-v850e
 607 // MUL
 608 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 609 *v850e
 610 // start-sanitize-v850eq
 611 *v850eq
 612 // end-sanitize-v850eq
 613 "mul r<reg1>, r<reg2>, r<reg3>"
 614 {
 615   COMPAT_2 (OP_22007E0 ());
 616 }
 617
 618 // end-sanitize-v850e
 619 // start-sanitize-v850e
 620 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 621 *v850e
 622 // start-sanitize-v850eq
 623 *v850eq
 624 // end-sanitize-v850eq
 625 "mul <imm9>, r<reg2>, r<reg3>"
 626 {
 627   COMPAT_2 (OP_24007E0 ());
 628 }
 629
 630
 631
 632 // end-sanitize-v850e
 633 // MULH
 634 rrrrr!0,000111,RRRRR:I:::mulh
 635 "mulh r<reg1>, r<reg2>"
 636 {
 637   COMPAT_1 (OP_E0 ());
 638 }
 639
 640 rrrrr!0,010111,iiiii:II:::mulh
 641 "mulh <imm5>, r<reg2>"
 642 {
 643   COMPAT_1 (OP_2E0 ());
 644 }
 645
 646
 647
 648 // MULHI
 649 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
 650 "mulhi <imm16>, r<reg1>, r<reg2>"
 651 {
 652   COMPAT_2 (OP_6E0 ());
 653 }
 654
 655
 656
 657 // start-sanitize-v850e
 658 // MULU
 659 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 660 *v850e
 661 // start-sanitize-v850eq
 662 *v850eq
 663 // end-sanitize-v850eq
 664 "mulu r<reg1>, r<reg2>, r<reg3>"
 665 {
 666   COMPAT_2 (OP_22207E0 ());
 667 }
 668
 669 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 670 *v850e
 671 // start-sanitize-v850eq
 672 *v850eq
 673 // end-sanitize-v850eq
 674 "mulu <imm9>, r<reg2>, r<reg3>"
 675 {
 676   COMPAT_2 (OP_24207E0 ());
 677 }
 678
 679
 680
 681 // end-sanitize-v850e
 682 // NOP
 683 0000000000000000:I:::nop
 684 "nop"
 685 {
 686   COMPAT_1 (OP_0 ());
 687 }
 688
 689
 690
 691 // NOT
 692 rrrrr,000001,RRRRR:I:::not
 693 "not r<reg1>, r<reg2>"
 694 {
 695   COMPAT_1 (OP_20 ());
 696 }
 697
 698
 699
 700 // NOT1
 701 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
 702 "not1 <bit3>, <disp16>[r<reg1>]"
 703 {
 704   COMPAT_2 (OP_47C0 ());
 705 }
 706
 707 // start-sanitize-v850e
 708 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 709 *v850e
 710 // start-sanitize-v850eq
 711 *v850eq
 712 // end-sanitize-v850eq
 713 "not1 r<reg2>, r<reg1>"
 714 {
 715   COMPAT_2 (OP_E207E0 ());
 716 }
 717
 718
 719
 720 // end-sanitize-v850e
 721 // OR
 722 rrrrr,001000,RRRRR:I:::or
 723 "or r<reg1>, r<reg2>"
 724 {
 725   COMPAT_1 (OP_100 ());
 726 }
 727
 728
 729
 730 // ORI
 731 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 732 "ori <imm16>, r<reg1>, r<reg2>"
 733 {
 734   COMPAT_2 (OP_680 ());
 735 }
 736
 737
 738
 739 // start-sanitize-v850e
 740 // PREPARE
 741 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
 742 *v850e
 743 // start-sanitize-v850eq
 744 *v850eq
 745 // end-sanitize-v850eq
 746 "prepare <list12>, <imm5>"
 747 {
 748   int  i;
 749   SAVE_2;
 750
 751   trace_input ("prepare", OP_PUSHPOP1, 0);
 752
 753   /* Store the registers with lower number registers being placed at
 754      higher addresses.  */
 755   for (i = 0; i < 12; i++)
 756     if ((OP[3] & (1 << type1_regs[ i ])))
 757       {
 758         SP -= 4;
 759         store_mem (SP, 4, State.regs[ 20 + i ]);
 760       }
 761
 762   SP -= (OP[3] & 0x3e) << 1;
 763
 764   trace_output (OP_PUSHPOP1);
 765 }
 766
 767
 768 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
 769 *v850e
 770 // start-sanitize-v850eq
 771 *v850eq
 772 // end-sanitize-v850eq
 773 "prepare <list12>, <imm5>, sp"
 774 {
 775   COMPAT_2 (OP_30780 ());
 776 }
 777
 778 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
 779 *v850e
 780 // start-sanitize-v850eq
 781 *v850eq
 782 // end-sanitize-v850eq
 783 "prepare <list12>, <imm5>, <uimm16>"
 784 {
 785   COMPAT_2 (OP_B0780 ());
 786 }
 787
 788 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
 789 *v850e
 790 // start-sanitize-v850eq
 791 *v850eq
 792 // end-sanitize-v850eq
 793 "prepare <list12>, <imm5>, <uimm16>"
 794 {
 795   COMPAT_2 (OP_130780 ());
 796 }
 797
 798 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
 799 *v850e
 800 // start-sanitize-v850eq
 801 *v850eq
 802 // end-sanitize-v850eq
 803 "prepare <list12>, <imm5>, <uimm32>"
 804 {
 805   COMPAT_2 (OP_1B0780 ());
 806 }
 807
 808
 809
 810 // end-sanitize-v850e
 811 // RETI
 812 0000011111100000 + 0000000101000000:X:::reti
 813 "reti"
 814 {
 815   COMPAT_2 (OP_14007E0 ());
 816 }
 817
 818
 819
 820 // SAR
 821 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
 822 "sar r<reg1>, r<reg2>"
 823 {
 824   COMPAT_2 (OP_A007E0 ());
 825 }
 826
 827 rrrrr,010101,iiiii:II:::sar
 828 "sar <imm5>, r<reg2>"
 829 {
 830   COMPAT_1 (OP_2A0 ());
 831 }
 832
 833
 834
 835 // start-sanitize-v850e
 836 // SASF
 837 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
 838 *v850e
 839 // start-sanitize-v850eq
 840 *v850eq
 841 // end-sanitize-v850eq
 842 "sasf <cccc>, r<reg2>"
 843 {
 844   COMPAT_2 (OP_20007E0 ());
 845 }
 846
 847
 848
 849
 850 // end-sanitize-v850e
 851 // SATADD
 852 rrrrr!0,000110,RRRRR:I:::satadd
 853 "satadd r<reg1>, r<reg2>"
 854 {
 855   COMPAT_1 (OP_C0 ());
 856 }
 857
 858 rrrrr!0,010001,iiiii:II:::satadd
 859 "satadd <imm5>, r<reg2>"
 860 {
 861   COMPAT_1 (OP_220 ());
 862 }
 863
 864
 865
 866 // SATSUB
 867 rrrrr!0,000101,RRRRR:I:::satsub
 868 "satsub r<reg1>, r<reg2>"
 869 {
 870   COMPAT_1 (OP_A0 ());
 871 }
 872
 873
 874
 875 // SATSUBI
 876 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
 877 "satsubi <imm16>, r<reg1>, r<reg2>"
 878 {
 879   COMPAT_2 (OP_660 ());
 880 }
 881
 882
 883
 884 // SATSUBR
 885 rrrrr!0,000100,RRRRR:I:::satsubr
 886 "satsubr r<reg1>, r<reg2>"
 887 {
 888   COMPAT_1 (OP_80 ());
 889 }
 890
 891
 892
 893 // SETF
 894 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
 895 "setf <cccc>, r<reg2>"
 896 {
 897   COMPAT_2 (OP_7E0 ());
 898 }
 899
 900
 901
 902 // SET1
 903 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
 904 "set1 <bit3>, <disp16>[r<reg1>]"
 905 {
 906   COMPAT_2 (OP_7C0 ());
 907 }
 908
 909 // start-sanitize-v850e
 910 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
 911 *v850e
 912 // start-sanitize-v850eq
 913 *v850eq
 914 // end-sanitize-v850eq
 915 "set1 r<reg2>, [r<reg1>]"
 916 {
 917   COMPAT_2 (OP_E007E0 ());
 918 }
 919
 920
 921
 922 // end-sanitize-v850e
 923 // SHL
 924 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
 925 "shl r<reg1>, r<reg2>"
 926 {
 927   COMPAT_2 (OP_C007E0 ());
 928 }
 929
 930 rrrrr,010110,iiiii:II:::shl
 931 "shl <imm5>, r<reg2>"
 932 {
 933   COMPAT_1 (OP_2C0 ());
 934 }
 935
 936
 937
 938 // SHR
 939 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
 940 "shr r<reg1>, r<reg2>"
 941 {
 942   COMPAT_2 (OP_8007E0 ());
 943 }
 944
 945 rrrrr,010100,iiiii:II:::shr
 946 "shr <imm5>, r<reg2>"
 947 {
 948   COMPAT_1 (OP_280 ());
 949 }
 950
 951
 952
 953 // SLD
 954 rrrrr,0110,ddddddd:IV:::sld.b
 955 "sld.b <disp7>[ep], r<reg2>"
 956 {
 957   COMPAT_1 (OP_300 ());
 958 }
 959
 960 rrrrr,1000,ddddddd:IV:::sld.h
 961 "sld.h <disp8>[ep], r<reg2>"
 962 {
 963   COMPAT_1 (OP_400 ());
 964 }
 965
 966 rrrrr,1010,dddddd,0:IV:::sld.w
 967 "sld.w <disp8>[ep], r<reg2>"
 968 {
 969   COMPAT_1 (OP_500 ());
 970 }
 971
 972 // start-sanitize-v850e
 973 rrrrr!0,0000110,dddd:IV:::sld.bu
 974 "sld.bu <disp4>[ep], r<reg2>"
 975 {
 976   unsigned long result;
 977
 978   SAVE_1;
 979   result = load_mem (State.regs[30] + disp4, 1);
 980
 981   /* start-sanitize-v850eq */
 982   if (PSW & PSW_US) {
 983     trace_input ("sld.b", OP_LOAD16, 1);
 984
 985     State.regs[ reg2 ] = EXTEND8 (result);
 986   } else {
 987   /* end-sanitize-v850eq */
 988   trace_input ("sld.bu", OP_LOAD16, 1);
 989   State.regs[ reg2 ] = result;
 990   /* start-sanitize-v850eq */
 991   }
 992   /* end-sanitize-v850eq */
 993   trace_output (OP_LOAD16);
 994 }
 995
 996 // end-sanitize-v850e
 997 // start-sanitize-v850e
 998 rrrrr!0,0000111,dddd:IV:::sld.hu
 999 "sld.hu <disp5>[ep], r<reg2>"
1000 {
1001   COMPAT_1 (OP_70 ());
1002 }
1003
1004 // end-sanitize-v850e
1005
1006
1007 // SST
1008 rrrrr,0111,ddddddd:IV:::sst.b
1009 "sst.b r<reg2>, <disp7>[ep]"
1010 {
1011   COMPAT_1 (OP_380 ());
1012 }
1013
1014 rrrrr,1001,ddddddd:IV:::sst.h
1015 "sst.h r<reg2>, <disp8>[ep]"
1016 {
1017   COMPAT_1 (OP_480 ());
1018 }
1019
1020 rrrrr,1010,dddddd,1:IV:::sst.w
1021 "sst.w r<reg2>, <disp8>[ep]"
1022 {
1023   COMPAT_1 (OP_501 ());
1024 }
1025
1026
1027
1028 // ST
1029 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
1030 "st.b r<reg2>, <disp16>[r<reg1>]"
1031 {
1032   COMPAT_2 (OP_740 ());
1033 }
1034
1035 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
1036 "st.h r<reg2>, <disp16>[r<reg1>]"
1037 {
1038   COMPAT_2 (OP_760 ());
1039 }
1040
1041 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1042 "st.w r<reg2>, <disp16>[r<reg1>]"
1043 {
1044   COMPAT_2 (OP_10760 ());
1045 }
1046
1047
1048
1049 // STSR
1050 //rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
1051 //"stsr r<regID>, r<reg2>"
1052 //{
1053 //  COMPAT_2 (OP_4007E0 ());
1054 //}
1055 rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
1056 "stsr r<regID>, r<reg1>"
1057 {
1058   SAVE_2;
1059
1060   trace_input ("stsr", OP_STSR, 0);
1061
1062   State.regs[ reg1 ] = State.sregs[ regID ];
1063
1064   trace_output (OP_STSR);
1065 }
1066
1067
1068
1069 // SUB
1070 rrrrr,001101,RRRRR:I:::sub
1071 "sub r<reg1>, r<reg2>"
1072 {
1073   COMPAT_1 (OP_1A0 ());
1074 }
1075
1076
1077
1078 // SUBR
1079 rrrrr,001100,RRRRR:I:::subr
1080 "subr r<reg1>, r<reg2>"
1081 {
1082   COMPAT_1 (OP_180 ());
1083 }
1084
1085
1086
1087 // start-sanitize-v850e
1088 // SWITCH
1089 00000000010,RRRRR:I:::switch
1090 *v850e
1091 // start-sanitize-v850eq
1092 *v850eq
1093 // end-sanitize-v850eq
1094 "switch r<reg1>"
1095 {
1096   COMPAT_1 (OP_40 ());
1097 }
1098 // end-sanitize-v850e
1099
1100
1101
1102 // start-sanitize-v850e
1103 // SXB
1104 00000000101,RRRRR:I:::sxb
1105 *v850e
1106 // start-sanitize-v850eq
1107 *v850eq
1108 // end-sanitize-v850eq
1109 "sxb r<reg1>"
1110 {
1111   COMPAT_1 (OP_A0 ());
1112 }
1113
1114
1115
1116 // end-sanitize-v850e
1117 // start-sanitize-v850e
1118 // SXH
1119 00000000111,RRRRR:I:::sxh
1120 *v850e
1121 // start-sanitize-v850eq
1122 *v850eq
1123 // end-sanitize-v850eq
1124 "sxh r<reg1>"
1125 {
1126   COMPAT_1 (OP_E0 ());
1127 }
1128
1129
1130
1131 // end-sanitize-v850e
1132 // TRAP
1133 00000111111,iiiii + 0000000100000000:X:::trap
1134 "trap <vector>"
1135 {
1136   COMPAT_2 (OP_10007E0 ());
1137 }
1138
1139
1140
1141 // TST
1142 rrrrr,001011,RRRRR:I:::tst
1143 "tst r<reg1>, r<reg2>"
1144 {
1145   COMPAT_1 (OP_160 ());
1146 }
1147
1148
1149
1150 // TST1
1151 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1152 "tst1 <bit3>, <disp16>[r<reg1>]"
1153 {
1154   COMPAT_2 (OP_C7C0 ());
1155 }
1156
1157 // start-sanitize-v850e
1158 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1159 *v850e
1160 // start-sanitize-v850eq
1161 *v850eq
1162 // end-sanitize-v850eq
1163 "tst1 r<reg2>, [r<reg1>]"
1164 {
1165   COMPAT_2 (OP_E607E0 ());
1166 }
1167
1168
1169
1170 // end-sanitize-v850e
1171 // XOR
1172 rrrrr,001001,RRRRR:I:::xor
1173 "xor r<reg1>, r<reg2>"
1174 {
1175   COMPAT_1 (OP_120 ());
1176 }
1177
1178
1179
1180 // XORI
1181 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1182 "xori <imm16>, r<reg1>, r<reg2>"
1183 {
1184   COMPAT_2 (OP_6A0 ());
1185 }
1186
1187
1188
1189 // start-sanitize-v850e
1190 // ZXB
1191 00000000100,RRRRR:I:::zxb
1192 *v850e
1193 // start-sanitize-v850eq
1194 *v850eq
1195 // end-sanitize-v850eq
1196 "zxb r<reg1>"
1197 {
1198   SAVE_1;
1199
1200   trace_input ("zxb", OP_REG, 0);
1201
1202   State.regs[ OP[0] ] &= 0xff;
1203
1204   trace_output (OP_REG);
1205 }
1206
1207
1208
1209 // end-sanitize-v850e
1210 // start-sanitize-v850e
1211 // ZXH
1212 00000000110,RRRRR:I:::zxh
1213 *v850e
1214 // start-sanitize-v850eq
1215 *v850eq
1216 // end-sanitize-v850eq
1217 "zxh r<reg1>"
1218 {
1219   SAVE_1;
1220
1221   trace_input ("zxh", OP_REG, 0);
1222
1223   State.regs[ OP[0] ] &= 0xffff;
1224
1225   trace_output (OP_REG);
1226 }
1227
1228
1229
1230 // end-sanitize-v850e
1231 // Special - breakpoint - illegal
1232 // Hopefully, in the future, this instruction will go away
1233 1111111111111111 + 1111111111111111:Z:::breakpoint
1234 *v850
1235 {
1236   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1237 }
1238
1239 // start-sanitize-v850e
1240 // First field could be any nonzero value.
1241 11111,000010,00000:I:::break
1242 {
1243   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1244 }
1245
1246 // end-sanitize-v850e
1247
1248
1249 // start-sanitize-v850eq
1250 // DIVHN
1251 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1252 *v850eq
1253 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1254 {
1255   signed32 quotient;
1256   signed32 remainder;
1257   signed32 divide_by;
1258   signed32 divide_this;
1259   boolean overflow = false;
1260   SAVE_2;
1261
1262   trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1263
1264   divide_by   = EXTEND16 (State.regs[ reg1 ]);
1265   divide_this = State.regs[ reg2 ];
1266
1267   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1268
1269   State.regs[ reg2 ] = quotient;
1270   State.regs[ reg3 ] = remainder;
1271
1272   /* Set condition codes.  */
1273   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1274
1275   if (overflow)      PSW |= PSW_OV;
1276   if (quotient == 0) PSW |= PSW_Z;
1277   if (quotient <  0) PSW |= PSW_S;
1278
1279   trace_output (OP_IMM_REG_REG_REG);
1280 }
1281
1282
1283
1284 // DIVHUN
1285 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1286 *v850eq
1287 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1288 {
1289   signed32 quotient;
1290   signed32 remainder;
1291   signed32 divide_by;
1292   signed32 divide_this;
1293   boolean overflow = false;
1294   SAVE_2;
1295
1296   trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1297
1298   divide_by   = State.regs[ reg1 ] & 0xffff;
1299   divide_this = State.regs[ reg2 ];
1300
1301   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1302
1303   State.regs[ reg2 ] = quotient;
1304   State.regs[ reg3 ] = remainder;
1305
1306   /* Set condition codes.  */
1307   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1308
1309   if (overflow)      PSW |= PSW_OV;
1310   if (quotient == 0) PSW |= PSW_Z;
1311   if (quotient & 0x80000000) PSW |= PSW_S;
1312
1313   trace_output (OP_IMM_REG_REG_REG);
1314 }
1315
1316
1317
1318 // DIVN
1319 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1320 *v850eq
1321 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1322 {
1323   signed32 quotient;
1324   signed32 remainder;
1325   signed32 divide_by;
1326   signed32 divide_this;
1327   boolean overflow = false;
1328   SAVE_2;
1329
1330   trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1331
1332   divide_by   = State.regs[ reg1 ];
1333   divide_this = State.regs[ reg2 ];
1334
1335   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1336
1337   State.regs[ reg2 ] = quotient;
1338   State.regs[ reg3 ] = remainder;
1339
1340   /* Set condition codes.  */
1341   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1342
1343   if (overflow)      PSW |= PSW_OV;
1344   if (quotient == 0) PSW |= PSW_Z;
1345   if (quotient <  0) PSW |= PSW_S;
1346
1347   trace_output (OP_IMM_REG_REG_REG);
1348 }
1349
1350
1351
1352 // DIVUN
1353 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1354 *v850eq
1355 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1356 {
1357   signed32 quotient;
1358   signed32 remainder;
1359   signed32 divide_by;
1360   signed32 divide_this;
1361   boolean overflow = false;
1362   SAVE_2;
1363
1364   trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1365
1366   divide_by   = State.regs[ reg1 ];
1367   divide_this = State.regs[ reg2 ];
1368
1369   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1370
1371   State.regs[ reg2 ] = quotient;
1372   State.regs[ reg3 ] = remainder;
1373
1374   /* Set condition codes.  */
1375   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1376
1377   if (overflow)      PSW |= PSW_OV;
1378   if (quotient == 0) PSW |= PSW_Z;
1379   if (quotient & 0x80000000) PSW |= PSW_S;
1380
1381   trace_output (OP_IMM_REG_REG_REG);
1382 }
1383
1384
1385
1386 // SDIVHN
1387 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1388 *v850eq
1389 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1390 {
1391   COMPAT_2 (OP_18007E0 ());
1392 }
1393
1394
1395
1396 // SDIVHUN
1397 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1398 *v850eq
1399 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1400 {
1401   COMPAT_2 (OP_18207E0 ());
1402 }
1403
1404
1405
1406 // SDIVN
1407 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1408 *v850eq
1409 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1410 {
1411   COMPAT_2 (OP_1C007E0 ());
1412 }
1413
1414
1415
1416 // SDIVUN
1417 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1418 *v850eq
1419 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1420 {
1421   COMPAT_2 (OP_1C207E0 ());
1422 }
1423
1424
1425
1426 // PUSHML
1427 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1428 *v850eq
1429 "pushml <list18>"
1430 {
1431   int i;
1432   SAVE_2;
1433
1434   trace_input ("pushml", OP_PUSHPOP3, 0);
1435
1436   /* Store the registers with lower number registers being placed at
1437      higher addresses.  */
1438
1439   for (i = 0; i < 15; i++)
1440     if ((OP[3] & (1 << type3_regs[ i ])))
1441       {
1442         SP -= 4;
1443         store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1444       }
1445
1446   if (OP[3] & (1 << 3))
1447     {
1448       SP -= 4;
1449
1450       store_mem (SP & ~ 3, 4, PSW);
1451     }
1452
1453   if (OP[3] & (1 << 19))
1454     {
1455       SP -= 8;
1456
1457       if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1458         {
1459           store_mem ((SP + 4) & ~ 3, 4, FEPC);
1460           store_mem ( SP      & ~ 3, 4, FEPSW);
1461         }
1462       else
1463         {
1464           store_mem ((SP + 4) & ~ 3, 4, EIPC);
1465           store_mem ( SP      & ~ 3, 4, EIPSW);
1466         }
1467     }
1468
1469   trace_output (OP_PUSHPOP2);
1470 }
1471
1472
1473
1474 // PUSHHML
1475 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1476 *v850eq
1477 "pushhml <list18>"
1478 {
1479   COMPAT_2 (OP_307E0 ());
1480 }
1481
1482
1483
1484 // POPML
1485 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1486 *v850eq
1487 "popml <list18>"
1488 {
1489   COMPAT_2 (OP_107F0 ());
1490 }
1491
1492
1493
1494 // POPMH
1495 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1496 *v850eq
1497 "popmh <list18>"
1498 {
1499   COMPAT_2 (OP_307F0 ());
1500 }
1501
1502
1503 // end-sanitize-v850eq