sim/v850/v850.igen

   1 :option:::insn-bit-size:16
   2 :option:::hi-bit-nr:15
   3
   4
   5 :option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
   6 # start-sanitize-v850e
   7 :option:::format-names:XI,XII,XIII
   8 :option:::format-names:XIV,XV
   9 # end-sanitize-v850e
  10 :option:::format-names:Z
  11
  12
  13 :model:::v850:v850:
  14
  15 # start-sanitize-v850e
  16 :option:::multi-sim:true
  17 :model:::v850e:v850e:
  18
  19 :option:::multi-sim:true
  20 :model:::v850eq:v850eq:
  21 # end-sanitize-v850e
  22
  23
  24
  25 // Cache macros
  26
  27 :cache:::unsigned:reg1:RRRRR:(RRRRR)
  28 :cache:::unsigned:reg2:rrrrr:(rrrrr)
  29 :cache:::unsigned:reg3:wwwww:(wwwww)
  30
  31 :cache:::unsigned:disp4:dddd:(dddd)
  32 # start-sanitize-v850e
  33 :cache:::unsigned:disp5:dddd:(dddd << 1)
  34 # end-sanitize-v850e
  35 :cache:::unsigned:disp7:ddddddd:ddddddd
  36 :cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
  37 :cache:::unsigned:disp8:dddddd:(dddddd << 2)
  38 :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
  39 :cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
  40 :cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
  41 :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
  42
  43 :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
  44 :cache:::unsigned:imm6:iiiiii:iiiiii
  45 :cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
  46 # start-sanitize-v850e
  47 :cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
  48 # end-sanitize-v850e
  49 :cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
  50 :cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  51 :cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
  52 # start-sanitize-v850e
  53 :cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
  54 # end-sanitize-v850e
  55
  56 :cache:::unsigned:vector:iiiii:iiiii
  57
  58 # start-sanitize-v850e
  59 :cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
  60 :cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
  61 # end-sanitize-v850e
  62
  63 :cache:::unsigned:bit3:bbb:bbb
  64
  65
  66 // What do we do with an illegal instruction?
  67 :internal::::illegal:
  68 {
  69   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  70                   (unsigned long) cia);
  71   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
  72 }
  73
  74
  75
  76 // Add
  77
  78 rrrrr,001110,RRRRR:I:::add
  79 "add r<reg1>, r<reg2>"
  80 {
  81   COMPAT_1 (OP_1C0 ());
  82 }
  83
  84 rrrrr,010010,iiiii:II:::add
  85 "add <imm5>,r<reg2>"
  86 {
  87   COMPAT_1 (OP_240 ());
  88 }
  89
  90
  91
  92 // ADDI
  93 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
  94 "addi <simm16>, r<reg1>, r<reg2>"
  95 {
  96   COMPAT_2 (OP_600 ());
  97 }
  98
  99
 100
 101 // AND
 102 rrrrr,001010,RRRRR:I:::and
 103 "and r<reg1>, r<reg2>"
 104 {
 105   COMPAT_1 (OP_140 ());
 106 }
 107
 108
 109
 110 // ANDI
 111 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
 112 "andi <uimm16>, r<reg1>, r<reg2>"
 113 {
 114   COMPAT_2 (OP_6C0 ());
 115 }
 116
 117
 118
 119 // Map condition code to a string
 120 :%s::::cccc:int cccc
 121 {
 122   switch (cccc)
 123     {
 124     case 0xf: return "gt";
 125     case 0xe: return "ge";
 126     case 0x6: return "lt";
 127
 128     case 0x7: return "le";
 129
 130     case 0xb: return "h";
 131     case 0x9: return "nl";
 132     case 0x1: return "l";
 133
 134     case 0x3: return "nh";
 135
 136     case 0x2: return "e";
 137
 138     case 0xa: return "ne";
 139
 140     case 0x0: return "v";
 141     case 0x8: return "nv";
 142     case 0x4: return "n";
 143     case 0xc: return "p";
 144       /* case 0x1: return "c"; */
 145       /* case 0x9: return "nc"; */
 146       /* case 0x2: return "z"; */
 147       /* case 0xa: return "nz"; */
 148     case 0x5: return "r"; /* always */
 149     case 0xd: return "sa";
 150     }
 151   return "(null)";
 152 }
 153
 154
 155 // Bcond
 156 ddddd,1011,ddd,cccc:III:::Bcond
 157 "b%s<cccc> <disp9>"
 158 {
 159   int cond = condition_met (cccc);
 160   if (cond)
 161     nia = cia + disp9;
 162   TRACE_BRANCH1 (cond);
 163 }
 164
 165
 166
 167 // start-sanitize-v850e
 168 // BSH
 169 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 170 *v850e
 171 *v850eq
 172 "bsh r<reg2>, r<reg3>"
 173 {
 174   unsigned32 value;
 175   TRACE_ALU_INPUT1 (GR[reg2]);
 176
 177   value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
 178            | MOVED32 (GR[reg2], 31, 24, 23, 16)
 179            | MOVED32 (GR[reg2], 7, 0, 15, 8)
 180            | MOVED32 (GR[reg2], 15, 8, 7, 0));
 181
 182   GR[reg3] = value;
 183   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 184   if (value == 0) PSW |= PSW_Z;
 185   if (value & 0x80000000) PSW |= PSW_S;
 186   if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
 187
 188   TRACE_ALU_RESULT (GR[reg3]);
 189 }
 190
 191 // BSW
 192 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 193 *v850e
 194 *v850eq
 195 "bsw r<reg2>, r<reg3>"
 196 {
 197 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
 198   unsigned32 value;
 199   TRACE_ALU_INPUT1 (GR[reg2]);
 200
 201   value = GR[reg2];
 202   value >>= 24;
 203   value |= (GR[reg2] << 24);
 204   value |= ((GR[reg2] << 8) & 0x00ff0000);
 205   value |= ((GR[reg2] >> 8) & 0x0000ff00);
 206   GR[reg3] = value;
 207
 208   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 209
 210   if (value == 0) PSW |= PSW_Z;
 211   if (value & 0x80000000) PSW |= PSW_S;
 212   if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
 213
 214   TRACE_ALU_RESULT (GR[reg3]);
 215 }
 216
 217 // CALLT
 218 0000001000,iiiiii:II:::callt
 219 *v850e
 220 *v850eq
 221 "callt <imm6>"
 222 {
 223   unsigned32 adr;
 224   unsigned32 off;
 225   CTPC  = cia + 2;
 226   CTPSW = PSW;
 227   adr = (CTBP & ~1) + (imm6 << 1);
 228   off = load_mem (adr, 2) & ~1; /* Force alignment */
 229   nia = (CTBP & ~1) + off;
 230   TRACE_BRANCH3 (adr, CTBP, off);
 231 }
 232
 233 // end-sanitize-v850e
 234
 235 // CLR1
 236 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
 237 "clr1 <bit3>, <disp16>[r<reg1>]"
 238 {
 239   COMPAT_2 (OP_87C0 ());
 240 }
 241
 242 // start-sanitize-v850e
 243 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 244 *v850e
 245 *v850eq
 246 "clr1 r<reg2>, [r<reg1>]"
 247 {
 248   COMPAT_2 (OP_E407E0 ());
 249 }
 250
 251
 252 // CTRET
 253 0000011111100000 + 0000000101000100:X:::ctret
 254 *v850e
 255 *v850eq
 256 "ctret"
 257 {
 258   nia  = (CTPC & ~1);
 259   PSW = (CTPSW & (CPU)->psw_mask);
 260   TRACE_BRANCH1 (PSW);
 261 }
 262
 263 // CMOV
 264 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 265 *v850e
 266 *v850eq
 267 "cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
 268 {
 269   int cond = condition_met (cccc);
 270   TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
 271   GR[reg3] = cond ? GR[reg1] : GR[reg2];
 272   TRACE_ALU_RESULT (GR[reg3]);
 273 }
 274
 275 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 276 *v850e
 277 *v850eq
 278 "cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
 279 {
 280   int cond = condition_met (cccc);
 281   TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
 282   GR[reg3] = cond ? imm5 : GR[reg2];
 283   TRACE_ALU_RESULT (GR[reg3]);
 284 }
 285
 286 // end-sanitize-v850e
 287
 288
 289 // CMP
 290 rrrrr,001111,RRRRR:I:::cmp
 291 "cmp r<reg1>, r<reg2>"
 292 {
 293   COMPAT_1 (OP_1E0 ());
 294 }
 295
 296 rrrrr,010011,iiiii:II:::cmp
 297 "cmp <imm5>, r<reg2>"
 298 {
 299   COMPAT_1 (OP_260 ());
 300 }
 301
 302
 303
 304 // DI
 305 0000011111100000 + 0000000101100000:X:::di
 306 "di"
 307 {
 308   COMPAT_2 (OP_16007E0 ());
 309 }
 310
 311
 312
 313 // start-sanitize-v850e
 314 // DISPOSE
 315 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
 316 // "dispose <imm5>, <list12>"
 317 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
 318 *v850e
 319 *v850eq
 320 "dispose <imm5>, <list12>":RRRRR == 0
 321 "dispose <imm5>, <list12>, [reg1]"
 322 {
 323   int i;
 324   SAVE_2;
 325
 326   trace_input ("dispose", OP_PUSHPOP1, 0);
 327
 328   SP += (OP[3] & 0x3e) << 1;
 329
 330   /* Load the registers with lower number registers being retrieved
 331      from higher addresses.  */
 332   for (i = 12; i--;)
 333     if ((OP[3] & (1 << type1_regs[ i ])))
 334       {
 335         State.regs[ 20 + i ] = load_mem (SP, 4);
 336         SP += 4;
 337       }
 338
 339   if ((OP[3] & 0x1f0000) != 0)
 340     {
 341       nia = State.regs[ (OP[3] >> 16) & 0x1f];
 342     }
 343
 344   trace_output (OP_PUSHPOP1);
 345 }
 346
 347
 348 // DIV
 349 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 350 *v850e
 351 "div r<reg1>, r<reg2>, r<reg3>"
 352 {
 353   COMPAT_2 (OP_2C007E0 ());
 354 }
 355
 356
 357 // end-sanitize-v850e
 358
 359 // DIVH
 360 rrrrr!0,000010,RRRRR:I:::divh
 361 "divh r<reg1>, r<reg2>"
 362 {
 363   COMPAT_1 (OP_40 ());
 364 }
 365
 366 // start-sanitize-v850e
 367 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 368 *v850e
 369 "divh r<reg1>, r<reg2>, r<reg3>"
 370 {
 371   COMPAT_2 (OP_28007E0 ());
 372 }
 373
 374
 375 // DIVHU
 376 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 377 *v850e
 378 "divhu r<reg1>, r<reg2>, r<reg3>"
 379 {
 380   COMPAT_2 (OP_28207E0 ());
 381 }
 382
 383
 384 // DIVU
 385 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 386 *v850e
 387 "divu r<reg1>, r<reg2>, r<reg3>"
 388 {
 389   COMPAT_2 (OP_2C207E0 ());
 390 }
 391
 392 // end-sanitize-v850e
 393
 394
 395 // EI
 396 1000011111100000 + 0000000101100000:X:::ei
 397 "ei"
 398 {
 399   COMPAT_2 (OP_16087E0 ());
 400 }
 401
 402
 403
 404 // HALT
 405 0000011111100000 + 0000000100100000:X:::halt
 406 "halt"
 407 {
 408   COMPAT_2 (OP_12007E0 ());
 409 }
 410
 411
 412
 413 // start-sanitize-v850e
 414 // HSW
 415 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 416 *v850e
 417 *v850eq
 418 "hsw r<reg2>, r<reg3>"
 419 {
 420   unsigned32 value;
 421   TRACE_ALU_INPUT1 (GR[reg2]);
 422
 423   value = GR[reg2];
 424   value >>= 16;
 425   value |= (GR[reg2] << 16);
 426
 427   GR[reg3] = value;
 428
 429   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 430
 431   if (value == 0) PSW |= PSW_Z;
 432   if (value & 0x80000000) PSW |= PSW_S;
 433   if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
 434
 435   TRACE_ALU_RESULT (GR[reg3]);
 436 }
 437
 438
 439
 440 // end-sanitize-v850e
 441 // JARL
 442 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 443 "jarl <disp22>, r<reg2>"
 444 {
 445   GR[reg2] = nia;
 446   nia = cia + disp22;
 447   TRACE_BRANCH1 (GR[reg2]);
 448 }
 449
 450
 451
 452 // JMP
 453 00000000011,RRRRR:I:::jmp
 454 "jmp [r<reg1>]"
 455 {
 456   nia = GR[reg1] & ~1;
 457   TRACE_BRANCH0 ();
 458 }
 459
 460
 461
 462 // JR
 463 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 464 "jr <disp22>"
 465 {
 466   nia = cia + disp22;
 467   TRACE_BRANCH0 ();
 468 }
 469
 470
 471
 472 // LD
 473 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 474 "ld.b <disp16>[r<reg1>], r<reg2>"
 475 {
 476   COMPAT_2 (OP_700 ());
 477 }
 478
 479 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 480 "ld.h <disp16>[r<reg1>], r<reg2>"
 481 {
 482   COMPAT_2 (OP_720 ());
 483 }
 484
 485 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 486 "ld.w <disp16>[r<reg1>], r<reg2>"
 487 {
 488   COMPAT_2 (OP_10720 ());
 489 }
 490
 491 // start-sanitize-v850e
 492 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 493 *v850e
 494 *v850eq
 495 "ld.bu <disp16>[r<reg1>], r<reg2>"
 496 {
 497   COMPAT_2 (OP_10780 ());
 498 }
 499
 500 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 501 *v850e
 502 *v850eq
 503 "ld.hu <disp16>[r<reg1>], r<reg2>"
 504 {
 505   COMPAT_2 (OP_107E0 ());
 506 }
 507
 508
 509 // end-sanitize-v850e
 510 // LDSR
 511 regID,111111,RRRRR + 0000000000100000:IX:::ldsr
 512 "ldsr r<reg1>, s<regID>"
 513 {
 514   TRACE_ALU_INPUT1 (GR[reg1]);
 515
 516   if (&PSW == &SR[regID])
 517     PSW = (GR[reg1] & (CPU)->psw_mask);
 518   else
 519     SR[regID] = GR[reg1];
 520
 521   TRACE_ALU_RESULT (SR[regID]);
 522 }
 523
 524
 525
 526 // MOV
 527 rrrrr!0,000000,RRRRR:I:::mov
 528 "mov r<reg1>, r<reg2>"
 529 {
 530   TRACE_ALU_INPUT0 ();
 531   GR[reg2] = GR[reg1];
 532   TRACE_ALU_RESULT (GR[reg2]);
 533 }
 534
 535
 536 rrrrr!0,010000,iiiii:II:::mov
 537 "mov <imm5>, r<reg2>"
 538 {
 539   COMPAT_1 (OP_200 ());
 540 }
 541
 542 // start-sanitize-v850e
 543 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
 544 *v850e
 545 *v850eq
 546 "mov <imm32>, r<reg1>"
 547 {
 548   SAVE_2;
 549   trace_input ("mov", OP_IMM_REG, 4);
 550   State.regs[ OP[0] ] = load_mem (PC + 2, 4);
 551   trace_output (OP_IMM_REG);
 552 }
 553
 554
 555
 556 // end-sanitize-v850e
 557 // MOVEA
 558 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
 559 "movea <simm16>, r<reg1>, r<reg2>"
 560 {
 561   TRACE_ALU_INPUT2 (GR[reg1], simm16);
 562   GR[reg2] = GR[reg1] + simm16;
 563   TRACE_ALU_RESULT (GR[reg2]);
 564 }
 565
 566
 567
 568 // MOVHI
 569 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
 570 "movhi <uimm16>, r<reg1>, r<reg2>"
 571 {
 572   COMPAT_2 (OP_640 ());
 573 }
 574
 575
 576
 577 // start-sanitize-v850e
 578 // MUL
 579 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 580 *v850e
 581 *v850eq
 582 "mul r<reg1>, r<reg2>, r<reg3>"
 583 {
 584   COMPAT_2 (OP_22007E0 ());
 585 }
 586
 587 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 588 *v850e
 589 *v850eq
 590 "mul <imm9>, r<reg2>, r<reg3>"
 591 {
 592   COMPAT_2 (OP_24007E0 ());
 593 }
 594
 595 // end-sanitize-v850e
 596
 597
 598 // MULH
 599 rrrrr!0,000111,RRRRR:I:::mulh
 600 "mulh r<reg1>, r<reg2>"
 601 {
 602   COMPAT_1 (OP_E0 ());
 603 }
 604
 605 rrrrr!0,010111,iiiii:II:::mulh
 606 "mulh <imm5>, r<reg2>"
 607 {
 608   COMPAT_1 (OP_2E0 ());
 609 }
 610
 611
 612
 613 // MULHI
 614 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
 615 "mulhi <uimm16>, r<reg1>, r<reg2>"
 616 {
 617   COMPAT_2 (OP_6E0 ());
 618 }
 619
 620
 621
 622 // start-sanitize-v850e
 623 // MULU
 624 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 625 *v850e
 626 *v850eq
 627 "mulu r<reg1>, r<reg2>, r<reg3>"
 628 {
 629   COMPAT_2 (OP_22207E0 ());
 630 }
 631
 632 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 633 *v850e
 634 *v850eq
 635 "mulu <imm9>, r<reg2>, r<reg3>"
 636 {
 637   COMPAT_2 (OP_24207E0 ());
 638 }
 639
 640
 641
 642 // end-sanitize-v850e
 643 // NOP
 644 0000000000000000:I:::nop
 645 "nop"
 646 {
 647   /* do nothing, trace nothing */
 648 }
 649
 650
 651
 652 // NOT
 653 rrrrr,000001,RRRRR:I:::not
 654 "not r<reg1>, r<reg2>"
 655 {
 656   COMPAT_1 (OP_20 ());
 657 }
 658
 659
 660
 661 // NOT1
 662 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
 663 "not1 <bit3>, <disp16>[r<reg1>]"
 664 {
 665   COMPAT_2 (OP_47C0 ());
 666 }
 667
 668 // start-sanitize-v850e
 669 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 670 *v850e
 671 *v850eq
 672 "not1 r<reg2>, r<reg1>"
 673 {
 674   COMPAT_2 (OP_E207E0 ());
 675 }
 676
 677
 678
 679 // end-sanitize-v850e
 680 // OR
 681 rrrrr,001000,RRRRR:I:::or
 682 "or r<reg1>, r<reg2>"
 683 {
 684   COMPAT_1 (OP_100 ());
 685 }
 686
 687
 688
 689 // ORI
 690 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 691 "ori <uimm16>, r<reg1>, r<reg2>"
 692 {
 693   COMPAT_2 (OP_680 ());
 694 }
 695
 696
 697
 698 // start-sanitize-v850e
 699 // PREPARE
 700 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
 701 *v850e
 702 *v850eq
 703 "prepare <list12>, <imm5>"
 704 {
 705   int  i;
 706   SAVE_2;
 707
 708   trace_input ("prepare", OP_PUSHPOP1, 0);
 709
 710   /* Store the registers with lower number registers being placed at
 711      higher addresses.  */
 712   for (i = 0; i < 12; i++)
 713     if ((OP[3] & (1 << type1_regs[ i ])))
 714       {
 715         SP -= 4;
 716         store_mem (SP, 4, State.regs[ 20 + i ]);
 717       }
 718
 719   SP -= (OP[3] & 0x3e) << 1;
 720
 721   trace_output (OP_PUSHPOP1);
 722 }
 723
 724
 725 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
 726 *v850e
 727 *v850eq
 728 "prepare <list12>, <imm5>, sp"
 729 {
 730   COMPAT_2 (OP_30780 ());
 731 }
 732
 733 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
 734 *v850e
 735 *v850eq
 736 "prepare <list12>, <imm5>, <uimm16>"
 737 {
 738   COMPAT_2 (OP_B0780 ());
 739 }
 740
 741 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
 742 *v850e
 743 *v850eq
 744 "prepare <list12>, <imm5>, <uimm16>"
 745 {
 746   COMPAT_2 (OP_130780 ());
 747 }
 748
 749 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
 750 *v850e
 751 *v850eq
 752 "prepare <list12>, <imm5>, <uimm32>"
 753 {
 754   COMPAT_2 (OP_1B0780 ());
 755 }
 756
 757
 758
 759 // end-sanitize-v850e
 760 // RETI
 761 0000011111100000 + 0000000101000000:X:::reti
 762 "reti"
 763 {
 764   if ((PSW & PSW_EP))
 765     {
 766       nia = (EIPC & ~1);
 767       PSW = EIPSW;
 768     }
 769   else if ((PSW & PSW_NP))
 770     {
 771       nia = (FEPC & ~1);
 772       PSW = FEPSW;
 773     }
 774   else
 775     {
 776       nia = (EIPC & ~1);
 777       PSW = EIPSW;
 778     }
 779   TRACE_BRANCH1 (PSW);
 780 }
 781
 782
 783
 784 // SAR
 785 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
 786 "sar r<reg1>, r<reg2>"
 787 {
 788   COMPAT_2 (OP_A007E0 ());
 789 }
 790
 791 rrrrr,010101,iiiii:II:::sar
 792 "sar <imm5>, r<reg2>"
 793 {
 794   COMPAT_1 (OP_2A0 ());
 795 }
 796
 797
 798
 799 // start-sanitize-v850e
 800 // SASF
 801 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
 802 *v850e
 803 *v850eq
 804 "sasf %s<cccc>, r<reg2>"
 805 {
 806   COMPAT_2 (OP_20007E0 ());
 807 }
 808
 809
 810
 811
 812 // end-sanitize-v850e
 813 // SATADD
 814 rrrrr!0,000110,RRRRR:I:::satadd
 815 "satadd r<reg1>, r<reg2>"
 816 {
 817   COMPAT_1 (OP_C0 ());
 818 }
 819
 820 rrrrr!0,010001,iiiii:II:::satadd
 821 "satadd <imm5>, r<reg2>"
 822 {
 823   COMPAT_1 (OP_220 ());
 824 }
 825
 826
 827
 828 // SATSUB
 829 rrrrr!0,000101,RRRRR:I:::satsub
 830 "satsub r<reg1>, r<reg2>"
 831 {
 832   COMPAT_1 (OP_A0 ());
 833 }
 834
 835
 836
 837 // SATSUBI
 838 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
 839 "satsubi <simm16>, r<reg1>, r<reg2>"
 840 {
 841   COMPAT_2 (OP_660 ());
 842 }
 843
 844
 845
 846 // SATSUBR
 847 rrrrr!0,000100,RRRRR:I:::satsubr
 848 "satsubr r<reg1>, r<reg2>"
 849 {
 850   COMPAT_1 (OP_80 ());
 851 }
 852
 853
 854
 855 // SETF
 856 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
 857 "setf %s<cccc>, r<reg2>"
 858 {
 859   COMPAT_2 (OP_7E0 ());
 860 }
 861
 862
 863
 864 // SET1
 865 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
 866 "set1 <bit3>, <disp16>[r<reg1>]"
 867 {
 868   COMPAT_2 (OP_7C0 ());
 869 }
 870
 871 // start-sanitize-v850e
 872 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
 873 *v850e
 874 *v850eq
 875 "set1 r<reg2>, [r<reg1>]"
 876 {
 877   COMPAT_2 (OP_E007E0 ());
 878 }
 879
 880
 881
 882 // end-sanitize-v850e
 883 // SHL
 884 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
 885 "shl r<reg1>, r<reg2>"
 886 {
 887   COMPAT_2 (OP_C007E0 ());
 888 }
 889
 890 rrrrr,010110,iiiii:II:::shl
 891 "shl <imm5>, r<reg2>"
 892 {
 893   COMPAT_1 (OP_2C0 ());
 894 }
 895
 896
 897
 898 // SHR
 899 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
 900 "shr r<reg1>, r<reg2>"
 901 {
 902   COMPAT_2 (OP_8007E0 ());
 903 }
 904
 905 rrrrr,010100,iiiii:II:::shr
 906 "shr <imm5>, r<reg2>"
 907 {
 908   COMPAT_1 (OP_280 ());
 909 }
 910
 911
 912
 913 // SLD
 914 rrrrr,0110,ddddddd:IV:::sld.b
 915 "sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
 916 "sld.b <disp7>[ep], r<reg2>"
 917 {
 918   unsigned32 addr = EP + disp7;
 919   unsigned32 result = load_mem (addr, 1);
 920   if (PSW & PSW_US)
 921     {
 922       GR[reg2] = result;
 923       TRACE_LD_NAME ("sld.bu", addr, result);
 924     }
 925   else
 926     {
 927       result = EXTEND8 (result);
 928       GR[reg2] = result;
 929       TRACE_LD (addr, result);
 930     }
 931 }
 932
 933 rrrrr,1000,ddddddd:IV:::sld.h
 934 "sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
 935 "sld.h <disp8>[ep], r<reg2>"
 936 {
 937   unsigned32 addr = EP + disp8;
 938   unsigned32 result = load_mem (addr, 2);
 939   if (PSW & PSW_US)
 940     {
 941       GR[reg2] = result;
 942       TRACE_LD_NAME ("sld.hu", addr, result);
 943     }
 944   else
 945     {
 946       result = EXTEND16 (result);
 947       GR[reg2] = result;
 948       TRACE_LD (addr, result);
 949     }
 950 }
 951
 952 rrrrr,1010,dddddd,0:IV:::sld.w
 953 "sld.w <disp8>[ep], r<reg2>"
 954 {
 955   unsigned32 addr = EP + disp8;
 956   unsigned32 result = load_mem (addr, 4);
 957   GR[reg2] = result;
 958   TRACE_LD (addr, result);
 959 }
 960
 961 // start-sanitize-v850e
 962 rrrrr!0,0000110,dddd:IV:::sld.bu
 963 *v850e
 964 *v850eq
 965 "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
 966 "sld.bu <disp4>[ep], r<reg2>"
 967 {
 968   unsigned32 addr = EP + disp4;
 969   unsigned32 result = load_mem (addr, 1);
 970   if (PSW & PSW_US)
 971     {
 972       result = EXTEND8 (result);
 973       GR[reg2] = result;
 974       TRACE_LD_NAME ("sld.b", addr, result);
 975     }
 976   else
 977     {
 978       GR[reg2] = result;
 979       TRACE_LD (addr, result);
 980     }
 981 }
 982
 983 rrrrr!0,0000111,dddd:IV:::sld.hu
 984 *v850e
 985 *v850eq
 986 "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
 987 "sld.hu <disp5>[ep], r<reg2>"
 988 {
 989   unsigned32 addr = EP + disp5;
 990   unsigned32 result = load_mem (addr, 2);
 991   if (PSW & PSW_US)
 992     {
 993       result = EXTEND16 (result);
 994       GR[reg2] = result;
 995       TRACE_LD_NAME ("sld.h", addr, result);
 996     }
 997   else
 998     {
 999       GR[reg2] = result;
1000       TRACE_LD (addr, result);
1001     }
1002 }
1003
1004 // end-sanitize-v850e
1005
1006
1007 // SST
1008 rrrrr,0111,ddddddd:IV:::sst.b
1009 "sst.b r<reg2>, <disp7>[ep]"
1010 {
1011   COMPAT_1 (OP_380 ());
1012 }
1013
1014 rrrrr,1001,ddddddd:IV:::sst.h
1015 "sst.h r<reg2>, <disp8>[ep]"
1016 {
1017   COMPAT_1 (OP_480 ());
1018 }
1019
1020 rrrrr,1010,dddddd,1:IV:::sst.w
1021 "sst.w r<reg2>, <disp8>[ep]"
1022 {
1023   COMPAT_1 (OP_501 ());
1024 }
1025
1026
1027
1028 // ST
1029 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
1030 "st.b r<reg2>, <disp16>[r<reg1>]"
1031 {
1032   COMPAT_2 (OP_740 ());
1033 }
1034
1035 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
1036 "st.h r<reg2>, <disp16>[r<reg1>]"
1037 {
1038   COMPAT_2 (OP_760 ());
1039 }
1040
1041 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1042 "st.w r<reg2>, <disp16>[r<reg1>]"
1043 {
1044   COMPAT_2 (OP_10760 ());
1045 }
1046
1047
1048
1049 // STSR
1050 rrrrr,111111,regID + 0000000001000000:IX:::stsr
1051 "stsr s<regID>, r<reg2>"
1052 {
1053   TRACE_ALU_INPUT1 (SR[regID]);
1054   GR[reg2] = SR[regID];
1055   TRACE_ALU_RESULT (GR[reg2]);
1056 }
1057
1058
1059
1060 // SUB
1061 rrrrr,001101,RRRRR:I:::sub
1062 "sub r<reg1>, r<reg2>"
1063 {
1064   COMPAT_1 (OP_1A0 ());
1065 }
1066
1067
1068
1069 // SUBR
1070 rrrrr,001100,RRRRR:I:::subr
1071 "subr r<reg1>, r<reg2>"
1072 {
1073   COMPAT_1 (OP_180 ());
1074 }
1075
1076
1077
1078 // start-sanitize-v850e
1079 // SWITCH
1080 00000000010,RRRRR:I:::switch
1081 *v850e
1082 *v850eq
1083 "switch r<reg1>"
1084 {
1085   unsigned long adr;
1086   SAVE_1;
1087   trace_input ("switch", OP_REG, 0);
1088   adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1089   nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1090   trace_output (OP_REG);
1091 }
1092
1093
1094 // SXB
1095 00000000101,RRRRR:I:::sxb
1096 *v850e
1097 *v850eq
1098 "sxb r<reg1>"
1099 {
1100   TRACE_ALU_INPUT1 (GR[reg1]);
1101   GR[reg1] = EXTEND8 (GR[reg1]);
1102   TRACE_ALU_RESULT (GR[reg1]);
1103 }
1104
1105 // SXH
1106 00000000111,RRRRR:I:::sxh
1107 *v850e
1108 *v850eq
1109 "sxh r<reg1>"
1110 {
1111   TRACE_ALU_INPUT1 (GR[reg1]);
1112   GR[reg1] = EXTEND16 (GR[reg1]);
1113   TRACE_ALU_RESULT (GR[reg1]);
1114 }
1115
1116
1117
1118 // end-sanitize-v850e
1119 // TRAP
1120 00000111111,iiiii + 0000000100000000:X:::trap
1121 "trap <vector>"
1122 {
1123   COMPAT_2 (OP_10007E0 ());
1124 }
1125
1126
1127
1128 // TST
1129 rrrrr,001011,RRRRR:I:::tst
1130 "tst r<reg1>, r<reg2>"
1131 {
1132   COMPAT_1 (OP_160 ());
1133 }
1134
1135
1136
1137 // TST1
1138 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1139 "tst1 <bit3>, <disp16>[r<reg1>]"
1140 {
1141   COMPAT_2 (OP_C7C0 ());
1142 }
1143
1144 // start-sanitize-v850e
1145 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1146 *v850e
1147 *v850eq
1148 "tst1 r<reg2>, [r<reg1>]"
1149 {
1150   COMPAT_2 (OP_E607E0 ());
1151 }
1152
1153
1154
1155 // end-sanitize-v850e
1156 // XOR
1157 rrrrr,001001,RRRRR:I:::xor
1158 "xor r<reg1>, r<reg2>"
1159 {
1160   COMPAT_1 (OP_120 ());
1161 }
1162
1163
1164
1165 // XORI
1166 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1167 "xori <uimm16>, r<reg1>, r<reg2>"
1168 {
1169   COMPAT_2 (OP_6A0 ());
1170 }
1171
1172
1173
1174 // start-sanitize-v850e
1175 // ZXB
1176 00000000100,RRRRR:I:::zxb
1177 *v850e
1178 *v850eq
1179 "zxb r<reg1>"
1180 {
1181   TRACE_ALU_INPUT1 (GR[reg1]);
1182   GR[reg1] = GR[reg1] & 0xff;
1183   TRACE_ALU_RESULT (GR[reg1]);
1184 }
1185
1186 // ZXH
1187 00000000110,RRRRR:I:::zxh
1188 *v850e
1189 *v850eq
1190 "zxh r<reg1>"
1191 {
1192   TRACE_ALU_INPUT1 (GR[reg1]);
1193   GR[reg1] = GR[reg1] & 0xffff;
1194   TRACE_ALU_RESULT (GR[reg1]);
1195 }
1196
1197 // end-sanitize-v850e
1198
1199
1200 // First field must be zero
1201 11111,000010,00000:I:::break
1202 {
1203   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1204 }
1205
1206
1207
1208 // start-sanitize-v850e
1209 // DIVHN
1210 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1211 *v850eq
1212 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1213 {
1214   signed32 quotient;
1215   signed32 remainder;
1216   signed32 divide_by;
1217   signed32 divide_this;
1218   boolean overflow = false;
1219   SAVE_2;
1220
1221   trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1222
1223   divide_by   = EXTEND16 (State.regs[ reg1 ]);
1224   divide_this = State.regs[ reg2 ];
1225
1226   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1227
1228   State.regs[ reg2 ] = quotient;
1229   State.regs[ reg3 ] = remainder;
1230
1231   /* Set condition codes.  */
1232   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1233
1234   if (overflow)      PSW |= PSW_OV;
1235   if (quotient == 0) PSW |= PSW_Z;
1236   if (quotient <  0) PSW |= PSW_S;
1237
1238   trace_output (OP_IMM_REG_REG_REG);
1239 }
1240
1241
1242
1243 // DIVHUN
1244 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1245 *v850eq
1246 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1247 {
1248   signed32 quotient;
1249   signed32 remainder;
1250   signed32 divide_by;
1251   signed32 divide_this;
1252   boolean overflow = false;
1253   SAVE_2;
1254
1255   trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1256
1257   divide_by   = State.regs[ reg1 ] & 0xffff;
1258   divide_this = State.regs[ reg2 ];
1259
1260   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1261
1262   State.regs[ reg2 ] = quotient;
1263   State.regs[ reg3 ] = remainder;
1264
1265   /* Set condition codes.  */
1266   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1267
1268   if (overflow)      PSW |= PSW_OV;
1269   if (quotient == 0) PSW |= PSW_Z;
1270   if (quotient & 0x80000000) PSW |= PSW_S;
1271
1272   trace_output (OP_IMM_REG_REG_REG);
1273 }
1274
1275
1276
1277 // DIVN
1278 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1279 *v850eq
1280 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1281 {
1282   signed32 quotient;
1283   signed32 remainder;
1284   signed32 divide_by;
1285   signed32 divide_this;
1286   boolean overflow = false;
1287   SAVE_2;
1288
1289   trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1290
1291   divide_by   = State.regs[ reg1 ];
1292   divide_this = State.regs[ reg2 ];
1293
1294   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1295
1296   State.regs[ reg2 ] = quotient;
1297   State.regs[ reg3 ] = remainder;
1298
1299   /* Set condition codes.  */
1300   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1301
1302   if (overflow)      PSW |= PSW_OV;
1303   if (quotient == 0) PSW |= PSW_Z;
1304   if (quotient <  0) PSW |= PSW_S;
1305
1306   trace_output (OP_IMM_REG_REG_REG);
1307 }
1308
1309
1310
1311 // DIVUN
1312 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1313 *v850eq
1314 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1315 {
1316   signed32 quotient;
1317   signed32 remainder;
1318   signed32 divide_by;
1319   signed32 divide_this;
1320   boolean overflow = false;
1321   SAVE_2;
1322
1323   trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1324
1325   divide_by   = State.regs[ reg1 ];
1326   divide_this = State.regs[ reg2 ];
1327
1328   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1329
1330   State.regs[ reg2 ] = quotient;
1331   State.regs[ reg3 ] = remainder;
1332
1333   /* Set condition codes.  */
1334   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1335
1336   if (overflow)      PSW |= PSW_OV;
1337   if (quotient == 0) PSW |= PSW_Z;
1338   if (quotient & 0x80000000) PSW |= PSW_S;
1339
1340   trace_output (OP_IMM_REG_REG_REG);
1341 }
1342
1343
1344
1345 // SDIVHN
1346 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1347 *v850eq
1348 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1349 {
1350   COMPAT_2 (OP_18007E0 ());
1351 }
1352
1353
1354
1355 // SDIVHUN
1356 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1357 *v850eq
1358 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1359 {
1360   COMPAT_2 (OP_18207E0 ());
1361 }
1362
1363
1364
1365 // SDIVN
1366 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1367 *v850eq
1368 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1369 {
1370   COMPAT_2 (OP_1C007E0 ());
1371 }
1372
1373
1374
1375 // SDIVUN
1376 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1377 *v850eq
1378 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1379 {
1380   COMPAT_2 (OP_1C207E0 ());
1381 }
1382
1383
1384
1385 // PUSHML
1386 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1387 *v850eq
1388 "pushml <list18>"
1389 {
1390   int i;
1391   SAVE_2;
1392
1393   trace_input ("pushml", OP_PUSHPOP3, 0);
1394
1395   /* Store the registers with lower number registers being placed at
1396      higher addresses.  */
1397
1398   for (i = 0; i < 15; i++)
1399     if ((OP[3] & (1 << type3_regs[ i ])))
1400       {
1401         SP -= 4;
1402         store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1403       }
1404
1405   if (OP[3] & (1 << 3))
1406     {
1407       SP -= 4;
1408
1409       store_mem (SP & ~ 3, 4, PSW);
1410     }
1411
1412   if (OP[3] & (1 << 19))
1413     {
1414       SP -= 8;
1415
1416       if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1417         {
1418           store_mem ((SP + 4) & ~ 3, 4, FEPC);
1419           store_mem ( SP      & ~ 3, 4, FEPSW);
1420         }
1421       else
1422         {
1423           store_mem ((SP + 4) & ~ 3, 4, EIPC);
1424           store_mem ( SP      & ~ 3, 4, EIPSW);
1425         }
1426     }
1427
1428   trace_output (OP_PUSHPOP2);
1429 }
1430
1431
1432
1433 // PUSHHML
1434 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1435 *v850eq
1436 "pushhml <list18>"
1437 {
1438   COMPAT_2 (OP_307E0 ());
1439 }
1440
1441
1442
1443 // POPML
1444 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1445 *v850eq
1446 "popml <list18>"
1447 {
1448   COMPAT_2 (OP_107F0 ());
1449 }
1450
1451
1452
1453 // POPMH
1454 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1455 *v850eq
1456 "popmh <list18>"
1457 {
1458   COMPAT_2 (OP_307F0 ());
1459 }
1460
1461 // end-sanitize-v850e