sim/v850/v850.igen

   1 :option::insn-bit-size:16
   2 :option::hi-bit-nr:15
   3
   4
   5 :option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
   6 # start-sanitize-v850e
   7 :option::format-names:XI,XII,XIII
   8 # end-sanitize-v850e
   9 # start-sanitize-v850eq
  10 :option::format-names:XIV,XV
  11 # end-sanitize-v850eq
  12 :option::format-names:Z
  13
  14
  15 :model::v850:v850:
  16
  17 # start-sanitize-v850e
  18 :option::multi-sim:true
  19 :model::v850e:v850e:
  20 # end-sanitize-v850e
  21
  22 # start-sanitize-v850eq
  23 :option::multi-sim:true
  24 :model::v850eq:v850eq:
  25 # end-sanitize-v850eq
  26
  27
  28
  29 // Cache macros
  30
  31 :cache::unsigned:reg1:RRRRR:(RRRRR)
  32 :cache::unsigned:reg2:rrrrr:(rrrrr)
  33 :cache::unsigned:reg3:wwwww:(wwwww)
  34 :cache::unsigned:regID:rrrrr:(rrrrr)
  35
  36 :cache::unsigned:disp4:dddd:(dddd)
  37 # start-sanitize-v850e
  38 :cache::unsigned:disp5:dddd:(dddd << 1)
  39 # end-sanitize-v850e
  40 :cache::unsigned:disp7:ddddddd:ddddddd
  41 :cache::unsigned:disp8:ddddddd:(ddddddd << 1)
  42 :cache::unsigned:disp8:dddddd:(dddddd << 2)
  43 :cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
  44 :cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
  45 :cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
  46 :cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
  47 :cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
  48
  49 :cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
  50 :cache::unsigned:imm6:iiiiii:iiiiii
  51 :cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
  52 # start-sanitize-v850eq
  53 :cache::unsigned:imm5:iiii:(32 - (iiii << 1))
  54 # end-sanitize-v850eq
  55 :cache::unsigned:imm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  56 :cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
  57 # start-sanitize-v850e
  58 :cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  59 :cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
  60 # end-sanitize-v850e
  61
  62 :cache::unsigned:vector:iiiii:iiiii
  63
  64 # start-sanitize-v850e
  65 :cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
  66 :cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
  67 # end-sanitize-v850e
  68
  69 :cache::unsigned:bit3:bbb:bbb
  70
  71
  72 // What do we do with an illegal instruction?
  73 :internal:::illegal
  74 {
  75   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  76                   (unsigned long) cia);
  77   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  78 }
  79
  80
  81
  82 // Add
  83
  84 rrrrr,001110,RRRRR:I:::add
  85 "add r<reg1>, r<reg2>"
  86 {
  87   COMPAT_1 (OP_1C0 ());
  88 }
  89
  90 rrrrr,010010,iiiii:II:::add
  91 "add <imm5>,r<reg2>"
  92 {
  93   COMPAT_1 (OP_240 ());
  94 }
  95
  96
  97
  98 // ADDI
  99 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
 100 "addi <imm16>, r<reg1>, r<reg2>"
 101 {
 102   COMPAT_2 (OP_600 ());
 103 }
 104
 105
 106
 107 // AND
 108 rrrrr,001010,RRRRR:I:::and
 109 "and r<reg1>, r<reg2>"
 110 {
 111   COMPAT_1 (OP_140 ());
 112 }
 113
 114
 115
 116 // ANDI
 117 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
 118 "andi <imm16>, r<reg1>, r<reg2>"
 119 {
 120   COMPAT_2 (OP_6C0 ());
 121 }
 122
 123
 124
 125 // Bcond
 126 // ddddd,1011,ddd,cccc:III:::Bcond
 127 // "b<cond> disp9"
 128
 129 ddddd,1011,ddd,0000:III:::bv
 130 "bv <disp9>"
 131 {
 132   COMPAT_1 (OP_580 ());
 133 }
 134
 135 ddddd,1011,ddd,0001:III:::bl
 136 "bl <disp9>"
 137 {
 138   COMPAT_1 (OP_581 ());
 139 }
 140
 141 ddddd,1011,ddd,0010:III:::be
 142 "be <disp9>"
 143 {
 144   COMPAT_1 (OP_582 ());
 145 }
 146
 147 ddddd,1011,ddd,0011:III:::bnh
 148 "bnh <disp9>"
 149 {
 150   COMPAT_1 (OP_583 ());
 151 }
 152
 153 ddddd,1011,ddd,0100:III:::bn
 154 "bn <disp9>"
 155 {
 156   COMPAT_1 (OP_584 ());
 157 }
 158
 159 ddddd,1011,ddd,0101:III:::br
 160 "br <disp9>"
 161 {
 162   COMPAT_1 (OP_585 ());
 163 }
 164
 165 ddddd,1011,ddd,0110:III:::blt
 166 "blt <disp9>"
 167 {
 168   COMPAT_1 (OP_586 ());
 169 }
 170
 171 ddddd,1011,ddd,0111:III:::ble
 172 "ble <disp9>"
 173 {
 174   COMPAT_1 (OP_587 ());
 175 }
 176
 177 ddddd,1011,ddd,1000:III:::bnv
 178 "bnv <disp9>"
 179 {
 180   COMPAT_1 (OP_588 ());
 181 }
 182
 183 ddddd,1011,ddd,1001:III:::bnl
 184 "bnl <disp9>"
 185 {
 186   COMPAT_1 (OP_589 ());
 187 }
 188
 189 ddddd,1011,ddd,1010:III:::bne
 190 "bne <disp9>"
 191 {
 192   COMPAT_1 (OP_58A ());
 193 }
 194
 195 ddddd,1011,ddd,1011:III:::bh
 196 "bh <disp9>"
 197 {
 198   COMPAT_1 (OP_58B ());
 199 }
 200
 201 ddddd,1011,ddd,1100:III:::bp
 202 "bp <disp9>"
 203 {
 204   COMPAT_1 (OP_58C ());
 205 }
 206
 207 ddddd,1011,ddd,1101:III:::bsa
 208 "bsa <disp9>"
 209 {
 210   COMPAT_1 (OP_58D ());
 211 }
 212
 213 ddddd,1011,ddd,1110:III:::bge
 214 "bge <disp9>"
 215 {
 216   COMPAT_1 (OP_58E ());
 217 }
 218
 219 ddddd,1011,ddd,1111:III:::bgt
 220 "bgt <disp9>"
 221 {
 222   COMPAT_1 (OP_58F ());
 223 }
 224
 225
 226
 227 // start-sanitize-v850e
 228 // BSH
 229 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 230 *v850e
 231 // start-sanitize-v850eq
 232 *v850eq
 233 // end-sanitize-v850eq
 234 "bsh r<reg2>, r<reg3>"
 235 {
 236   COMPAT_2 (OP_34207E0 ());
 237 }
 238
 239
 240
 241 // end-sanitize-v850e
 242 // start-sanitize-v850e
 243 // BSW
 244 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 245 *v850e
 246 // start-sanitize-v850eq
 247 *v850eq
 248 // end-sanitize-v850eq
 249 "bsw r<reg2>, reg3>"
 250 {
 251   COMPAT_2 (OP_34007E0 ());
 252 }
 253
 254
 255
 256 // end-sanitize-v850e
 257 // CALLT
 258 0000001000,iiiiii:II:::callt
 259 "callt <imm6>"
 260 {
 261   COMPAT_1 (OP_200 ());
 262 }
 263
 264
 265
 266 // CLR1
 267 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
 268 "clr1 <bit3>, <disp16>[r<reg1>]"
 269 {
 270   COMPAT_2 (OP_87C0 ());
 271 }
 272
 273 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 274 "clr1 r<reg2>, [r<reg1>]"
 275 {
 276   COMPAT_2 (OP_E407E0 ());
 277 }
 278
 279
 280
 281 // CTRET
 282 0000011111100000 + 0000000101000100:X:::ctret
 283 "ctret"
 284 {
 285   COMPAT_2 (OP_14407E0 ());
 286 }
 287
 288
 289
 290 // start-sanitize-v850e
 291 // CMOV
 292 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 293 *v850e
 294 // start-sanitize-v850eq
 295 *v850eq
 296 // end-sanitize-v850eq
 297 "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
 298 {
 299   COMPAT_2 (OP_32007E0 ());
 300 }
 301
 302 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 303 *v850e
 304 // start-sanitize-v850eq
 305 *v850eq
 306 // end-sanitize-v850eq
 307 "cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
 308 {
 309   COMPAT_2 (OP_30007E0 ());
 310 }
 311
 312
 313
 314 // end-sanitize-v850e
 315 // CMP
 316 rrrrr,001111,RRRRR:I:::cmp
 317 "cmp r<reg1>, r<reg2>"
 318 {
 319   COMPAT_1 (OP_1E0 ());
 320 }
 321
 322 rrrrr,010011,iiiii:II:::cmp
 323 "cmp <imm5>, r<reg2>"
 324 {
 325   COMPAT_1 (OP_260 ());
 326 }
 327
 328
 329
 330 // DI
 331 0000011111100000 + 0000000101100000:X:::di
 332 "di"
 333 {
 334   COMPAT_2 (OP_16007E0 ());
 335 }
 336
 337
 338
 339 // start-sanitize-v850e
 340 // DISPOSE
 341 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
 342 // "dispose <imm5>, <list12>"
 343 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
 344 *v850e
 345 // start-sanitize-v850eq
 346 *v850eq
 347 // end-sanitize-v850eq
 348 "dispose <imm5>, <list12>":RRRRR == 0
 349 "dispose <imm5>, <list12>, [reg1]"
 350 {
 351   COMPAT_2 (OP_640 ());
 352 }
 353
 354
 355
 356 // end-sanitize-v850e
 357 // start-sanitize-v850e
 358 // DIV
 359 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 360 *v850e
 361 "div r<reg1>, r<reg2>, r<reg3>"
 362 {
 363   COMPAT_2 (OP_2C007E0 ());
 364 }
 365
 366
 367
 368
 369 // end-sanitize-v850e
 370 // DIVH
 371 rrrrr!0,000010,RRRRR!0:I:::divh
 372 "divh r<reg1>, r<reg2>"
 373 {
 374   COMPAT_1 (OP_40 ());
 375 }
 376
 377 // start-sanitize-v850e
 378 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 379 *v850e
 380 "divh r<reg1>, r<reg2>, r<reg3>"
 381 {
 382   COMPAT_2 (OP_28007E0 ());
 383 }
 384
 385 // end-sanitize-v850e
 386
 387
 388 // start-sanitize-v850e
 389 // DIVHU
 390 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 391 *v850e
 392 "divhu r<reg1>, r<reg2>, r<reg3>"
 393 {
 394   COMPAT_2 (OP_28207E0 ());
 395 }
 396
 397
 398
 399 // end-sanitize-v850e
 400 // start-sanitize-v850e
 401 // DIVU
 402 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 403 *v850e
 404 "divu r<reg1>, r<reg2>, r<reg3>"
 405 {
 406   COMPAT_2 (OP_2C207E0 ());
 407 }
 408
 409
 410
 411 // end-sanitize-v850e
 412 // EI
 413 1000011111100000 + 0000000101100000:X:::ei
 414 "ei"
 415 {
 416   COMPAT_2 (OP_16087E0 ());
 417 }
 418
 419
 420
 421 // HALT
 422 0000011111100000 + 0000000100100000:X:::halt
 423 "halt"
 424 {
 425   COMPAT_2 (OP_12007E0 ());
 426 }
 427
 428
 429
 430 // HSW
 431 // start-sanitize-v850e
 432 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 433 *v850e
 434 // start-sanitize-v850eq
 435 *v850eq
 436 // end-sanitize-v850eq
 437 "hsw r<reg2>, r<reg3>"
 438 {
 439   COMPAT_2 (OP_34407E0 ());
 440 }
 441
 442
 443
 444 // end-sanitize-v850e
 445 // JARL
 446 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 447 "jarl <disp22>, r<reg2>"
 448 {
 449   COMPAT_2 (OP_780 ());
 450 }
 451
 452
 453
 454 // JMP
 455 00000000011,RRRRR:I:::jmp
 456 "jmp [r<reg1>]"
 457 {
 458   COMPAT_1 (OP_60 ());
 459 }
 460
 461
 462
 463 // JR
 464 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 465 "jr <disp22>"
 466 {
 467   COMPAT_2 (OP_780 ());
 468 }
 469
 470
 471
 472 // LD
 473 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 474 "ld.b <disp16>[r<reg1>, r<reg2>"
 475 {
 476   COMPAT_2 (OP_700 ());
 477 }
 478
 479 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 480 "ld.h <disp16>[r<reg1>], r<reg2>"
 481 {
 482   COMPAT_2 (OP_720 ());
 483 }
 484
 485 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 486 "ld.w <disp16>[r<reg1>], r<reg2>"
 487 {
 488   COMPAT_2 (OP_10720 ());
 489 }
 490
 491 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 492 "ld.bu <disp16>[r<reg1>], r<reg2>"
 493 {
 494   COMPAT_2 (OP_10780 ());
 495 }
 496
 497 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 498 "ld.hu <disp16>[r<reg1>], r<reg2>"
 499 {
 500   COMPAT_2 (OP_107E0 ());
 501 }
 502
 503
 504
 505 // LDSR
 506 //rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 507 //"ldsr r<reg2>, r<regID>"
 508 //{
 509 //  COMPAT_2 (OP_2007E0 ());
 510 //}
 511 rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 512 "ldsr r<reg1>, r<regID>"
 513 {
 514   COMPAT_2 (OP_2007E0 ());
 515 }
 516
 517
 518
 519 // MOV
 520 rrrrr!0,000000,RRRRR:I:::mov
 521 "mov r<reg1>, r<reg2>"
 522 {
 523   COMPAT_1 (OP_0 ());
 524 }
 525
 526 rrrrr!0,010000,iiiii:II:::mov
 527 "mov <imm5>, r<reg2>"
 528 {
 529   COMPAT_1 (OP_200 ());
 530 }
 531
 532 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
 533 "mov <imm32>, r<reg1>"
 534 {
 535   COMPAT_2 (OP_620 ());
 536 }
 537
 538
 539
 540 // MOVEA
 541 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
 542 "movea <imm16>, r<reg1>, r<reg2>"
 543 {
 544   COMPAT_2 (OP_620 ());
 545 }
 546
 547
 548
 549 // MOVHI
 550 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
 551 "movhi <imm16>, r<reg1>, r<reg2>"
 552 {
 553   COMPAT_2 (OP_640 ());
 554 }
 555
 556
 557
 558 // start-sanitize-v850e
 559 // MUL
 560 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 561 *v850e
 562 // start-sanitize-v850eq
 563 *v850eq
 564 // end-sanitize-v850eq
 565 "mul r<reg1>, r<reg2>, r<reg3>"
 566 {
 567   COMPAT_2 (OP_22007E0 ());
 568 }
 569
 570 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 571 *v850e
 572 // start-sanitize-v850eq
 573 *v850eq
 574 // end-sanitize-v850eq
 575 "mul <imm9>, r<reg2>, r<reg3>"
 576 {
 577   COMPAT_2 (OP_24007E0 ());
 578 }
 579
 580
 581
 582 // end-sanitize-v850e
 583 // MULH
 584 rrrrr!0,000111,RRRRR:I:::mulh
 585 "mulh r<reg1>, r<reg2>"
 586 {
 587   COMPAT_1 (OP_E0 ());
 588 }
 589
 590 rrrrr!0,010111,iiiii:II:::mulh
 591 "mulh <imm5>, r<reg2>"
 592 {
 593   COMPAT_1 (OP_2E0 ());
 594 }
 595
 596
 597
 598 // MULHI
 599 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
 600 "mulhi <imm16>, r<reg1>, r<reg2>"
 601 {
 602   COMPAT_2 (OP_6E0 ());
 603 }
 604
 605
 606
 607 // start-sanitize-v850e
 608 // MULU
 609 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 610 *v850e
 611 // start-sanitize-v850eq
 612 *v850eq
 613 // end-sanitize-v850eq
 614 "mulu r<reg1>, r<reg2>, r<reg3>"
 615 {
 616   COMPAT_2 (OP_22207E0 ());
 617 }
 618
 619 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 620 *v850e
 621 // start-sanitize-v850eq
 622 *v850eq
 623 // end-sanitize-v850eq
 624 "mulu <imm9>, r<reg2>, r<reg3>"
 625 {
 626   COMPAT_2 (OP_24207E0 ());
 627 }
 628
 629
 630
 631 // end-sanitize-v850e
 632 // NOP
 633 0000000000000000:I:::nop
 634 "nop"
 635 {
 636   COMPAT_1 (OP_0 ());
 637 }
 638
 639
 640
 641 // NOT
 642 rrrrr,000001,RRRRR:I:::not
 643 "not r<reg1>, r<reg2>"
 644 {
 645   COMPAT_1 (OP_20 ());
 646 }
 647
 648
 649
 650 // NOT1
 651 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
 652 "not1 <bit3>, <disp16>[r<reg1>]"
 653 {
 654   COMPAT_2 (OP_47C0 ());
 655 }
 656
 657 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 658 "not1 r<reg2>, r<reg1>"
 659 {
 660   COMPAT_2 (OP_E207E0 ());
 661 }
 662
 663
 664
 665 // OR
 666 rrrrr,001000,RRRRR:I:::or
 667 "or r<reg1>, r<reg2>"
 668 {
 669   COMPAT_1 (OP_100 ());
 670 }
 671
 672
 673
 674 // ORI
 675 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 676 "ori <imm16>, r<reg1>, r<reg2>"
 677 {
 678   COMPAT_2 (OP_680 ());
 679 }
 680
 681
 682
 683 // start-sanitize-v850e
 684 // PREPARE
 685 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
 686 *v850e
 687 // start-sanitize-v850eq
 688 *v850eq
 689 // end-sanitize-v850eq
 690 "prepare <list12>, <imm5>"
 691 {
 692   COMPAT_2 (OP_10780 ());
 693 }
 694
 695 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
 696 *v850e
 697 // start-sanitize-v850eq
 698 *v850eq
 699 // end-sanitize-v850eq
 700 "prepare <list12>, <imm5>, sp"
 701 {
 702   COMPAT_2 (OP_30780 ());
 703 }
 704
 705 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
 706 *v850e
 707 // start-sanitize-v850eq
 708 *v850eq
 709 // end-sanitize-v850eq
 710 "prepare <list12>, <imm5>, <uimm16>"
 711 {
 712   COMPAT_2 (OP_B0780 ());
 713 }
 714
 715 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
 716 *v850e
 717 // start-sanitize-v850eq
 718 *v850eq
 719 // end-sanitize-v850eq
 720 "prepare <list12>, <imm5>, <uimm16>"
 721 {
 722   COMPAT_2 (OP_130780 ());
 723 }
 724
 725 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
 726 *v850e
 727 // start-sanitize-v850eq
 728 *v850eq
 729 // end-sanitize-v850eq
 730 "prepare <list12>, <imm5>, <uimm32>"
 731 {
 732   COMPAT_2 (OP_1B0780 ());
 733 }
 734
 735
 736
 737 // end-sanitize-v850e
 738 // RETI
 739 0000011111100000 + 0000000101000000:X:::reti
 740 "reti"
 741 {
 742   COMPAT_2 (OP_14007E0 ());
 743 }
 744
 745
 746
 747 // SAR
 748 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
 749 "sar r<reg1>, r<reg2>"
 750 {
 751   COMPAT_2 (OP_A007E0 ());
 752 }
 753
 754 rrrrr,010101,iiiii:II:::sar
 755 "sar <imm5>, r<reg2>"
 756 {
 757   COMPAT_1 (OP_2A0 ());
 758 }
 759
 760
 761
 762 // SASF
 763 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
 764 "sasf <cccc>, r<reg2>"
 765 {
 766   COMPAT_2 (OP_20007E0 ());
 767 }
 768
 769
 770
 771
 772 // SATADD
 773 rrrrr!0,000110,RRRRR:I:::satadd
 774 "satadd r<reg1>, r<reg2>"
 775 {
 776   COMPAT_1 (OP_C0 ());
 777 }
 778
 779 rrrrr!0,010001,iiiii:II:::satadd
 780 "satadd <imm5>, r<reg2>"
 781 {
 782   COMPAT_1 (OP_220 ());
 783 }
 784
 785
 786
 787 // SATSUB
 788 rrrrr!0,000101,RRRRR:I:::satsub
 789 "satsub r<reg1>, r<reg2>"
 790 {
 791   COMPAT_1 (OP_A0 ());
 792 }
 793
 794
 795
 796 // SATSUBI
 797 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
 798 "satsubi <imm16>, r<reg1>, r<reg2>"
 799 {
 800   COMPAT_2 (OP_660 ());
 801 }
 802
 803
 804
 805 // SATSUBR
 806 rrrrr!0,000100,RRRRR:I:::satsubr
 807 "satsubr r<reg1>, r<reg2>"
 808 {
 809   COMPAT_1 (OP_80 ());
 810 }
 811
 812
 813
 814 // SETF
 815 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
 816 "setf <cccc>, r<reg2>"
 817 {
 818   COMPAT_2 (OP_7E0 ());
 819 }
 820
 821
 822
 823 // SET1
 824 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
 825 "set1 <bit3>, <disp16>[r<reg1>]"
 826 {
 827   COMPAT_2 (OP_7C0 ());
 828 }
 829
 830 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
 831 "set1 r<reg2>, [r<reg1>]"
 832 {
 833   COMPAT_2 (OP_E007E0 ());
 834 }
 835
 836
 837
 838 // SHL
 839 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
 840 "shl r<reg1>, r<reg2>"
 841 {
 842   COMPAT_2 (OP_C007E0 ());
 843 }
 844
 845 rrrrr,010110,iiiii:II:::shl
 846 "shl <imm5>, r<reg2>"
 847 {
 848   COMPAT_1 (OP_2C0 ());
 849 }
 850
 851
 852
 853 // SHR
 854 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
 855 "shr r<reg1>, r<reg2>"
 856 {
 857   COMPAT_2 (OP_8007E0 ());
 858 }
 859
 860 rrrrr,010100,iiiii:II:::shr
 861 "shr <imm5>, r<reg2>"
 862 {
 863   COMPAT_1 (OP_280 ());
 864 }
 865
 866
 867
 868 // SLD
 869 rrrrr,0110,ddddddd:IV:::sld.b
 870 "sld.b <disp7>[ep], r<reg2>"
 871 {
 872   COMPAT_1 (OP_300 ());
 873 }
 874
 875 rrrrr,1000,ddddddd:IV:::sld.h
 876 "sld.h <disp8>[ep], r<reg2>"
 877 {
 878   COMPAT_1 (OP_400 ());
 879 }
 880
 881 rrrrr,1010,dddddd,0:IV:::sld.w
 882 "sld.w <disp8>[ep], r<reg2>"
 883 {
 884   COMPAT_1 (OP_500 ());
 885 }
 886
 887 rrrrr!0,0000110,dddd:IV:::sld.bu
 888 "sld.bu <disp4>[ep], r<reg2>"
 889 {
 890   COMPAT_1 (OP_60 ());
 891 }
 892
 893 rrrrr!0,0000111,dddd:IV:::sld.hu
 894 "sld.hu <disp5>[ep], r<reg2>"
 895 {
 896   COMPAT_1 (OP_70 ());
 897 }
 898
 899
 900
 901 // SST
 902 rrrrr,0111,ddddddd:IV:::sst.b
 903 "sst.b r<reg2>, <disp7>[ep]"
 904 {
 905   COMPAT_1 (OP_380 ());
 906 }
 907
 908 rrrrr,1001,ddddddd:IV:::sst.h
 909 "sst.h r<reg2>, <disp8>[ep]"
 910 {
 911   COMPAT_1 (OP_480 ());
 912 }
 913
 914 rrrrr,1010,dddddd,1:IV:::sst.w
 915 "sst.w r<reg2>, <disp8>[ep]"
 916 {
 917   COMPAT_1 (OP_501 ());
 918 }
 919
 920
 921
 922 // ST
 923 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
 924 "st.b r<reg2>, <disp16>[r<reg1>]"
 925 {
 926   COMPAT_2 (OP_740 ());
 927 }
 928
 929 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
 930 "st.h r<reg2>, <disp16>[r<reg1>]"
 931 {
 932   COMPAT_2 (OP_760 ());
 933 }
 934
 935 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 936 "st.w r<reg2>, <disp16>[r<reg1>]"
 937 {
 938   COMPAT_2 (OP_10760 ());
 939 }
 940
 941
 942
 943 // STSR
 944 //rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
 945 //"stsr r<regID>, r<reg2>"
 946 //{
 947 //  COMPAT_2 (OP_4007E0 ());
 948 //}
 949 rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
 950 "stsr r<regID>, r<reg1>"
 951 {
 952   COMPAT_2 (OP_4007E0 ());
 953 }
 954
 955
 956
 957 // SUB
 958 rrrrr,001101,RRRRR:I:::sub
 959 "sub r<reg1>, r<reg2>"
 960 {
 961   COMPAT_1 (OP_1A0 ());
 962 }
 963
 964
 965
 966 // SUBR
 967 rrrrr,001100,RRRRR:I:::subr
 968 "subr r<reg1>, r<reg2>"
 969 {
 970   COMPAT_1 (OP_180 ());
 971 }
 972
 973
 974
 975 // SWITCH
 976 00000000010,RRRRR:I:::switch
 977 "switch r<reg1>"
 978 {
 979   COMPAT_1 (OP_40 ());
 980 }
 981
 982
 983
 984 // SXB
 985 00000000101,RRRRR:I:::sxb
 986 "sxb r<reg1>"
 987 {
 988   COMPAT_1 (OP_A0 ());
 989 }
 990
 991
 992
 993 // SXH
 994 00000000111,RRRRR:I:::sxh
 995 "sxh r<reg1>"
 996 {
 997   COMPAT_1 (OP_E0 ());
 998 }
 999
1000
1001
1002 // TRAP
1003 00000111111,iiiii + 0000000100000000:X:::trap
1004 "trap <vector>"
1005 {
1006   COMPAT_2 (OP_10007E0 ());
1007 }
1008
1009
1010
1011 // TST
1012 rrrrr,001011,RRRRR:I:::tst
1013 "tst r<reg1>, r<reg2>"
1014 {
1015   COMPAT_1 (OP_160 ());
1016 }
1017
1018
1019
1020 // TST1
1021 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1022 "tst1 <bit3>, <disp16>[r<reg1>]"
1023 {
1024   COMPAT_2 (OP_C7C0 ());
1025 }
1026
1027 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1028 "tst1 r<reg2>, [r<reg1>]"
1029 {
1030   COMPAT_2 (OP_E607E0 ());
1031 }
1032
1033
1034
1035 // XOR
1036 rrrrr,001001,RRRRR:I:::xor
1037 "xor r<reg1>, r<reg2>"
1038 {
1039   COMPAT_1 (OP_120 ());
1040 }
1041
1042
1043
1044 // XORI
1045 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1046 "xori <imm16>, r<reg1>, r<reg2>"
1047 {
1048   COMPAT_2 (OP_6A0 ());
1049 }
1050
1051
1052
1053 // ZXB
1054 00000000100,RRRRR:I:::zxb
1055 "zxb r<reg1>"
1056 {
1057   COMPAT_1 (OP_80 ());
1058 }
1059
1060
1061
1062 // ZXH
1063 00000000110,RRRRR:I:::zxh
1064 "zxh r<reg1>"
1065 {
1066   COMPAT_1 (OP_C0 ());
1067 }
1068
1069
1070
1071 // Special - breakpoint
1072 // 1111111111111111:Z:::breakpoint
1073 // {
1074 //   COMPAT_2 (OP_FFFF ());
1075 // }
1076
1077
1078 // start-sanitize-v850eq
1079 // DIVHN
1080 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1081 *v850eq
1082 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1083 {
1084   COMPAT_2 (OP_28007E0 ());
1085 }
1086
1087
1088
1089 // DIVHUN
1090 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1091 *v850eq
1092 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1093 {
1094   COMPAT_2 (OP_28207E0 ());
1095 }
1096
1097
1098
1099 // DIVN
1100 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1101 *v850eq
1102 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1103 {
1104   COMPAT_2 (OP_2C007E0 ());
1105 }
1106
1107
1108
1109 // DIVUN
1110 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1111 *v850eq
1112 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1113 {
1114   COMPAT_2 (OP_2C207E0 ());
1115 }
1116
1117
1118
1119 // SDIVHN
1120 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1121 *v850eq
1122 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1123 {
1124   COMPAT_2 (OP_18007E0 ());
1125 }
1126
1127
1128
1129 // SDIVHUN
1130 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1131 *v850eq
1132 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1133 {
1134   COMPAT_2 (OP_18207E0 ());
1135 }
1136
1137
1138
1139 // SDIVN
1140 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1141 *v850eq
1142 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1143 {
1144   COMPAT_2 (OP_1C007E0 ());
1145 }
1146
1147
1148
1149 // SDIVUN
1150 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1151 *v850eq
1152 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1153 {
1154   COMPAT_2 (OP_1C207E0 ());
1155 }
1156
1157
1158
1159 // PUSHML
1160 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1161 *v850eq
1162 "pushml <list18>"
1163 {
1164   COMPAT_2 (OP_107E0 ());
1165 }
1166
1167
1168
1169 // PUSHHML
1170 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1171 *v850eq
1172 "pushhml <list18>"
1173 {
1174   COMPAT_2 (OP_307E0 ());
1175 }
1176
1177
1178
1179 // POPML
1180 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1181 *v850eq
1182 "popml <list18>"
1183 {
1184   COMPAT_2 (OP_107F0 ());
1185 }
1186
1187
1188
1189 // POPMH
1190 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1191 *v850eq
1192 "popmh <list18>"
1193 {
1194   COMPAT_2 (OP_307F0 ());
1195 }
1196
1197
1198 // end-sanitize-v850eq