sim/v850/v850.igen

   1 :option:::insn-bit-size:16
   2 :option:::hi-bit-nr:15
   3
   4
   5 :option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
   6 :option:::format-names:XI,XII,XIII
   7 :option:::format-names:XIV,XV
   8 :option:::format-names:Z
   9
  10
  11 :model:::v850:v850:
  12
  13 :option:::multi-sim:true
  14 :model:::v850e:v850e:
  15
  16 // Cache macros
  17
  18 :cache:::unsigned:reg1:RRRRR:(RRRRR)
  19 :cache:::unsigned:reg2:rrrrr:(rrrrr)
  20 :cache:::unsigned:reg3:wwwww:(wwwww)
  21
  22 :cache:::unsigned:disp4:dddd:(dddd)
  23 :cache:::unsigned:disp5:dddd:(dddd << 1)
  24 :cache:::unsigned:disp7:ddddddd:ddddddd
  25 :cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
  26 :cache:::unsigned:disp8:dddddd:(dddddd << 2)
  27 :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
  28 :cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
  29 :cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
  30 :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
  31
  32 :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
  33 :cache:::unsigned:imm6:iiiiii:iiiiii
  34 :cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
  35 :cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
  36 :cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
  37 :cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  38 :cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
  39 :cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
  40
  41 :cache:::unsigned:vector:iiiii:iiiii
  42
  43 :cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
  44 :cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
  45
  46 :cache:::unsigned:bit3:bbb:bbb
  47
  48
  49 // What do we do with an illegal instruction?
  50 :internal::::illegal:
  51 {
  52   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  53                   (unsigned long) cia);
  54   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
  55 }
  56
  57
  58
  59 // Add
  60
  61 rrrrr,001110,RRRRR:I:::add
  62 "add r<reg1>, r<reg2>"
  63 {
  64   COMPAT_1 (OP_1C0 ());
  65 }
  66
  67 rrrrr,010010,iiiii:II:::add
  68 "add <imm5>,r<reg2>"
  69 {
  70   COMPAT_1 (OP_240 ());
  71 }
  72
  73
  74
  75 // ADDI
  76 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
  77 "addi <simm16>, r<reg1>, r<reg2>"
  78 {
  79   COMPAT_2 (OP_600 ());
  80 }
  81
  82
  83
  84 // AND
  85 rrrrr,001010,RRRRR:I:::and
  86 "and r<reg1>, r<reg2>"
  87 {
  88   COMPAT_1 (OP_140 ());
  89 }
  90
  91
  92
  93 // ANDI
  94 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
  95 "andi <uimm16>, r<reg1>, r<reg2>"
  96 {
  97   COMPAT_2 (OP_6C0 ());
  98 }
  99
 100
 101
 102 // Map condition code to a string
 103 :%s::::cccc:int cccc
 104 {
 105   switch (cccc)
 106     {
 107     case 0xf: return "gt";
 108     case 0xe: return "ge";
 109     case 0x6: return "lt";
 110
 111     case 0x7: return "le";
 112
 113     case 0xb: return "h";
 114     case 0x9: return "nl";
 115     case 0x1: return "l";
 116
 117     case 0x3: return "nh";
 118
 119     case 0x2: return "e";
 120
 121     case 0xa: return "ne";
 122
 123     case 0x0: return "v";
 124     case 0x8: return "nv";
 125     case 0x4: return "n";
 126     case 0xc: return "p";
 127       /* case 0x1: return "c"; */
 128       /* case 0x9: return "nc"; */
 129       /* case 0x2: return "z"; */
 130       /* case 0xa: return "nz"; */
 131     case 0x5: return "r"; /* always */
 132     case 0xd: return "sa";
 133     }
 134   return "(null)";
 135 }
 136
 137
 138 // Bcond
 139 ddddd,1011,ddd,cccc:III:::Bcond
 140 "b%s<cccc> <disp9>"
 141 {
 142   int cond;
 143   if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
 144     // Special case - treat "br *" like illegal instruction
 145     sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
 146   } else {
 147     cond = condition_met (cccc);
 148     if (cond)
 149       nia = cia + disp9;
 150     TRACE_BRANCH1 (cond);
 151   }
 152 }
 153
 154
 155
 156 // BSH
 157 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 158 *v850e
 159 "bsh r<reg2>, r<reg3>"
 160 {
 161   unsigned32 value;
 162   TRACE_ALU_INPUT1 (GR[reg2]);
 163
 164   value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
 165            | MOVED32 (GR[reg2], 31, 24, 23, 16)
 166            | MOVED32 (GR[reg2], 7, 0, 15, 8)
 167            | MOVED32 (GR[reg2], 15, 8, 7, 0));
 168
 169   GR[reg3] = value;
 170   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 171   if (value == 0) PSW |= PSW_Z;
 172   if (value & 0x80000000) PSW |= PSW_S;
 173   if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
 174
 175   TRACE_ALU_RESULT (GR[reg3]);
 176 }
 177
 178 // BSW
 179 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 180 *v850e
 181 "bsw r<reg2>, r<reg3>"
 182 {
 183 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
 184   unsigned32 value;
 185   TRACE_ALU_INPUT1 (GR[reg2]);
 186
 187   value = GR[reg2];
 188   value >>= 24;
 189   value |= (GR[reg2] << 24);
 190   value |= ((GR[reg2] << 8) & 0x00ff0000);
 191   value |= ((GR[reg2] >> 8) & 0x0000ff00);
 192   GR[reg3] = value;
 193
 194   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 195
 196   if (value == 0) PSW |= PSW_Z;
 197   if (value & 0x80000000) PSW |= PSW_S;
 198   if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
 199
 200   TRACE_ALU_RESULT (GR[reg3]);
 201 }
 202
 203 // CALLT
 204 0000001000,iiiiii:II:::callt
 205 *v850e
 206 "callt <imm6>"
 207 {
 208   unsigned32 adr;
 209   unsigned32 off;
 210   CTPC  = cia + 2;
 211   CTPSW = PSW;
 212   adr = (CTBP & ~1) + (imm6 << 1);
 213   off = load_mem (adr, 2) & ~1; /* Force alignment */
 214   nia = (CTBP & ~1) + off;
 215   TRACE_BRANCH3 (adr, CTBP, off);
 216 }
 217
 218
 219 // CLR1
 220 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
 221 "clr1 <bit3>, <disp16>[r<reg1>]"
 222 {
 223   COMPAT_2 (OP_87C0 ());
 224 }
 225
 226 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 227 *v850e
 228 "clr1 r<reg2>, [r<reg1>]"
 229 {
 230   COMPAT_2 (OP_E407E0 ());
 231 }
 232
 233
 234 // CTRET
 235 0000011111100000 + 0000000101000100:X:::ctret
 236 *v850e
 237 "ctret"
 238 {
 239   nia  = (CTPC & ~1);
 240   PSW = (CTPSW & (CPU)->psw_mask);
 241   TRACE_BRANCH1 (PSW);
 242 }
 243
 244 // CMOV
 245 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 246 *v850e
 247 "cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
 248 {
 249   int cond = condition_met (cccc);
 250   TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
 251   GR[reg3] = cond ? GR[reg1] : GR[reg2];
 252   TRACE_ALU_RESULT (GR[reg3]);
 253 }
 254
 255 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 256 *v850e
 257 "cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
 258 {
 259   int cond = condition_met (cccc);
 260   TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
 261   GR[reg3] = cond ? imm5 : GR[reg2];
 262   TRACE_ALU_RESULT (GR[reg3]);
 263 }
 264
 265 // CMP
 266 rrrrr,001111,RRRRR:I:::cmp
 267 "cmp r<reg1>, r<reg2>"
 268 {
 269   COMPAT_1 (OP_1E0 ());
 270 }
 271
 272 rrrrr,010011,iiiii:II:::cmp
 273 "cmp <imm5>, r<reg2>"
 274 {
 275   COMPAT_1 (OP_260 ());
 276 }
 277
 278
 279
 280 // DI
 281 0000011111100000 + 0000000101100000:X:::di
 282 "di"
 283 {
 284   COMPAT_2 (OP_16007E0 ());
 285 }
 286
 287
 288
 289 // DISPOSE
 290 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
 291 // "dispose <imm5>, <list12>"
 292 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
 293 *v850e
 294 "dispose <imm5>, <list12>":RRRRR == 0
 295 "dispose <imm5>, <list12>, [reg1]"
 296 {
 297   int i;
 298   SAVE_2;
 299
 300   trace_input ("dispose", OP_PUSHPOP1, 0);
 301
 302   SP += (OP[3] & 0x3e) << 1;
 303
 304   /* Load the registers with lower number registers being retrieved
 305      from higher addresses.  */
 306   for (i = 12; i--;)
 307     if ((OP[3] & (1 << type1_regs[ i ])))
 308       {
 309         State.regs[ 20 + i ] = load_mem (SP, 4);
 310         SP += 4;
 311       }
 312
 313   if ((OP[3] & 0x1f0000) != 0)
 314     {
 315       nia = State.regs[ (OP[3] >> 16) & 0x1f];
 316     }
 317
 318   trace_output (OP_PUSHPOP1);
 319 }
 320
 321
 322 // DIV
 323 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 324 *v850e
 325 "div r<reg1>, r<reg2>, r<reg3>"
 326 {
 327   COMPAT_2 (OP_2C007E0 ());
 328 }
 329
 330
 331 // DIVH
 332 rrrrr!0,000010,RRRRR!0:I:::divh
 333 "divh r<reg1>, r<reg2>"
 334 {
 335   COMPAT_1 (OP_40 ());
 336 }
 337
 338 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 339 *v850e
 340 "divh r<reg1>, r<reg2>, r<reg3>"
 341 {
 342   COMPAT_2 (OP_28007E0 ());
 343 }
 344
 345
 346 // DIVHU
 347 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 348 *v850e
 349 "divhu r<reg1>, r<reg2>, r<reg3>"
 350 {
 351   COMPAT_2 (OP_28207E0 ());
 352 }
 353
 354
 355 // DIVU
 356 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 357 *v850e
 358 "divu r<reg1>, r<reg2>, r<reg3>"
 359 {
 360   COMPAT_2 (OP_2C207E0 ());
 361 }
 362
 363
 364 // EI
 365 1000011111100000 + 0000000101100000:X:::ei
 366 "ei"
 367 {
 368   COMPAT_2 (OP_16087E0 ());
 369 }
 370
 371
 372
 373 // HALT
 374 0000011111100000 + 0000000100100000:X:::halt
 375 "halt"
 376 {
 377   COMPAT_2 (OP_12007E0 ());
 378 }
 379
 380
 381
 382 // HSW
 383 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 384 *v850e
 385 "hsw r<reg2>, r<reg3>"
 386 {
 387   unsigned32 value;
 388   TRACE_ALU_INPUT1 (GR[reg2]);
 389
 390   value = GR[reg2];
 391   value >>= 16;
 392   value |= (GR[reg2] << 16);
 393
 394   GR[reg3] = value;
 395
 396   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 397
 398   if (value == 0) PSW |= PSW_Z;
 399   if (value & 0x80000000) PSW |= PSW_S;
 400   if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
 401
 402   TRACE_ALU_RESULT (GR[reg3]);
 403 }
 404
 405
 406
 407 // JARL
 408 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 409 "jarl <disp22>, r<reg2>"
 410 {
 411   GR[reg2] = nia;
 412   nia = cia + disp22;
 413   TRACE_BRANCH1 (GR[reg2]);
 414 }
 415
 416
 417
 418 // JMP
 419 00000000011,RRRRR:I:::jmp
 420 "jmp [r<reg1>]"
 421 {
 422   nia = GR[reg1] & ~1;
 423   TRACE_BRANCH0 ();
 424 }
 425
 426
 427
 428 // JR
 429 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 430 "jr <disp22>"
 431 {
 432   nia = cia + disp22;
 433   TRACE_BRANCH0 ();
 434 }
 435
 436
 437
 438 // LD
 439 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 440 "ld.b <disp16>[r<reg1>], r<reg2>"
 441 {
 442   COMPAT_2 (OP_700 ());
 443 }
 444
 445 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 446 "ld.h <disp16>[r<reg1>], r<reg2>"
 447 {
 448   COMPAT_2 (OP_720 ());
 449 }
 450
 451 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 452 "ld.w <disp16>[r<reg1>], r<reg2>"
 453 {
 454   COMPAT_2 (OP_10720 ());
 455 }
 456
 457 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 458 *v850e
 459 "ld.bu <disp16>[r<reg1>], r<reg2>"
 460 {
 461   COMPAT_2 (OP_10780 ());
 462 }
 463
 464 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 465 *v850e
 466 "ld.hu <disp16>[r<reg1>], r<reg2>"
 467 {
 468   COMPAT_2 (OP_107E0 ());
 469 }
 470
 471
 472 // LDSR
 473 regID,111111,RRRRR + 0000000000100000:IX:::ldsr
 474 "ldsr r<reg1>, s<regID>"
 475 {
 476   TRACE_ALU_INPUT1 (GR[reg1]);
 477
 478   if (&PSW == &SR[regID])
 479     PSW = (GR[reg1] & (CPU)->psw_mask);
 480   else
 481     SR[regID] = GR[reg1];
 482
 483   TRACE_ALU_RESULT (SR[regID]);
 484 }
 485
 486
 487
 488 // MOV
 489 rrrrr!0,000000,RRRRR:I:::mov
 490 "mov r<reg1>, r<reg2>"
 491 {
 492   TRACE_ALU_INPUT0 ();
 493   GR[reg2] = GR[reg1];
 494   TRACE_ALU_RESULT (GR[reg2]);
 495 }
 496
 497
 498 rrrrr!0,010000,iiiii:II:::mov
 499 "mov <imm5>, r<reg2>"
 500 {
 501   COMPAT_1 (OP_200 ());
 502 }
 503
 504 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
 505 *v850e
 506 "mov <imm32>, r<reg1>"
 507 {
 508   SAVE_2;
 509   trace_input ("mov", OP_IMM_REG, 4);
 510   State.regs[ OP[0] ] = load_mem (PC + 2, 4);
 511   trace_output (OP_IMM_REG);
 512 }
 513
 514
 515
 516 // MOVEA
 517 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
 518 "movea <simm16>, r<reg1>, r<reg2>"
 519 {
 520   TRACE_ALU_INPUT2 (GR[reg1], simm16);
 521   GR[reg2] = GR[reg1] + simm16;
 522   TRACE_ALU_RESULT (GR[reg2]);
 523 }
 524
 525
 526
 527 // MOVHI
 528 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
 529 "movhi <uimm16>, r<reg1>, r<reg2>"
 530 {
 531   COMPAT_2 (OP_640 ());
 532 }
 533
 534
 535
 536 // MUL
 537 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 538 *v850e
 539 "mul r<reg1>, r<reg2>, r<reg3>"
 540 {
 541   COMPAT_2 (OP_22007E0 ());
 542 }
 543
 544 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 545 *v850e
 546 "mul <imm9>, r<reg2>, r<reg3>"
 547 {
 548   COMPAT_2 (OP_24007E0 ());
 549 }
 550
 551
 552 // MULH
 553 rrrrr!0,000111,RRRRR:I:::mulh
 554 "mulh r<reg1>, r<reg2>"
 555 {
 556   COMPAT_1 (OP_E0 ());
 557 }
 558
 559 rrrrr!0,010111,iiiii:II:::mulh
 560 "mulh <imm5>, r<reg2>"
 561 {
 562   COMPAT_1 (OP_2E0 ());
 563 }
 564
 565
 566
 567 // MULHI
 568 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
 569 "mulhi <uimm16>, r<reg1>, r<reg2>"
 570 {
 571   COMPAT_2 (OP_6E0 ());
 572 }
 573
 574
 575
 576 // MULU
 577 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 578 *v850e
 579 "mulu r<reg1>, r<reg2>, r<reg3>"
 580 {
 581   COMPAT_2 (OP_22207E0 ());
 582 }
 583
 584 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 585 *v850e
 586 "mulu <imm9>, r<reg2>, r<reg3>"
 587 {
 588   COMPAT_2 (OP_24207E0 ());
 589 }
 590
 591
 592
 593 // NOP
 594 0000000000000000:I:::nop
 595 "nop"
 596 {
 597   /* do nothing, trace nothing */
 598 }
 599
 600
 601
 602 // NOT
 603 rrrrr,000001,RRRRR:I:::not
 604 "not r<reg1>, r<reg2>"
 605 {
 606   COMPAT_1 (OP_20 ());
 607 }
 608
 609
 610
 611 // NOT1
 612 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
 613 "not1 <bit3>, <disp16>[r<reg1>]"
 614 {
 615   COMPAT_2 (OP_47C0 ());
 616 }
 617
 618 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 619 *v850e
 620 "not1 r<reg2>, r<reg1>"
 621 {
 622   COMPAT_2 (OP_E207E0 ());
 623 }
 624
 625
 626
 627 // OR
 628 rrrrr,001000,RRRRR:I:::or
 629 "or r<reg1>, r<reg2>"
 630 {
 631   COMPAT_1 (OP_100 ());
 632 }
 633
 634
 635
 636 // ORI
 637 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 638 "ori <uimm16>, r<reg1>, r<reg2>"
 639 {
 640   COMPAT_2 (OP_680 ());
 641 }
 642
 643
 644
 645 // PREPARE
 646 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
 647 *v850e
 648 "prepare <list12>, <imm5>"
 649 {
 650   int  i;
 651   SAVE_2;
 652
 653   trace_input ("prepare", OP_PUSHPOP1, 0);
 654
 655   /* Store the registers with lower number registers being placed at
 656      higher addresses.  */
 657   for (i = 0; i < 12; i++)
 658     if ((OP[3] & (1 << type1_regs[ i ])))
 659       {
 660         SP -= 4;
 661         store_mem (SP, 4, State.regs[ 20 + i ]);
 662       }
 663
 664   SP -= (OP[3] & 0x3e) << 1;
 665
 666   trace_output (OP_PUSHPOP1);
 667 }
 668
 669
 670 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
 671 *v850e
 672 "prepare <list12>, <imm5>, sp"
 673 {
 674   COMPAT_2 (OP_30780 ());
 675 }
 676
 677 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
 678 *v850e
 679 "prepare <list12>, <imm5>, <uimm16>"
 680 {
 681   COMPAT_2 (OP_B0780 ());
 682 }
 683
 684 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
 685 *v850e
 686 "prepare <list12>, <imm5>, <uimm16>"
 687 {
 688   COMPAT_2 (OP_130780 ());
 689 }
 690
 691 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
 692 *v850e
 693 "prepare <list12>, <imm5>, <uimm32>"
 694 {
 695   COMPAT_2 (OP_1B0780 ());
 696 }
 697
 698
 699
 700 // RETI
 701 0000011111100000 + 0000000101000000:X:::reti
 702 "reti"
 703 {
 704   if ((PSW & PSW_EP))
 705     {
 706       nia = (EIPC & ~1);
 707       PSW = EIPSW;
 708     }
 709   else if ((PSW & PSW_NP))
 710     {
 711       nia = (FEPC & ~1);
 712       PSW = FEPSW;
 713     }
 714   else
 715     {
 716       nia = (EIPC & ~1);
 717       PSW = EIPSW;
 718     }
 719   TRACE_BRANCH1 (PSW);
 720 }
 721
 722
 723
 724 // SAR
 725 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
 726 "sar r<reg1>, r<reg2>"
 727 {
 728   COMPAT_2 (OP_A007E0 ());
 729 }
 730
 731 rrrrr,010101,iiiii:II:::sar
 732 "sar <imm5>, r<reg2>"
 733 {
 734   COMPAT_1 (OP_2A0 ());
 735 }
 736
 737
 738
 739 // SASF
 740 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
 741 *v850e
 742 "sasf %s<cccc>, r<reg2>"
 743 {
 744   COMPAT_2 (OP_20007E0 ());
 745 }
 746
 747
 748
 749
 750 // SATADD
 751 rrrrr!0,000110,RRRRR:I:::satadd
 752 "satadd r<reg1>, r<reg2>"
 753 {
 754   COMPAT_1 (OP_C0 ());
 755 }
 756
 757 rrrrr!0,010001,iiiii:II:::satadd
 758 "satadd <imm5>, r<reg2>"
 759 {
 760   COMPAT_1 (OP_220 ());
 761 }
 762
 763
 764
 765 // SATSUB
 766 rrrrr!0,000101,RRRRR:I:::satsub
 767 "satsub r<reg1>, r<reg2>"
 768 {
 769   COMPAT_1 (OP_A0 ());
 770 }
 771
 772
 773
 774 // SATSUBI
 775 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
 776 "satsubi <simm16>, r<reg1>, r<reg2>"
 777 {
 778   COMPAT_2 (OP_660 ());
 779 }
 780
 781
 782
 783 // SATSUBR
 784 rrrrr!0,000100,RRRRR:I:::satsubr
 785 "satsubr r<reg1>, r<reg2>"
 786 {
 787   COMPAT_1 (OP_80 ());
 788 }
 789
 790
 791
 792 // SETF
 793 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
 794 "setf %s<cccc>, r<reg2>"
 795 {
 796   COMPAT_2 (OP_7E0 ());
 797 }
 798
 799
 800
 801 // SET1
 802 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
 803 "set1 <bit3>, <disp16>[r<reg1>]"
 804 {
 805   COMPAT_2 (OP_7C0 ());
 806 }
 807
 808 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
 809 *v850e
 810 "set1 r<reg2>, [r<reg1>]"
 811 {
 812   COMPAT_2 (OP_E007E0 ());
 813 }
 814
 815
 816
 817 // SHL
 818 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
 819 "shl r<reg1>, r<reg2>"
 820 {
 821   COMPAT_2 (OP_C007E0 ());
 822 }
 823
 824 rrrrr,010110,iiiii:II:::shl
 825 "shl <imm5>, r<reg2>"
 826 {
 827   COMPAT_1 (OP_2C0 ());
 828 }
 829
 830
 831
 832 // SHR
 833 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
 834 "shr r<reg1>, r<reg2>"
 835 {
 836   COMPAT_2 (OP_8007E0 ());
 837 }
 838
 839 rrrrr,010100,iiiii:II:::shr
 840 "shr <imm5>, r<reg2>"
 841 {
 842   COMPAT_1 (OP_280 ());
 843 }
 844
 845
 846
 847 // SLD
 848 rrrrr,0110,ddddddd:IV:::sld.b
 849 "sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
 850 "sld.b <disp7>[ep], r<reg2>"
 851 {
 852   unsigned32 addr = EP + disp7;
 853   unsigned32 result = load_mem (addr, 1);
 854   if (PSW & PSW_US)
 855     {
 856       GR[reg2] = result;
 857       TRACE_LD_NAME ("sld.bu", addr, result);
 858     }
 859   else
 860     {
 861       result = EXTEND8 (result);
 862       GR[reg2] = result;
 863       TRACE_LD (addr, result);
 864     }
 865 }
 866
 867 rrrrr,1000,ddddddd:IV:::sld.h
 868 "sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
 869 "sld.h <disp8>[ep], r<reg2>"
 870 {
 871   unsigned32 addr = EP + disp8;
 872   unsigned32 result = load_mem (addr, 2);
 873   if (PSW & PSW_US)
 874     {
 875       GR[reg2] = result;
 876       TRACE_LD_NAME ("sld.hu", addr, result);
 877     }
 878   else
 879     {
 880       result = EXTEND16 (result);
 881       GR[reg2] = result;
 882       TRACE_LD (addr, result);
 883     }
 884 }
 885
 886 rrrrr,1010,dddddd,0:IV:::sld.w
 887 "sld.w <disp8>[ep], r<reg2>"
 888 {
 889   unsigned32 addr = EP + disp8;
 890   unsigned32 result = load_mem (addr, 4);
 891   GR[reg2] = result;
 892   TRACE_LD (addr, result);
 893 }
 894
 895 rrrrr!0,0000110,dddd:IV:::sld.bu
 896 *v850e
 897 "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
 898 "sld.bu <disp4>[ep], r<reg2>"
 899 {
 900   unsigned32 addr = EP + disp4;
 901   unsigned32 result = load_mem (addr, 1);
 902   if (PSW & PSW_US)
 903     {
 904       result = EXTEND8 (result);
 905       GR[reg2] = result;
 906       TRACE_LD_NAME ("sld.b", addr, result);
 907     }
 908   else
 909     {
 910       GR[reg2] = result;
 911       TRACE_LD (addr, result);
 912     }
 913 }
 914
 915 rrrrr!0,0000111,dddd:IV:::sld.hu
 916 *v850e
 917 "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
 918 "sld.hu <disp5>[ep], r<reg2>"
 919 {
 920   unsigned32 addr = EP + disp5;
 921   unsigned32 result = load_mem (addr, 2);
 922   if (PSW & PSW_US)
 923     {
 924       result = EXTEND16 (result);
 925       GR[reg2] = result;
 926       TRACE_LD_NAME ("sld.h", addr, result);
 927     }
 928   else
 929     {
 930       GR[reg2] = result;
 931       TRACE_LD (addr, result);
 932     }
 933 }
 934
 935 // SST
 936 rrrrr,0111,ddddddd:IV:::sst.b
 937 "sst.b r<reg2>, <disp7>[ep]"
 938 {
 939   COMPAT_1 (OP_380 ());
 940 }
 941
 942 rrrrr,1001,ddddddd:IV:::sst.h
 943 "sst.h r<reg2>, <disp8>[ep]"
 944 {
 945   COMPAT_1 (OP_480 ());
 946 }
 947
 948 rrrrr,1010,dddddd,1:IV:::sst.w
 949 "sst.w r<reg2>, <disp8>[ep]"
 950 {
 951   COMPAT_1 (OP_501 ());
 952 }
 953
 954 // ST
 955 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
 956 "st.b r<reg2>, <disp16>[r<reg1>]"
 957 {
 958   COMPAT_2 (OP_740 ());
 959 }
 960
 961 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
 962 "st.h r<reg2>, <disp16>[r<reg1>]"
 963 {
 964   COMPAT_2 (OP_760 ());
 965 }
 966
 967 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 968 "st.w r<reg2>, <disp16>[r<reg1>]"
 969 {
 970   COMPAT_2 (OP_10760 ());
 971 }
 972
 973 // STSR
 974 rrrrr,111111,regID + 0000000001000000:IX:::stsr
 975 "stsr s<regID>, r<reg2>"
 976 {
 977   TRACE_ALU_INPUT1 (SR[regID]);
 978   GR[reg2] = SR[regID];
 979   TRACE_ALU_RESULT (GR[reg2]);
 980 }
 981
 982 // SUB
 983 rrrrr,001101,RRRRR:I:::sub
 984 "sub r<reg1>, r<reg2>"
 985 {
 986   COMPAT_1 (OP_1A0 ());
 987 }
 988
 989 // SUBR
 990 rrrrr,001100,RRRRR:I:::subr
 991 "subr r<reg1>, r<reg2>"
 992 {
 993   COMPAT_1 (OP_180 ());
 994 }
 995
 996 // SWITCH
 997 00000000010,RRRRR:I:::switch
 998 *v850e
 999 "switch r<reg1>"
1000 {
1001   unsigned long adr;
1002   SAVE_1;
1003   trace_input ("switch", OP_REG, 0);
1004   adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1005   nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1006   trace_output (OP_REG);
1007 }
1008
1009 // SXB
1010 00000000101,RRRRR:I:::sxb
1011 *v850e
1012 "sxb r<reg1>"
1013 {
1014   TRACE_ALU_INPUT1 (GR[reg1]);
1015   GR[reg1] = EXTEND8 (GR[reg1]);
1016   TRACE_ALU_RESULT (GR[reg1]);
1017 }
1018
1019 // SXH
1020 00000000111,RRRRR:I:::sxh
1021 *v850e
1022 "sxh r<reg1>"
1023 {
1024   TRACE_ALU_INPUT1 (GR[reg1]);
1025   GR[reg1] = EXTEND16 (GR[reg1]);
1026   TRACE_ALU_RESULT (GR[reg1]);
1027 }
1028
1029 // TRAP
1030 00000111111,iiiii + 0000000100000000:X:::trap
1031 "trap <vector>"
1032 {
1033   COMPAT_2 (OP_10007E0 ());
1034 }
1035
1036 // TST
1037 rrrrr,001011,RRRRR:I:::tst
1038 "tst r<reg1>, r<reg2>"
1039 {
1040   COMPAT_1 (OP_160 ());
1041 }
1042
1043 // TST1
1044 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1045 "tst1 <bit3>, <disp16>[r<reg1>]"
1046 {
1047   COMPAT_2 (OP_C7C0 ());
1048 }
1049
1050 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1051 *v850e
1052 "tst1 r<reg2>, [r<reg1>]"
1053 {
1054   COMPAT_2 (OP_E607E0 ());
1055 }
1056
1057 // XOR
1058 rrrrr,001001,RRRRR:I:::xor
1059 "xor r<reg1>, r<reg2>"
1060 {
1061   COMPAT_1 (OP_120 ());
1062 }
1063
1064 // XORI
1065 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1066 "xori <uimm16>, r<reg1>, r<reg2>"
1067 {
1068   COMPAT_2 (OP_6A0 ());
1069 }
1070
1071 // ZXB
1072 00000000100,RRRRR:I:::zxb
1073 *v850e
1074 "zxb r<reg1>"
1075 {
1076   TRACE_ALU_INPUT1 (GR[reg1]);
1077   GR[reg1] = GR[reg1] & 0xff;
1078   TRACE_ALU_RESULT (GR[reg1]);
1079 }
1080
1081 // ZXH
1082 00000000110,RRRRR:I:::zxh
1083 *v850e
1084 "zxh r<reg1>"
1085 {
1086   TRACE_ALU_INPUT1 (GR[reg1]);
1087   GR[reg1] = GR[reg1] & 0xffff;
1088   TRACE_ALU_RESULT (GR[reg1]);
1089 }
1090
1091 // Right field must be zero so that it doesn't clash with DIVH
1092 // Left field must be non-zero so that it doesn't clash with SWITCH
1093 11111,000010,00000:I:::break
1094 {
1095   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1096 }
1097
1098 // New breakpoint: 0x7E0 0x7E0
1099 00000,111111,00000 + 00000,11111,100000:X:::ilgop
1100 {
1101   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1102 }