sim/v850/v850.igen

   1 :option::insn-bit-size:16
   2 :option::hi-bit-nr:15
   3
   4
   5 :option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
   6 # start-sanitize-v850e
   7 :option::format-names:XI,XII,XIII
   8 # end-sanitize-v850e
   9 # start-sanitize-v850eq
  10 :option::format-names:XIV,XV
  11 # end-sanitize-v850eq
  12 :option::format-names:Z
  13
  14
  15 :model::v850:v850:
  16
  17 # start-sanitize-v850e
  18 :option::multi-sim:true
  19 :model::v850e:v850e:
  20 # end-sanitize-v850e
  21
  22 # start-sanitize-v850eq
  23 :option::multi-sim:true
  24 :model::v850eq:v850eq:
  25 # end-sanitize-v850eq
  26
  27
  28
  29 // Cache macros
  30
  31 :cache::unsigned:reg1:RRRRR:(RRRRR)
  32 :cache::unsigned:reg2:rrrrr:(rrrrr)
  33 :cache::unsigned:reg3:wwwww:(wwwww)
  34
  35 :cache::unsigned:disp4:dddd:(dddd)
  36 # start-sanitize-v850e
  37 :cache::unsigned:disp5:dddd:(dddd << 1)
  38 # end-sanitize-v850e
  39 :cache::unsigned:disp7:ddddddd:ddddddd
  40 :cache::unsigned:disp8:ddddddd:(ddddddd << 1)
  41 :cache::unsigned:disp8:dddddd:(dddddd << 2)
  42 :cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
  43 :cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
  44 :cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
  45 :cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
  46 :cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
  47
  48 :cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
  49 :cache::unsigned:imm6:iiiiii:iiiiii
  50 :cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
  51 # start-sanitize-v850eq
  52 :cache::unsigned:imm5:iiii:(32 - (iiii << 1))
  53 # end-sanitize-v850eq
  54 :cache::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
  55 :cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  56 :cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
  57 # start-sanitize-v850e
  58 :cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
  59 # end-sanitize-v850e
  60
  61 :cache::unsigned:vector:iiiii:iiiii
  62
  63 # start-sanitize-v850e
  64 :cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
  65 :cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
  66 # end-sanitize-v850e
  67
  68 :cache::unsigned:bit3:bbb:bbb
  69
  70
  71 // What do we do with an illegal instruction?
  72 :internal:::illegal
  73 {
  74   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  75                   (unsigned long) cia);
  76   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  77 }
  78
  79
  80
  81 // Add
  82
  83 rrrrr,001110,RRRRR:I:::add
  84 "add r<reg1>, r<reg2>"
  85 {
  86   COMPAT_1 (OP_1C0 ());
  87 }
  88
  89 rrrrr,010010,iiiii:II:::add
  90 "add <imm5>,r<reg2>"
  91 {
  92   COMPAT_1 (OP_240 ());
  93 }
  94
  95
  96
  97 // ADDI
  98 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
  99 "addi <simm16>, r<reg1>, r<reg2>"
 100 {
 101   COMPAT_2 (OP_600 ());
 102 }
 103
 104
 105
 106 // AND
 107 rrrrr,001010,RRRRR:I:::and
 108 "and r<reg1>, r<reg2>"
 109 {
 110   COMPAT_1 (OP_140 ());
 111 }
 112
 113
 114
 115 // ANDI
 116 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
 117 "andi <uimm16>, r<reg1>, r<reg2>"
 118 {
 119   COMPAT_2 (OP_6C0 ());
 120 }
 121
 122
 123
 124 // Bcond
 125 // ddddd,1011,ddd,cccc:III:::Bcond
 126 // "b<cond> disp9"
 127
 128 ddddd,1011,ddd,0000:III:::bv
 129 "bv <disp9>"
 130 {
 131   COMPAT_1 (OP_580 ());
 132 }
 133
 134 ddddd,1011,ddd,0001:III:::bl
 135 "bl <disp9>"
 136 {
 137   COMPAT_1 (OP_581 ());
 138 }
 139
 140 ddddd,1011,ddd,0010:III:::be
 141 "be <disp9>"
 142 {
 143   COMPAT_1 (OP_582 ());
 144 }
 145
 146 ddddd,1011,ddd,0011:III:::bnh
 147 "bnh <disp9>"
 148 {
 149   COMPAT_1 (OP_583 ());
 150 }
 151
 152 ddddd,1011,ddd,0100:III:::bn
 153 "bn <disp9>"
 154 {
 155   COMPAT_1 (OP_584 ());
 156 }
 157
 158 ddddd,1011,ddd,0101:III:::br
 159 "br <disp9>"
 160 {
 161   COMPAT_1 (OP_585 ());
 162 }
 163
 164 ddddd,1011,ddd,0110:III:::blt
 165 "blt <disp9>"
 166 {
 167   COMPAT_1 (OP_586 ());
 168 }
 169
 170 ddddd,1011,ddd,0111:III:::ble
 171 "ble <disp9>"
 172 {
 173   COMPAT_1 (OP_587 ());
 174 }
 175
 176 ddddd,1011,ddd,1000:III:::bnv
 177 "bnv <disp9>"
 178 {
 179   COMPAT_1 (OP_588 ());
 180 }
 181
 182 ddddd,1011,ddd,1001:III:::bnl
 183 "bnl <disp9>"
 184 {
 185   COMPAT_1 (OP_589 ());
 186 }
 187
 188 ddddd,1011,ddd,1010:III:::bne
 189 "bne <disp9>"
 190 {
 191   COMPAT_1 (OP_58A ());
 192 }
 193
 194 ddddd,1011,ddd,1011:III:::bh
 195 "bh <disp9>"
 196 {
 197   COMPAT_1 (OP_58B ());
 198 }
 199
 200 ddddd,1011,ddd,1100:III:::bp
 201 "bp <disp9>"
 202 {
 203   COMPAT_1 (OP_58C ());
 204 }
 205
 206 ddddd,1011,ddd,1101:III:::bsa
 207 "bsa <disp9>"
 208 {
 209   COMPAT_1 (OP_58D ());
 210 }
 211
 212 ddddd,1011,ddd,1110:III:::bge
 213 "bge <disp9>"
 214 {
 215   COMPAT_1 (OP_58E ());
 216 }
 217
 218 ddddd,1011,ddd,1111:III:::bgt
 219 "bgt <disp9>"
 220 {
 221   COMPAT_1 (OP_58F ());
 222 }
 223
 224
 225
 226 // start-sanitize-v850e
 227 // BSH
 228 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 229 *v850e
 230 // start-sanitize-v850eq
 231 *v850eq
 232 // end-sanitize-v850eq
 233 "bsh r<reg2>, r<reg3>"
 234 {
 235   unsigned32 value;
 236   TRACE_ALU_INPUT1 (GR[reg2]);
 237
 238   value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
 239            | MOVED32 (GR[reg2], 31, 24, 23, 16)
 240            | MOVED32 (GR[reg2], 7, 0, 15, 8)
 241            | MOVED32 (GR[reg2], 15, 8, 7, 0));
 242
 243   GR[reg3] = value;
 244   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 245   if (value == 0) PSW |= PSW_Z;
 246   if (value & 0x80000000) PSW |= PSW_S;
 247   if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
 248
 249   TRACE_ALU_RESULT (GR[reg3]);
 250 }
 251
 252
 253
 254 // end-sanitize-v850e
 255 // start-sanitize-v850e
 256 // BSW
 257 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 258 *v850e
 259 // start-sanitize-v850eq
 260 *v850eq
 261 // end-sanitize-v850eq
 262 "bsw r<reg2>, r<reg3>"
 263 {
 264 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
 265   unsigned32 value;
 266   TRACE_ALU_INPUT1 (GR[reg2]);
 267
 268   value = GR[reg2];
 269   value >>= 24;
 270   value |= (GR[reg2] << 24);
 271   value |= ((GR[reg2] << 8) & 0x00ff0000);
 272   value |= ((GR[reg2] >> 8) & 0x0000ff00);
 273   GR[reg3] = value;
 274
 275   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 276
 277   if (value == 0) PSW |= PSW_Z;
 278   if (value & 0x80000000) PSW |= PSW_S;
 279   if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
 280
 281   TRACE_ALU_RESULT (GR[reg3]);
 282 }
 283
 284
 285
 286 // end-sanitize-v850e
 287 // start-sanitize-v850e
 288 // CALLT
 289 0000001000,iiiiii:II:::callt
 290 *v850e
 291 // start-sanitize-v850eq
 292 *v850eq
 293 // end-sanitize-v850eq
 294 "callt <imm6>"
 295 {
 296   unsigned32 adr;
 297   unsigned32 off;
 298   CTPC  = cia + 2;
 299   CTPSW = PSW;
 300   adr = (CTBP & ~1) + (imm6 << 1);
 301   off = load_mem (adr, 2) & ~1; /* Force alignment */
 302   nia = (CTBP & ~1) + off;
 303   TRACE_BRANCH3 (adr, CTBP, off);
 304 }
 305
 306
 307
 308 // end-sanitize-v850e
 309 // CLR1
 310 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
 311 "clr1 <bit3>, <disp16>[r<reg1>]"
 312 {
 313   COMPAT_2 (OP_87C0 ());
 314 }
 315
 316 // start-sanitize-v850e
 317 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 318 *v850e
 319 // start-sanitize-v850eq
 320 *v850eq
 321 // end-sanitize-v850eq
 322 "clr1 r<reg2>, [r<reg1>]"
 323 {
 324   COMPAT_2 (OP_E407E0 ());
 325 }
 326
 327
 328
 329 // end-sanitize-v850e
 330 // start-sanitize-v850e
 331 // CTRET
 332 0000011111100000 + 0000000101000100:X:::ctret
 333 *v850e
 334 // start-sanitize-v850eq
 335 *v850eq
 336 // end-sanitize-v850eq
 337 "ctret"
 338 {
 339   nia  = (CTPC & ~1);
 340   PSW = (CTPSW & (CPU)->psw_mask);
 341   TRACE_BRANCH1 (PSW);
 342 }
 343
 344
 345
 346 // end-sanitize-v850e
 347 // start-sanitize-v850e
 348 // CMOV
 349 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 350 *v850e
 351 // start-sanitize-v850eq
 352 *v850eq
 353 // end-sanitize-v850eq
 354 "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
 355 {
 356   TRACE_ALU_INPUT3 (cccc, GR[reg1], GR[reg2]);
 357   GR[reg3] = condition_met (cccc) ? GR[reg1] : GR[reg2];
 358   TRACE_ALU_RESULT (GR[reg3]);
 359 }
 360
 361 // end-sanitize-v850e
 362 // start-sanitize-v850e
 363 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 364 *v850e
 365 // start-sanitize-v850eq
 366 *v850eq
 367 // end-sanitize-v850eq
 368 "cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
 369 {
 370   COMPAT_2 (OP_30007E0 ());
 371 }
 372
 373
 374
 375 // end-sanitize-v850e
 376 // CMP
 377 rrrrr,001111,RRRRR:I:::cmp
 378 "cmp r<reg1>, r<reg2>"
 379 {
 380   COMPAT_1 (OP_1E0 ());
 381 }
 382
 383 rrrrr,010011,iiiii:II:::cmp
 384 "cmp <imm5>, r<reg2>"
 385 {
 386   COMPAT_1 (OP_260 ());
 387 }
 388
 389
 390
 391 // DI
 392 0000011111100000 + 0000000101100000:X:::di
 393 "di"
 394 {
 395   COMPAT_2 (OP_16007E0 ());
 396 }
 397
 398
 399
 400 // start-sanitize-v850e
 401 // DISPOSE
 402 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
 403 // "dispose <imm5>, <list12>"
 404 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
 405 *v850e
 406 // start-sanitize-v850eq
 407 *v850eq
 408 // end-sanitize-v850eq
 409 "dispose <imm5>, <list12>":RRRRR == 0
 410 "dispose <imm5>, <list12>, [reg1]"
 411 {
 412   int i;
 413   SAVE_2;
 414
 415   trace_input ("dispose", OP_PUSHPOP1, 0);
 416
 417   SP += (OP[3] & 0x3e) << 1;
 418
 419   /* Load the registers with lower number registers being retrieved
 420      from higher addresses.  */
 421   for (i = 12; i--;)
 422     if ((OP[3] & (1 << type1_regs[ i ])))
 423       {
 424         State.regs[ 20 + i ] = load_mem (SP, 4);
 425         SP += 4;
 426       }
 427
 428   if ((OP[3] & 0x1f0000) != 0)
 429     {
 430       nia = State.regs[ (OP[3] >> 16) & 0x1f];
 431     }
 432
 433   trace_output (OP_PUSHPOP1);
 434 }
 435
 436
 437
 438 // end-sanitize-v850e
 439 // start-sanitize-v850e
 440 // DIV
 441 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 442 *v850e
 443 "div r<reg1>, r<reg2>, r<reg3>"
 444 {
 445   COMPAT_2 (OP_2C007E0 ());
 446 }
 447
 448
 449
 450
 451 // end-sanitize-v850e
 452 // DIVH
 453 rrrrr!0,000010,RRRRR!0:I:::divh
 454 "divh r<reg1>, r<reg2>"
 455 {
 456   COMPAT_1 (OP_40 ());
 457 }
 458
 459 // start-sanitize-v850e
 460 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 461 *v850e
 462 "divh r<reg1>, r<reg2>, r<reg3>"
 463 {
 464   COMPAT_2 (OP_28007E0 ());
 465 }
 466
 467
 468
 469 // end-sanitize-v850e
 470 // start-sanitize-v850e
 471 // DIVHU
 472 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 473 *v850e
 474 "divhu r<reg1>, r<reg2>, r<reg3>"
 475 {
 476   COMPAT_2 (OP_28207E0 ());
 477 }
 478
 479
 480
 481 // end-sanitize-v850e
 482 // start-sanitize-v850e
 483 // DIVU
 484 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 485 *v850e
 486 "divu r<reg1>, r<reg2>, r<reg3>"
 487 {
 488   COMPAT_2 (OP_2C207E0 ());
 489 }
 490
 491
 492
 493 // end-sanitize-v850e
 494 // EI
 495 1000011111100000 + 0000000101100000:X:::ei
 496 "ei"
 497 {
 498   COMPAT_2 (OP_16087E0 ());
 499 }
 500
 501
 502
 503 // HALT
 504 0000011111100000 + 0000000100100000:X:::halt
 505 "halt"
 506 {
 507   COMPAT_2 (OP_12007E0 ());
 508 }
 509
 510
 511
 512 // start-sanitize-v850e
 513 // HSW
 514 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 515 *v850e
 516 // start-sanitize-v850eq
 517 *v850eq
 518 // end-sanitize-v850eq
 519 "hsw r<reg2>, r<reg3>"
 520 {
 521   unsigned32 value;
 522   TRACE_ALU_INPUT1 (GR[reg2]);
 523
 524   value = GR[reg2];
 525   value >>= 16;
 526   value |= (GR[reg2] << 16);
 527
 528   GR[reg3] = value;
 529
 530   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 531
 532   if (value == 0) PSW |= PSW_Z;
 533   if (value & 0x80000000) PSW |= PSW_S;
 534   if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
 535
 536   TRACE_ALU_RESULT (GR[reg3]);
 537 }
 538
 539
 540
 541 // end-sanitize-v850e
 542 // JARL
 543 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 544 "jarl <disp22>, r<reg2>"
 545 {
 546   COMPAT_2 (OP_780 ());
 547 }
 548
 549
 550
 551 // JMP
 552 00000000011,RRRRR:I:::jmp
 553 "jmp [r<reg1>]"
 554 {
 555   SAVE_1;
 556   trace_input ("jmp", OP_REG, 0);
 557   nia = State.regs[ reg1 ];
 558   trace_output (OP_REG);
 559 }
 560
 561
 562
 563 // JR
 564 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 565 "jr <disp22>"
 566 {
 567   COMPAT_2 (OP_780 ());
 568 }
 569
 570
 571
 572 // LD
 573 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 574 "ld.b <disp16>[r<reg1>, r<reg2>"
 575 {
 576   COMPAT_2 (OP_700 ());
 577 }
 578
 579 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 580 "ld.h <disp16>[r<reg1>], r<reg2>"
 581 {
 582   COMPAT_2 (OP_720 ());
 583 }
 584
 585 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 586 "ld.w <disp16>[r<reg1>], r<reg2>"
 587 {
 588   COMPAT_2 (OP_10720 ());
 589 }
 590
 591 // start-sanitize-v850e
 592 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 593 *v850e
 594 // start-sanitize-v850eq
 595 *v850eq
 596 // end-sanitize-v850eq
 597 "ld.bu <disp16>[r<reg1>], r<reg2>"
 598 {
 599   COMPAT_2 (OP_10780 ());
 600 }
 601
 602 // end-sanitize-v850e
 603 // start-sanitize-v850e
 604 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 605 *v850e
 606 // start-sanitize-v850eq
 607 *v850eq
 608 // end-sanitize-v850eq
 609 "ld.hu <disp16>[r<reg1>], r<reg2>"
 610 {
 611   COMPAT_2 (OP_107E0 ());
 612 }
 613
 614
 615 // end-sanitize-v850e
 616 // LDSR
 617 regID,111111,RRRRR + 0000000000100000:IX:::ldsr
 618 "ldsr r<reg1>, s<regID>"
 619 {
 620   TRACE_ALU_INPUT1 (GR[reg1]);
 621
 622   if (&PSW == &SR[regID])
 623     PSW = (GR[reg1] & (CPU)->psw_mask);
 624   else
 625     SR[regID] = GR[reg1];
 626
 627   TRACE_ALU_RESULT (SR[regID]);
 628 }
 629
 630
 631
 632 // MOV
 633 rrrrr!0,000000,RRRRR:I:::mov
 634 "mov r<reg1>, r<reg2>"
 635 {
 636   TRACE_ALU_INPUT0 ();
 637   GR[reg2] = GR[reg1];
 638   TRACE_ALU_RESULT (GR[reg2]);
 639 }
 640
 641
 642 rrrrr!0,010000,iiiii:II:::mov
 643 "mov <imm5>, r<reg2>"
 644 {
 645   COMPAT_1 (OP_200 ());
 646 }
 647
 648 // start-sanitize-v850e
 649 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
 650 *v850e
 651 // start-sanitize-v850eq
 652 *v850eq
 653 // end-sanitize-v850eq
 654 "mov <imm32>, r<reg1>"
 655 {
 656   SAVE_2;
 657   trace_input ("mov", OP_IMM_REG, 4);
 658   State.regs[ OP[0] ] = load_mem (PC + 2, 4);
 659   trace_output (OP_IMM_REG);
 660 }
 661
 662
 663
 664 // end-sanitize-v850e
 665 // MOVEA
 666 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
 667 "movea <simm16>, r<reg1>, r<reg2>"
 668 {
 669   TRACE_ALU_INPUT2 (GR[reg1], simm16);
 670   GR[reg2] = GR[reg1] + simm16;
 671   TRACE_ALU_RESULT (GR[reg2]);
 672 }
 673
 674
 675
 676 // MOVHI
 677 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
 678 "movhi <uimm16>, r<reg1>, r<reg2>"
 679 {
 680   COMPAT_2 (OP_640 ());
 681 }
 682
 683
 684
 685 // start-sanitize-v850e
 686 // MUL
 687 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 688 *v850e
 689 // start-sanitize-v850eq
 690 *v850eq
 691 // end-sanitize-v850eq
 692 "mul r<reg1>, r<reg2>, r<reg3>"
 693 {
 694   COMPAT_2 (OP_22007E0 ());
 695 }
 696
 697 // end-sanitize-v850e
 698 // start-sanitize-v850e
 699 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 700 *v850e
 701 // start-sanitize-v850eq
 702 *v850eq
 703 // end-sanitize-v850eq
 704 "mul <imm9>, r<reg2>, r<reg3>"
 705 {
 706   COMPAT_2 (OP_24007E0 ());
 707 }
 708
 709
 710
 711 // end-sanitize-v850e
 712 // MULH
 713 rrrrr!0,000111,RRRRR:I:::mulh
 714 "mulh r<reg1>, r<reg2>"
 715 {
 716   COMPAT_1 (OP_E0 ());
 717 }
 718
 719 rrrrr!0,010111,iiiii:II:::mulh
 720 "mulh <imm5>, r<reg2>"
 721 {
 722   COMPAT_1 (OP_2E0 ());
 723 }
 724
 725
 726
 727 // MULHI
 728 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
 729 "mulhi <uimm16>, r<reg1>, r<reg2>"
 730 {
 731   COMPAT_2 (OP_6E0 ());
 732 }
 733
 734
 735
 736 // start-sanitize-v850e
 737 // MULU
 738 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 739 *v850e
 740 // start-sanitize-v850eq
 741 *v850eq
 742 // end-sanitize-v850eq
 743 "mulu r<reg1>, r<reg2>, r<reg3>"
 744 {
 745   COMPAT_2 (OP_22207E0 ());
 746 }
 747
 748 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 749 *v850e
 750 // start-sanitize-v850eq
 751 *v850eq
 752 // end-sanitize-v850eq
 753 "mulu <imm9>, r<reg2>, r<reg3>"
 754 {
 755   COMPAT_2 (OP_24207E0 ());
 756 }
 757
 758
 759
 760 // end-sanitize-v850e
 761 // NOP
 762 0000000000000000:I:::nop
 763 "nop"
 764 {
 765   /* do nothing, trace nothing */
 766 }
 767
 768
 769
 770 // NOT
 771 rrrrr,000001,RRRRR:I:::not
 772 "not r<reg1>, r<reg2>"
 773 {
 774   COMPAT_1 (OP_20 ());
 775 }
 776
 777
 778
 779 // NOT1
 780 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
 781 "not1 <bit3>, <disp16>[r<reg1>]"
 782 {
 783   COMPAT_2 (OP_47C0 ());
 784 }
 785
 786 // start-sanitize-v850e
 787 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 788 *v850e
 789 // start-sanitize-v850eq
 790 *v850eq
 791 // end-sanitize-v850eq
 792 "not1 r<reg2>, r<reg1>"
 793 {
 794   COMPAT_2 (OP_E207E0 ());
 795 }
 796
 797
 798
 799 // end-sanitize-v850e
 800 // OR
 801 rrrrr,001000,RRRRR:I:::or
 802 "or r<reg1>, r<reg2>"
 803 {
 804   COMPAT_1 (OP_100 ());
 805 }
 806
 807
 808
 809 // ORI
 810 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 811 "ori <uimm16>, r<reg1>, r<reg2>"
 812 {
 813   COMPAT_2 (OP_680 ());
 814 }
 815
 816
 817
 818 // start-sanitize-v850e
 819 // PREPARE
 820 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
 821 *v850e
 822 // start-sanitize-v850eq
 823 *v850eq
 824 // end-sanitize-v850eq
 825 "prepare <list12>, <imm5>"
 826 {
 827   int  i;
 828   SAVE_2;
 829
 830   trace_input ("prepare", OP_PUSHPOP1, 0);
 831
 832   /* Store the registers with lower number registers being placed at
 833      higher addresses.  */
 834   for (i = 0; i < 12; i++)
 835     if ((OP[3] & (1 << type1_regs[ i ])))
 836       {
 837         SP -= 4;
 838         store_mem (SP, 4, State.regs[ 20 + i ]);
 839       }
 840
 841   SP -= (OP[3] & 0x3e) << 1;
 842
 843   trace_output (OP_PUSHPOP1);
 844 }
 845
 846
 847 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
 848 *v850e
 849 // start-sanitize-v850eq
 850 *v850eq
 851 // end-sanitize-v850eq
 852 "prepare <list12>, <imm5>, sp"
 853 {
 854   COMPAT_2 (OP_30780 ());
 855 }
 856
 857 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
 858 *v850e
 859 // start-sanitize-v850eq
 860 *v850eq
 861 // end-sanitize-v850eq
 862 "prepare <list12>, <imm5>, <uimm16>"
 863 {
 864   COMPAT_2 (OP_B0780 ());
 865 }
 866
 867 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
 868 *v850e
 869 // start-sanitize-v850eq
 870 *v850eq
 871 // end-sanitize-v850eq
 872 "prepare <list12>, <imm5>, <uimm16>"
 873 {
 874   COMPAT_2 (OP_130780 ());
 875 }
 876
 877 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
 878 *v850e
 879 // start-sanitize-v850eq
 880 *v850eq
 881 // end-sanitize-v850eq
 882 "prepare <list12>, <imm5>, <uimm32>"
 883 {
 884   COMPAT_2 (OP_1B0780 ());
 885 }
 886
 887
 888
 889 // end-sanitize-v850e
 890 // RETI
 891 0000011111100000 + 0000000101000000:X:::reti
 892 "reti"
 893 {
 894   if ((PSW & PSW_EP))
 895     {
 896       nia = (EIPC & ~1);
 897       PSW = EIPSW;
 898     }
 899   else if ((PSW & PSW_NP))
 900     {
 901       nia = (FEPC & ~1);
 902       PSW = FEPSW;
 903     }
 904   else
 905     {
 906       nia = (EIPC & ~1);
 907       PSW = EIPSW;
 908     }
 909   TRACE_BRANCH1 (PSW);
 910 }
 911
 912
 913
 914 // SAR
 915 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
 916 "sar r<reg1>, r<reg2>"
 917 {
 918   COMPAT_2 (OP_A007E0 ());
 919 }
 920
 921 rrrrr,010101,iiiii:II:::sar
 922 "sar <imm5>, r<reg2>"
 923 {
 924   COMPAT_1 (OP_2A0 ());
 925 }
 926
 927
 928
 929 // start-sanitize-v850e
 930 // SASF
 931 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
 932 *v850e
 933 // start-sanitize-v850eq
 934 *v850eq
 935 // end-sanitize-v850eq
 936 "sasf <cccc>, r<reg2>"
 937 {
 938   COMPAT_2 (OP_20007E0 ());
 939 }
 940
 941
 942
 943
 944 // end-sanitize-v850e
 945 // SATADD
 946 rrrrr!0,000110,RRRRR:I:::satadd
 947 "satadd r<reg1>, r<reg2>"
 948 {
 949   COMPAT_1 (OP_C0 ());
 950 }
 951
 952 rrrrr!0,010001,iiiii:II:::satadd
 953 "satadd <imm5>, r<reg2>"
 954 {
 955   COMPAT_1 (OP_220 ());
 956 }
 957
 958
 959
 960 // SATSUB
 961 rrrrr!0,000101,RRRRR:I:::satsub
 962 "satsub r<reg1>, r<reg2>"
 963 {
 964   COMPAT_1 (OP_A0 ());
 965 }
 966
 967
 968
 969 // SATSUBI
 970 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
 971 "satsubi <simm16>, r<reg1>, r<reg2>"
 972 {
 973   COMPAT_2 (OP_660 ());
 974 }
 975
 976
 977
 978 // SATSUBR
 979 rrrrr!0,000100,RRRRR:I:::satsubr
 980 "satsubr r<reg1>, r<reg2>"
 981 {
 982   COMPAT_1 (OP_80 ());
 983 }
 984
 985
 986
 987 // SETF
 988 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
 989 "setf <cccc>, r<reg2>"
 990 {
 991   COMPAT_2 (OP_7E0 ());
 992 }
 993
 994
 995
 996 // SET1
 997 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
 998 "set1 <bit3>, <disp16>[r<reg1>]"
 999 {
1000   COMPAT_2 (OP_7C0 ());
1001 }
1002
1003 // start-sanitize-v850e
1004 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
1005 *v850e
1006 // start-sanitize-v850eq
1007 *v850eq
1008 // end-sanitize-v850eq
1009 "set1 r<reg2>, [r<reg1>]"
1010 {
1011   COMPAT_2 (OP_E007E0 ());
1012 }
1013
1014
1015
1016 // end-sanitize-v850e
1017 // SHL
1018 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
1019 "shl r<reg1>, r<reg2>"
1020 {
1021   COMPAT_2 (OP_C007E0 ());
1022 }
1023
1024 rrrrr,010110,iiiii:II:::shl
1025 "shl <imm5>, r<reg2>"
1026 {
1027   COMPAT_1 (OP_2C0 ());
1028 }
1029
1030
1031
1032 // SHR
1033 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
1034 "shr r<reg1>, r<reg2>"
1035 {
1036   COMPAT_2 (OP_8007E0 ());
1037 }
1038
1039 rrrrr,010100,iiiii:II:::shr
1040 "shr <imm5>, r<reg2>"
1041 {
1042   COMPAT_1 (OP_280 ());
1043 }
1044
1045
1046
1047 // SLD
1048 rrrrr,0110,ddddddd:IV:::sld.b
1049 "sld.b <disp7>[ep], r<reg2>"
1050 {
1051   COMPAT_1 (OP_300 ());
1052 }
1053
1054 rrrrr,1000,ddddddd:IV:::sld.h
1055 "sld.h <disp8>[ep], r<reg2>"
1056 {
1057   COMPAT_1 (OP_400 ());
1058 }
1059
1060 rrrrr,1010,dddddd,0:IV:::sld.w
1061 "sld.w <disp8>[ep], r<reg2>"
1062 {
1063   COMPAT_1 (OP_500 ());
1064 }
1065
1066 // start-sanitize-v850e
1067 rrrrr!0,0000110,dddd:IV:::sld.bu
1068 "sld.bu <disp4>[ep], r<reg2>"
1069 {
1070   unsigned long result;
1071
1072   SAVE_1;
1073   result = load_mem (State.regs[30] + disp4, 1);
1074
1075   /* start-sanitize-v850eq */
1076   if (PSW & PSW_US) {
1077     trace_input ("sld.b", OP_LOAD16, 1);
1078
1079     State.regs[ reg2 ] = EXTEND8 (result);
1080   } else {
1081   /* end-sanitize-v850eq */
1082   trace_input ("sld.bu", OP_LOAD16, 1);
1083   State.regs[ reg2 ] = result;
1084   /* start-sanitize-v850eq */
1085   }
1086   /* end-sanitize-v850eq */
1087   trace_output (OP_LOAD16);
1088 }
1089
1090 // end-sanitize-v850e
1091 // start-sanitize-v850e
1092 rrrrr!0,0000111,dddd:IV:::sld.hu
1093 "sld.hu <disp5>[ep], r<reg2>"
1094 {
1095   COMPAT_1 (OP_70 ());
1096 }
1097
1098 // end-sanitize-v850e
1099
1100
1101 // SST
1102 rrrrr,0111,ddddddd:IV:::sst.b
1103 "sst.b r<reg2>, <disp7>[ep]"
1104 {
1105   COMPAT_1 (OP_380 ());
1106 }
1107
1108 rrrrr,1001,ddddddd:IV:::sst.h
1109 "sst.h r<reg2>, <disp8>[ep]"
1110 {
1111   COMPAT_1 (OP_480 ());
1112 }
1113
1114 rrrrr,1010,dddddd,1:IV:::sst.w
1115 "sst.w r<reg2>, <disp8>[ep]"
1116 {
1117   COMPAT_1 (OP_501 ());
1118 }
1119
1120
1121
1122 // ST
1123 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
1124 "st.b r<reg2>, <disp16>[r<reg1>]"
1125 {
1126   COMPAT_2 (OP_740 ());
1127 }
1128
1129 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
1130 "st.h r<reg2>, <disp16>[r<reg1>]"
1131 {
1132   COMPAT_2 (OP_760 ());
1133 }
1134
1135 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1136 "st.w r<reg2>, <disp16>[r<reg1>]"
1137 {
1138   COMPAT_2 (OP_10760 ());
1139 }
1140
1141
1142
1143 // STSR
1144 rrrrr,111111,regID + 0000000001000000:IX:::stsr
1145 "stsr s<regID>, r<reg2>"
1146 {
1147   TRACE_ALU_INPUT1 (SR[regID]);
1148   GR[reg2] = SR[regID];
1149   TRACE_ALU_RESULT (GR[reg2]);
1150 }
1151
1152
1153
1154 // SUB
1155 rrrrr,001101,RRRRR:I:::sub
1156 "sub r<reg1>, r<reg2>"
1157 {
1158   COMPAT_1 (OP_1A0 ());
1159 }
1160
1161
1162
1163 // SUBR
1164 rrrrr,001100,RRRRR:I:::subr
1165 "subr r<reg1>, r<reg2>"
1166 {
1167   COMPAT_1 (OP_180 ());
1168 }
1169
1170
1171
1172 // start-sanitize-v850e
1173 // SWITCH
1174 00000000010,RRRRR:I:::switch
1175 *v850e
1176 // start-sanitize-v850eq
1177 *v850eq
1178 // end-sanitize-v850eq
1179 "switch r<reg1>"
1180 {
1181   unsigned long adr;
1182   SAVE_1;
1183   trace_input ("switch", OP_REG, 0);
1184   adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1185   nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1186   trace_output (OP_REG);
1187 }
1188
1189
1190
1191 // end-sanitize-v850e
1192 // start-sanitize-v850e
1193 // SXB
1194 00000000101,RRRRR:I:::sxb
1195 *v850e
1196 // start-sanitize-v850eq
1197 *v850eq
1198 // end-sanitize-v850eq
1199 "sxb r<reg1>"
1200 {
1201   TRACE_ALU_INPUT1 (GR[reg1]);
1202   GR[reg1] = EXTEND8 (GR[reg1]);
1203   TRACE_ALU_RESULT (GR[reg1]);
1204 }
1205
1206
1207
1208 // end-sanitize-v850e
1209 // start-sanitize-v850e
1210 // SXH
1211 00000000111,RRRRR:I:::sxh
1212 *v850e
1213 // start-sanitize-v850eq
1214 *v850eq
1215 // end-sanitize-v850eq
1216 "sxh r<reg1>"
1217 {
1218   TRACE_ALU_INPUT1 (GR[reg1]);
1219   GR[reg1] = EXTEND16 (GR[reg1]);
1220   TRACE_ALU_RESULT (GR[reg1]);
1221 }
1222
1223
1224
1225 // end-sanitize-v850e
1226 // TRAP
1227 00000111111,iiiii + 0000000100000000:X:::trap
1228 "trap <vector>"
1229 {
1230   COMPAT_2 (OP_10007E0 ());
1231 }
1232
1233
1234
1235 // TST
1236 rrrrr,001011,RRRRR:I:::tst
1237 "tst r<reg1>, r<reg2>"
1238 {
1239   COMPAT_1 (OP_160 ());
1240 }
1241
1242
1243
1244 // TST1
1245 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1246 "tst1 <bit3>, <disp16>[r<reg1>]"
1247 {
1248   COMPAT_2 (OP_C7C0 ());
1249 }
1250
1251 // start-sanitize-v850e
1252 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1253 *v850e
1254 // start-sanitize-v850eq
1255 *v850eq
1256 // end-sanitize-v850eq
1257 "tst1 r<reg2>, [r<reg1>]"
1258 {
1259   COMPAT_2 (OP_E607E0 ());
1260 }
1261
1262
1263
1264 // end-sanitize-v850e
1265 // XOR
1266 rrrrr,001001,RRRRR:I:::xor
1267 "xor r<reg1>, r<reg2>"
1268 {
1269   COMPAT_1 (OP_120 ());
1270 }
1271
1272
1273
1274 // XORI
1275 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1276 "xori <uimm16>, r<reg1>, r<reg2>"
1277 {
1278   COMPAT_2 (OP_6A0 ());
1279 }
1280
1281
1282
1283 // start-sanitize-v850e
1284 // ZXB
1285 00000000100,RRRRR:I:::zxb
1286 *v850e
1287 // start-sanitize-v850eq
1288 *v850eq
1289 // end-sanitize-v850eq
1290 "zxb r<reg1>"
1291 {
1292   TRACE_ALU_INPUT1 (GR[reg1]);
1293   GR[reg1] = GR[reg1] & 0xff;
1294   TRACE_ALU_RESULT (GR[reg1]);
1295 }
1296
1297
1298
1299 // end-sanitize-v850e
1300 // start-sanitize-v850e
1301 // ZXH
1302 00000000110,RRRRR:I:::zxh
1303 *v850e
1304 // start-sanitize-v850eq
1305 *v850eq
1306 // end-sanitize-v850eq
1307 "zxh r<reg1>"
1308 {
1309   TRACE_ALU_INPUT1 (GR[reg1]);
1310   GR[reg1] = GR[reg1] & 0xffff;
1311   TRACE_ALU_RESULT (GR[reg1]);
1312 }
1313
1314
1315
1316 // end-sanitize-v850e
1317 // Special - breakpoint - illegal
1318 // Hopefully, in the future, this instruction will go away
1319 1111111111111111 + 1111111111111111:Z:::breakpoint
1320 *v850
1321 {
1322   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1323 }
1324
1325 // start-sanitize-v850e
1326 // First field could be any nonzero value.
1327 11111,000010,00000:I:::break
1328 {
1329   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1330 }
1331
1332 // end-sanitize-v850e
1333
1334
1335 // start-sanitize-v850eq
1336 // DIVHN
1337 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1338 *v850eq
1339 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1340 {
1341   signed32 quotient;
1342   signed32 remainder;
1343   signed32 divide_by;
1344   signed32 divide_this;
1345   boolean overflow = false;
1346   SAVE_2;
1347
1348   trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1349
1350   divide_by   = EXTEND16 (State.regs[ reg1 ]);
1351   divide_this = State.regs[ reg2 ];
1352
1353   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1354
1355   State.regs[ reg2 ] = quotient;
1356   State.regs[ reg3 ] = remainder;
1357
1358   /* Set condition codes.  */
1359   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1360
1361   if (overflow)      PSW |= PSW_OV;
1362   if (quotient == 0) PSW |= PSW_Z;
1363   if (quotient <  0) PSW |= PSW_S;
1364
1365   trace_output (OP_IMM_REG_REG_REG);
1366 }
1367
1368
1369
1370 // DIVHUN
1371 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1372 *v850eq
1373 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1374 {
1375   signed32 quotient;
1376   signed32 remainder;
1377   signed32 divide_by;
1378   signed32 divide_this;
1379   boolean overflow = false;
1380   SAVE_2;
1381
1382   trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1383
1384   divide_by   = State.regs[ reg1 ] & 0xffff;
1385   divide_this = State.regs[ reg2 ];
1386
1387   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1388
1389   State.regs[ reg2 ] = quotient;
1390   State.regs[ reg3 ] = remainder;
1391
1392   /* Set condition codes.  */
1393   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1394
1395   if (overflow)      PSW |= PSW_OV;
1396   if (quotient == 0) PSW |= PSW_Z;
1397   if (quotient & 0x80000000) PSW |= PSW_S;
1398
1399   trace_output (OP_IMM_REG_REG_REG);
1400 }
1401
1402
1403
1404 // DIVN
1405 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1406 *v850eq
1407 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1408 {
1409   signed32 quotient;
1410   signed32 remainder;
1411   signed32 divide_by;
1412   signed32 divide_this;
1413   boolean overflow = false;
1414   SAVE_2;
1415
1416   trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1417
1418   divide_by   = State.regs[ reg1 ];
1419   divide_this = State.regs[ reg2 ];
1420
1421   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1422
1423   State.regs[ reg2 ] = quotient;
1424   State.regs[ reg3 ] = remainder;
1425
1426   /* Set condition codes.  */
1427   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1428
1429   if (overflow)      PSW |= PSW_OV;
1430   if (quotient == 0) PSW |= PSW_Z;
1431   if (quotient <  0) PSW |= PSW_S;
1432
1433   trace_output (OP_IMM_REG_REG_REG);
1434 }
1435
1436
1437
1438 // DIVUN
1439 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1440 *v850eq
1441 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1442 {
1443   signed32 quotient;
1444   signed32 remainder;
1445   signed32 divide_by;
1446   signed32 divide_this;
1447   boolean overflow = false;
1448   SAVE_2;
1449
1450   trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1451
1452   divide_by   = State.regs[ reg1 ];
1453   divide_this = State.regs[ reg2 ];
1454
1455   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1456
1457   State.regs[ reg2 ] = quotient;
1458   State.regs[ reg3 ] = remainder;
1459
1460   /* Set condition codes.  */
1461   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1462
1463   if (overflow)      PSW |= PSW_OV;
1464   if (quotient == 0) PSW |= PSW_Z;
1465   if (quotient & 0x80000000) PSW |= PSW_S;
1466
1467   trace_output (OP_IMM_REG_REG_REG);
1468 }
1469
1470
1471
1472 // SDIVHN
1473 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1474 *v850eq
1475 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1476 {
1477   COMPAT_2 (OP_18007E0 ());
1478 }
1479
1480
1481
1482 // SDIVHUN
1483 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1484 *v850eq
1485 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1486 {
1487   COMPAT_2 (OP_18207E0 ());
1488 }
1489
1490
1491
1492 // SDIVN
1493 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1494 *v850eq
1495 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1496 {
1497   COMPAT_2 (OP_1C007E0 ());
1498 }
1499
1500
1501
1502 // SDIVUN
1503 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1504 *v850eq
1505 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1506 {
1507   COMPAT_2 (OP_1C207E0 ());
1508 }
1509
1510
1511
1512 // PUSHML
1513 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1514 *v850eq
1515 "pushml <list18>"
1516 {
1517   int i;
1518   SAVE_2;
1519
1520   trace_input ("pushml", OP_PUSHPOP3, 0);
1521
1522   /* Store the registers with lower number registers being placed at
1523      higher addresses.  */
1524
1525   for (i = 0; i < 15; i++)
1526     if ((OP[3] & (1 << type3_regs[ i ])))
1527       {
1528         SP -= 4;
1529         store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1530       }
1531
1532   if (OP[3] & (1 << 3))
1533     {
1534       SP -= 4;
1535
1536       store_mem (SP & ~ 3, 4, PSW);
1537     }
1538
1539   if (OP[3] & (1 << 19))
1540     {
1541       SP -= 8;
1542
1543       if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1544         {
1545           store_mem ((SP + 4) & ~ 3, 4, FEPC);
1546           store_mem ( SP      & ~ 3, 4, FEPSW);
1547         }
1548       else
1549         {
1550           store_mem ((SP + 4) & ~ 3, 4, EIPC);
1551           store_mem ( SP      & ~ 3, 4, EIPSW);
1552         }
1553     }
1554
1555   trace_output (OP_PUSHPOP2);
1556 }
1557
1558
1559
1560 // PUSHHML
1561 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1562 *v850eq
1563 "pushhml <list18>"
1564 {
1565   COMPAT_2 (OP_307E0 ());
1566 }
1567
1568
1569
1570 // POPML
1571 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1572 *v850eq
1573 "popml <list18>"
1574 {
1575   COMPAT_2 (OP_107F0 ());
1576 }
1577
1578
1579
1580 // POPMH
1581 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1582 *v850eq
1583 "popmh <list18>"
1584 {
1585   COMPAT_2 (OP_307F0 ());
1586 }
1587
1588
1589 // end-sanitize-v850eq