sim/v850/v850.igen

   1 :option::insn-bit-size:16
   2 :option::hi-bit-nr:15
   3
   4
   5 :option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
   6 # start-sanitize-v850e
   7 :option::format-names:XI,XII,XIII
   8 # end-sanitize-v850e
   9 # start-sanitize-v850eq
  10 :option::format-names:XIV,XV
  11 # end-sanitize-v850eq
  12 :option::format-names:Z
  13
  14
  15 :model::v850:v850:
  16
  17 # start-sanitize-v850e
  18 :option::multi-sim:true
  19 :model::v850e:v850e:
  20 # end-sanitize-v850e
  21
  22 # start-sanitize-v850eq
  23 :option::multi-sim:true
  24 :model::v850eq:v850eq:
  25 # end-sanitize-v850eq
  26
  27
  28
  29 // Cache macros
  30
  31 :cache::unsigned:reg1:RRRRR:(RRRRR)
  32 :cache::unsigned:reg2:rrrrr:(rrrrr)
  33 :cache::unsigned:reg3:wwwww:(wwwww)
  34
  35 :cache::unsigned:disp4:dddd:(dddd)
  36 # start-sanitize-v850e
  37 :cache::unsigned:disp5:dddd:(dddd << 1)
  38 # end-sanitize-v850e
  39 :cache::unsigned:disp7:ddddddd:ddddddd
  40 :cache::unsigned:disp8:ddddddd:(ddddddd << 1)
  41 :cache::unsigned:disp8:dddddd:(dddddd << 2)
  42 :cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
  43 :cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
  44 :cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
  45 :cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
  46 :cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
  47
  48 :cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
  49 :cache::unsigned:imm6:iiiiii:iiiiii
  50 :cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
  51 # start-sanitize-v850eq
  52 :cache::unsigned:imm5:iiii:(32 - (iiii << 1))
  53 # end-sanitize-v850eq
  54 :cache::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
  55 :cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  56 :cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
  57 # start-sanitize-v850e
  58 :cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
  59 # end-sanitize-v850e
  60
  61 :cache::unsigned:vector:iiiii:iiiii
  62
  63 # start-sanitize-v850e
  64 :cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
  65 :cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
  66 # end-sanitize-v850e
  67
  68 :cache::unsigned:bit3:bbb:bbb
  69
  70
  71 // What do we do with an illegal instruction?
  72 :internal:::illegal
  73 {
  74   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  75                   (unsigned long) cia);
  76   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  77 }
  78
  79
  80
  81 // Add
  82
  83 rrrrr,001110,RRRRR:I:::add
  84 "add r<reg1>, r<reg2>"
  85 {
  86   COMPAT_1 (OP_1C0 ());
  87 }
  88
  89 rrrrr,010010,iiiii:II:::add
  90 "add <imm5>,r<reg2>"
  91 {
  92   COMPAT_1 (OP_240 ());
  93 }
  94
  95
  96
  97 // ADDI
  98 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
  99 "addi <simm16>, r<reg1>, r<reg2>"
 100 {
 101   COMPAT_2 (OP_600 ());
 102 }
 103
 104
 105
 106 // AND
 107 rrrrr,001010,RRRRR:I:::and
 108 "and r<reg1>, r<reg2>"
 109 {
 110   COMPAT_1 (OP_140 ());
 111 }
 112
 113
 114
 115 // ANDI
 116 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
 117 "andi <uimm16>, r<reg1>, r<reg2>"
 118 {
 119   COMPAT_2 (OP_6C0 ());
 120 }
 121
 122
 123
 124 // Bcond
 125 // ddddd,1011,ddd,cccc:III:::Bcond
 126 // "b<cond> disp9"
 127
 128 ddddd,1011,ddd,0000:III:::bv
 129 "bv <disp9>"
 130 {
 131   COMPAT_1 (OP_580 ());
 132 }
 133
 134 ddddd,1011,ddd,0001:III:::bl
 135 "bl <disp9>"
 136 {
 137   COMPAT_1 (OP_581 ());
 138 }
 139
 140 ddddd,1011,ddd,0010:III:::be
 141 "be <disp9>"
 142 {
 143   COMPAT_1 (OP_582 ());
 144 }
 145
 146 ddddd,1011,ddd,0011:III:::bnh
 147 "bnh <disp9>"
 148 {
 149   COMPAT_1 (OP_583 ());
 150 }
 151
 152 ddddd,1011,ddd,0100:III:::bn
 153 "bn <disp9>"
 154 {
 155   COMPAT_1 (OP_584 ());
 156 }
 157
 158 ddddd,1011,ddd,0101:III:::br
 159 "br <disp9>"
 160 {
 161   COMPAT_1 (OP_585 ());
 162 }
 163
 164 ddddd,1011,ddd,0110:III:::blt
 165 "blt <disp9>"
 166 {
 167   COMPAT_1 (OP_586 ());
 168 }
 169
 170 ddddd,1011,ddd,0111:III:::ble
 171 "ble <disp9>"
 172 {
 173   COMPAT_1 (OP_587 ());
 174 }
 175
 176 ddddd,1011,ddd,1000:III:::bnv
 177 "bnv <disp9>"
 178 {
 179   COMPAT_1 (OP_588 ());
 180 }
 181
 182 ddddd,1011,ddd,1001:III:::bnl
 183 "bnl <disp9>"
 184 {
 185   COMPAT_1 (OP_589 ());
 186 }
 187
 188 ddddd,1011,ddd,1010:III:::bne
 189 "bne <disp9>"
 190 {
 191   COMPAT_1 (OP_58A ());
 192 }
 193
 194 ddddd,1011,ddd,1011:III:::bh
 195 "bh <disp9>"
 196 {
 197   COMPAT_1 (OP_58B ());
 198 }
 199
 200 ddddd,1011,ddd,1100:III:::bp
 201 "bp <disp9>"
 202 {
 203   COMPAT_1 (OP_58C ());
 204 }
 205
 206 ddddd,1011,ddd,1101:III:::bsa
 207 "bsa <disp9>"
 208 {
 209   COMPAT_1 (OP_58D ());
 210 }
 211
 212 ddddd,1011,ddd,1110:III:::bge
 213 "bge <disp9>"
 214 {
 215   COMPAT_1 (OP_58E ());
 216 }
 217
 218 ddddd,1011,ddd,1111:III:::bgt
 219 "bgt <disp9>"
 220 {
 221   COMPAT_1 (OP_58F ());
 222 }
 223
 224
 225
 226 // start-sanitize-v850e
 227 // BSH
 228 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 229 *v850e
 230 // start-sanitize-v850eq
 231 *v850eq
 232 // end-sanitize-v850eq
 233 "bsh r<reg2>, r<reg3>"
 234 {
 235   unsigned32 value;
 236   TRACE_ALU_INPUT1 (GR[reg2]);
 237
 238   value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
 239            | MOVED32 (GR[reg2], 31, 24, 23, 16)
 240            | MOVED32 (GR[reg2], 7, 0, 15, 8)
 241            | MOVED32 (GR[reg2], 15, 8, 7, 0));
 242
 243   GR[reg3] = value;
 244   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 245   if (value == 0) PSW |= PSW_Z;
 246   if (value & 0x80000000) PSW |= PSW_S;
 247   if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
 248
 249   TRACE_ALU_RESULT (GR[reg3]);
 250 }
 251
 252
 253
 254 // end-sanitize-v850e
 255 // start-sanitize-v850e
 256 // BSW
 257 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 258 *v850e
 259 // start-sanitize-v850eq
 260 *v850eq
 261 // end-sanitize-v850eq
 262 "bsw r<reg2>, r<reg3>"
 263 {
 264 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
 265   unsigned32 value;
 266   TRACE_ALU_INPUT1 (GR[reg2]);
 267
 268   value = GR[reg2];
 269   value >>= 24;
 270   value |= (GR[reg2] << 24);
 271   value |= ((GR[reg2] << 8) & 0x00ff0000);
 272   value |= ((GR[reg2] >> 8) & 0x0000ff00);
 273   GR[reg3] = value;
 274
 275   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 276
 277   if (value == 0) PSW |= PSW_Z;
 278   if (value & 0x80000000) PSW |= PSW_S;
 279   if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
 280
 281   TRACE_ALU_RESULT (GR[reg3]);
 282 }
 283
 284
 285
 286 // end-sanitize-v850e
 287 // start-sanitize-v850e
 288 // CALLT
 289 0000001000,iiiiii:II:::callt
 290 *v850e
 291 // start-sanitize-v850eq
 292 *v850eq
 293 // end-sanitize-v850eq
 294 "callt <imm6>"
 295 {
 296   unsigned32 adr;
 297   unsigned32 off;
 298   CTPC  = cia + 2;
 299   CTPSW = PSW;
 300   adr = (CTBP & ~1) + (imm6 << 1);
 301   off = load_mem (adr, 2) & ~1; /* Force alignment */
 302   nia = (CTBP & ~1) + off;
 303   TRACE_BRANCH3 (adr, CTBP, off);
 304 }
 305
 306
 307
 308 // end-sanitize-v850e
 309 // CLR1
 310 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
 311 "clr1 <bit3>, <disp16>[r<reg1>]"
 312 {
 313   COMPAT_2 (OP_87C0 ());
 314 }
 315
 316 // start-sanitize-v850e
 317 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 318 *v850e
 319 // start-sanitize-v850eq
 320 *v850eq
 321 // end-sanitize-v850eq
 322 "clr1 r<reg2>, [r<reg1>]"
 323 {
 324   COMPAT_2 (OP_E407E0 ());
 325 }
 326
 327
 328
 329 // end-sanitize-v850e
 330 // start-sanitize-v850e
 331 // CTRET
 332 0000011111100000 + 0000000101000100:X:::ctret
 333 *v850e
 334 // start-sanitize-v850eq
 335 *v850eq
 336 // end-sanitize-v850eq
 337 "ctret"
 338 {
 339   nia  = (CTPC & ~1);
 340   PSW = (CTPSW & (CPU)->psw_mask);
 341   TRACE_BRANCH1 (PSW);
 342 }
 343
 344
 345
 346 // end-sanitize-v850e
 347 // start-sanitize-v850e
 348 // CMOV
 349 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 350 *v850e
 351 // start-sanitize-v850eq
 352 *v850eq
 353 // end-sanitize-v850eq
 354 "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
 355 {
 356   COMPAT_2 (OP_32007E0 ());
 357 }
 358
 359 // end-sanitize-v850e
 360 // start-sanitize-v850e
 361 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 362 *v850e
 363 // start-sanitize-v850eq
 364 *v850eq
 365 // end-sanitize-v850eq
 366 "cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
 367 {
 368   COMPAT_2 (OP_30007E0 ());
 369 }
 370
 371
 372
 373 // end-sanitize-v850e
 374 // CMP
 375 rrrrr,001111,RRRRR:I:::cmp
 376 "cmp r<reg1>, r<reg2>"
 377 {
 378   COMPAT_1 (OP_1E0 ());
 379 }
 380
 381 rrrrr,010011,iiiii:II:::cmp
 382 "cmp <imm5>, r<reg2>"
 383 {
 384   COMPAT_1 (OP_260 ());
 385 }
 386
 387
 388
 389 // DI
 390 0000011111100000 + 0000000101100000:X:::di
 391 "di"
 392 {
 393   COMPAT_2 (OP_16007E0 ());
 394 }
 395
 396
 397
 398 // start-sanitize-v850e
 399 // DISPOSE
 400 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
 401 // "dispose <imm5>, <list12>"
 402 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
 403 *v850e
 404 // start-sanitize-v850eq
 405 *v850eq
 406 // end-sanitize-v850eq
 407 "dispose <imm5>, <list12>":RRRRR == 0
 408 "dispose <imm5>, <list12>, [reg1]"
 409 {
 410   int i;
 411   SAVE_2;
 412
 413   trace_input ("dispose", OP_PUSHPOP1, 0);
 414
 415   SP += (OP[3] & 0x3e) << 1;
 416
 417   /* Load the registers with lower number registers being retrieved
 418      from higher addresses.  */
 419   for (i = 12; i--;)
 420     if ((OP[3] & (1 << type1_regs[ i ])))
 421       {
 422         State.regs[ 20 + i ] = load_mem (SP, 4);
 423         SP += 4;
 424       }
 425
 426   if ((OP[3] & 0x1f0000) != 0)
 427     {
 428       nia = State.regs[ (OP[3] >> 16) & 0x1f];
 429     }
 430
 431   trace_output (OP_PUSHPOP1);
 432 }
 433
 434
 435
 436 // end-sanitize-v850e
 437 // start-sanitize-v850e
 438 // DIV
 439 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 440 *v850e
 441 "div r<reg1>, r<reg2>, r<reg3>"
 442 {
 443   COMPAT_2 (OP_2C007E0 ());
 444 }
 445
 446
 447
 448
 449 // end-sanitize-v850e
 450 // DIVH
 451 rrrrr!0,000010,RRRRR!0:I:::divh
 452 "divh r<reg1>, r<reg2>"
 453 {
 454   COMPAT_1 (OP_40 ());
 455 }
 456
 457 // start-sanitize-v850e
 458 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 459 *v850e
 460 "divh r<reg1>, r<reg2>, r<reg3>"
 461 {
 462   COMPAT_2 (OP_28007E0 ());
 463 }
 464
 465
 466
 467 // end-sanitize-v850e
 468 // start-sanitize-v850e
 469 // DIVHU
 470 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 471 *v850e
 472 "divhu r<reg1>, r<reg2>, r<reg3>"
 473 {
 474   COMPAT_2 (OP_28207E0 ());
 475 }
 476
 477
 478
 479 // end-sanitize-v850e
 480 // start-sanitize-v850e
 481 // DIVU
 482 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 483 *v850e
 484 "divu r<reg1>, r<reg2>, r<reg3>"
 485 {
 486   COMPAT_2 (OP_2C207E0 ());
 487 }
 488
 489
 490
 491 // end-sanitize-v850e
 492 // EI
 493 1000011111100000 + 0000000101100000:X:::ei
 494 "ei"
 495 {
 496   COMPAT_2 (OP_16087E0 ());
 497 }
 498
 499
 500
 501 // HALT
 502 0000011111100000 + 0000000100100000:X:::halt
 503 "halt"
 504 {
 505   COMPAT_2 (OP_12007E0 ());
 506 }
 507
 508
 509
 510 // start-sanitize-v850e
 511 // HSW
 512 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 513 *v850e
 514 // start-sanitize-v850eq
 515 *v850eq
 516 // end-sanitize-v850eq
 517 "hsw r<reg2>, r<reg3>"
 518 {
 519   unsigned32 value;
 520   TRACE_ALU_INPUT1 (GR[reg2]);
 521
 522   value = GR[reg2];
 523   value >>= 16;
 524   value |= (GR[reg2] << 16);
 525
 526   GR[reg3] = value;
 527
 528   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 529
 530   if (value == 0) PSW |= PSW_Z;
 531   if (value & 0x80000000) PSW |= PSW_S;
 532   if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
 533
 534   TRACE_ALU_RESULT (GR[reg3]);
 535 }
 536
 537
 538
 539 // end-sanitize-v850e
 540 // JARL
 541 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 542 "jarl <disp22>, r<reg2>"
 543 {
 544   COMPAT_2 (OP_780 ());
 545 }
 546
 547
 548
 549 // JMP
 550 00000000011,RRRRR:I:::jmp
 551 "jmp [r<reg1>]"
 552 {
 553   SAVE_1;
 554   trace_input ("jmp", OP_REG, 0);
 555   nia = State.regs[ reg1 ];
 556   trace_output (OP_REG);
 557 }
 558
 559
 560
 561 // JR
 562 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 563 "jr <disp22>"
 564 {
 565   COMPAT_2 (OP_780 ());
 566 }
 567
 568
 569
 570 // LD
 571 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 572 "ld.b <disp16>[r<reg1>, r<reg2>"
 573 {
 574   COMPAT_2 (OP_700 ());
 575 }
 576
 577 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 578 "ld.h <disp16>[r<reg1>], r<reg2>"
 579 {
 580   COMPAT_2 (OP_720 ());
 581 }
 582
 583 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 584 "ld.w <disp16>[r<reg1>], r<reg2>"
 585 {
 586   COMPAT_2 (OP_10720 ());
 587 }
 588
 589 // start-sanitize-v850e
 590 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 591 *v850e
 592 // start-sanitize-v850eq
 593 *v850eq
 594 // end-sanitize-v850eq
 595 "ld.bu <disp16>[r<reg1>], r<reg2>"
 596 {
 597   COMPAT_2 (OP_10780 ());
 598 }
 599
 600 // end-sanitize-v850e
 601 // start-sanitize-v850e
 602 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 603 *v850e
 604 // start-sanitize-v850eq
 605 *v850eq
 606 // end-sanitize-v850eq
 607 "ld.hu <disp16>[r<reg1>], r<reg2>"
 608 {
 609   COMPAT_2 (OP_107E0 ());
 610 }
 611
 612
 613 // end-sanitize-v850e
 614 // LDSR
 615 regID,111111,RRRRR + 0000000000100000:IX:::ldsr
 616 "ldsr r<reg1>, s<regID>"
 617 {
 618   TRACE_ALU_INPUT1 (GR[reg1]);
 619
 620   if (&PSW == &SR[regID])
 621     PSW = (GR[reg1] & (CPU)->psw_mask);
 622   else
 623     SR[regID] = GR[reg1];
 624
 625   TRACE_ALU_RESULT (SR[regID]);
 626 }
 627
 628
 629
 630 // MOV
 631 rrrrr!0,000000,RRRRR:I:::mov
 632 "mov r<reg1>, r<reg2>"
 633 {
 634   COMPAT_1 (OP_0 ());
 635 }
 636
 637 rrrrr!0,010000,iiiii:II:::mov
 638 "mov <imm5>, r<reg2>"
 639 {
 640   COMPAT_1 (OP_200 ());
 641 }
 642
 643 // start-sanitize-v850e
 644 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
 645 *v850e
 646 // start-sanitize-v850eq
 647 *v850eq
 648 // end-sanitize-v850eq
 649 "mov <imm32>, r<reg1>"
 650 {
 651   SAVE_2;
 652   trace_input ("mov", OP_IMM_REG, 4);
 653   State.regs[ OP[0] ] = load_mem (PC + 2, 4);
 654   trace_output (OP_IMM_REG);
 655 }
 656
 657
 658
 659 // end-sanitize-v850e
 660 // MOVEA
 661 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
 662 "movea <simm16>, r<reg1>, r<reg2>"
 663 {
 664   TRACE_ALU_INPUT2 (GR[reg1], simm16);
 665   GR[reg2] = GR[reg1] + simm16;
 666   TRACE_ALU_RESULT (GR[reg2]);
 667 }
 668
 669
 670
 671 // MOVHI
 672 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
 673 "movhi <uimm16>, r<reg1>, r<reg2>"
 674 {
 675   COMPAT_2 (OP_640 ());
 676 }
 677
 678
 679
 680 // start-sanitize-v850e
 681 // MUL
 682 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 683 *v850e
 684 // start-sanitize-v850eq
 685 *v850eq
 686 // end-sanitize-v850eq
 687 "mul r<reg1>, r<reg2>, r<reg3>"
 688 {
 689   COMPAT_2 (OP_22007E0 ());
 690 }
 691
 692 // end-sanitize-v850e
 693 // start-sanitize-v850e
 694 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 695 *v850e
 696 // start-sanitize-v850eq
 697 *v850eq
 698 // end-sanitize-v850eq
 699 "mul <imm9>, r<reg2>, r<reg3>"
 700 {
 701   COMPAT_2 (OP_24007E0 ());
 702 }
 703
 704
 705
 706 // end-sanitize-v850e
 707 // MULH
 708 rrrrr!0,000111,RRRRR:I:::mulh
 709 "mulh r<reg1>, r<reg2>"
 710 {
 711   COMPAT_1 (OP_E0 ());
 712 }
 713
 714 rrrrr!0,010111,iiiii:II:::mulh
 715 "mulh <imm5>, r<reg2>"
 716 {
 717   COMPAT_1 (OP_2E0 ());
 718 }
 719
 720
 721
 722 // MULHI
 723 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
 724 "mulhi <uimm16>, r<reg1>, r<reg2>"
 725 {
 726   COMPAT_2 (OP_6E0 ());
 727 }
 728
 729
 730
 731 // start-sanitize-v850e
 732 // MULU
 733 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 734 *v850e
 735 // start-sanitize-v850eq
 736 *v850eq
 737 // end-sanitize-v850eq
 738 "mulu r<reg1>, r<reg2>, r<reg3>"
 739 {
 740   COMPAT_2 (OP_22207E0 ());
 741 }
 742
 743 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 744 *v850e
 745 // start-sanitize-v850eq
 746 *v850eq
 747 // end-sanitize-v850eq
 748 "mulu <imm9>, r<reg2>, r<reg3>"
 749 {
 750   COMPAT_2 (OP_24207E0 ());
 751 }
 752
 753
 754
 755 // end-sanitize-v850e
 756 // NOP
 757 0000000000000000:I:::nop
 758 "nop"
 759 {
 760   COMPAT_1 (OP_0 ());
 761 }
 762
 763
 764
 765 // NOT
 766 rrrrr,000001,RRRRR:I:::not
 767 "not r<reg1>, r<reg2>"
 768 {
 769   COMPAT_1 (OP_20 ());
 770 }
 771
 772
 773
 774 // NOT1
 775 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
 776 "not1 <bit3>, <disp16>[r<reg1>]"
 777 {
 778   COMPAT_2 (OP_47C0 ());
 779 }
 780
 781 // start-sanitize-v850e
 782 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 783 *v850e
 784 // start-sanitize-v850eq
 785 *v850eq
 786 // end-sanitize-v850eq
 787 "not1 r<reg2>, r<reg1>"
 788 {
 789   COMPAT_2 (OP_E207E0 ());
 790 }
 791
 792
 793
 794 // end-sanitize-v850e
 795 // OR
 796 rrrrr,001000,RRRRR:I:::or
 797 "or r<reg1>, r<reg2>"
 798 {
 799   COMPAT_1 (OP_100 ());
 800 }
 801
 802
 803
 804 // ORI
 805 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 806 "ori <uimm16>, r<reg1>, r<reg2>"
 807 {
 808   COMPAT_2 (OP_680 ());
 809 }
 810
 811
 812
 813 // start-sanitize-v850e
 814 // PREPARE
 815 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
 816 *v850e
 817 // start-sanitize-v850eq
 818 *v850eq
 819 // end-sanitize-v850eq
 820 "prepare <list12>, <imm5>"
 821 {
 822   int  i;
 823   SAVE_2;
 824
 825   trace_input ("prepare", OP_PUSHPOP1, 0);
 826
 827   /* Store the registers with lower number registers being placed at
 828      higher addresses.  */
 829   for (i = 0; i < 12; i++)
 830     if ((OP[3] & (1 << type1_regs[ i ])))
 831       {
 832         SP -= 4;
 833         store_mem (SP, 4, State.regs[ 20 + i ]);
 834       }
 835
 836   SP -= (OP[3] & 0x3e) << 1;
 837
 838   trace_output (OP_PUSHPOP1);
 839 }
 840
 841
 842 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
 843 *v850e
 844 // start-sanitize-v850eq
 845 *v850eq
 846 // end-sanitize-v850eq
 847 "prepare <list12>, <imm5>, sp"
 848 {
 849   COMPAT_2 (OP_30780 ());
 850 }
 851
 852 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
 853 *v850e
 854 // start-sanitize-v850eq
 855 *v850eq
 856 // end-sanitize-v850eq
 857 "prepare <list12>, <imm5>, <uimm16>"
 858 {
 859   COMPAT_2 (OP_B0780 ());
 860 }
 861
 862 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
 863 *v850e
 864 // start-sanitize-v850eq
 865 *v850eq
 866 // end-sanitize-v850eq
 867 "prepare <list12>, <imm5>, <uimm16>"
 868 {
 869   COMPAT_2 (OP_130780 ());
 870 }
 871
 872 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
 873 *v850e
 874 // start-sanitize-v850eq
 875 *v850eq
 876 // end-sanitize-v850eq
 877 "prepare <list12>, <imm5>, <uimm32>"
 878 {
 879   COMPAT_2 (OP_1B0780 ());
 880 }
 881
 882
 883
 884 // end-sanitize-v850e
 885 // RETI
 886 0000011111100000 + 0000000101000000:X:::reti
 887 "reti"
 888 {
 889   COMPAT_2 (OP_14007E0 ());
 890 }
 891
 892
 893
 894 // SAR
 895 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
 896 "sar r<reg1>, r<reg2>"
 897 {
 898   COMPAT_2 (OP_A007E0 ());
 899 }
 900
 901 rrrrr,010101,iiiii:II:::sar
 902 "sar <imm5>, r<reg2>"
 903 {
 904   COMPAT_1 (OP_2A0 ());
 905 }
 906
 907
 908
 909 // start-sanitize-v850e
 910 // SASF
 911 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
 912 *v850e
 913 // start-sanitize-v850eq
 914 *v850eq
 915 // end-sanitize-v850eq
 916 "sasf <cccc>, r<reg2>"
 917 {
 918   COMPAT_2 (OP_20007E0 ());
 919 }
 920
 921
 922
 923
 924 // end-sanitize-v850e
 925 // SATADD
 926 rrrrr!0,000110,RRRRR:I:::satadd
 927 "satadd r<reg1>, r<reg2>"
 928 {
 929   COMPAT_1 (OP_C0 ());
 930 }
 931
 932 rrrrr!0,010001,iiiii:II:::satadd
 933 "satadd <imm5>, r<reg2>"
 934 {
 935   COMPAT_1 (OP_220 ());
 936 }
 937
 938
 939
 940 // SATSUB
 941 rrrrr!0,000101,RRRRR:I:::satsub
 942 "satsub r<reg1>, r<reg2>"
 943 {
 944   COMPAT_1 (OP_A0 ());
 945 }
 946
 947
 948
 949 // SATSUBI
 950 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
 951 "satsubi <simm16>, r<reg1>, r<reg2>"
 952 {
 953   COMPAT_2 (OP_660 ());
 954 }
 955
 956
 957
 958 // SATSUBR
 959 rrrrr!0,000100,RRRRR:I:::satsubr
 960 "satsubr r<reg1>, r<reg2>"
 961 {
 962   COMPAT_1 (OP_80 ());
 963 }
 964
 965
 966
 967 // SETF
 968 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
 969 "setf <cccc>, r<reg2>"
 970 {
 971   COMPAT_2 (OP_7E0 ());
 972 }
 973
 974
 975
 976 // SET1
 977 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
 978 "set1 <bit3>, <disp16>[r<reg1>]"
 979 {
 980   COMPAT_2 (OP_7C0 ());
 981 }
 982
 983 // start-sanitize-v850e
 984 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
 985 *v850e
 986 // start-sanitize-v850eq
 987 *v850eq
 988 // end-sanitize-v850eq
 989 "set1 r<reg2>, [r<reg1>]"
 990 {
 991   COMPAT_2 (OP_E007E0 ());
 992 }
 993
 994
 995
 996 // end-sanitize-v850e
 997 // SHL
 998 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
 999 "shl r<reg1>, r<reg2>"
1000 {
1001   COMPAT_2 (OP_C007E0 ());
1002 }
1003
1004 rrrrr,010110,iiiii:II:::shl
1005 "shl <imm5>, r<reg2>"
1006 {
1007   COMPAT_1 (OP_2C0 ());
1008 }
1009
1010
1011
1012 // SHR
1013 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
1014 "shr r<reg1>, r<reg2>"
1015 {
1016   COMPAT_2 (OP_8007E0 ());
1017 }
1018
1019 rrrrr,010100,iiiii:II:::shr
1020 "shr <imm5>, r<reg2>"
1021 {
1022   COMPAT_1 (OP_280 ());
1023 }
1024
1025
1026
1027 // SLD
1028 rrrrr,0110,ddddddd:IV:::sld.b
1029 "sld.b <disp7>[ep], r<reg2>"
1030 {
1031   COMPAT_1 (OP_300 ());
1032 }
1033
1034 rrrrr,1000,ddddddd:IV:::sld.h
1035 "sld.h <disp8>[ep], r<reg2>"
1036 {
1037   COMPAT_1 (OP_400 ());
1038 }
1039
1040 rrrrr,1010,dddddd,0:IV:::sld.w
1041 "sld.w <disp8>[ep], r<reg2>"
1042 {
1043   COMPAT_1 (OP_500 ());
1044 }
1045
1046 // start-sanitize-v850e
1047 rrrrr!0,0000110,dddd:IV:::sld.bu
1048 "sld.bu <disp4>[ep], r<reg2>"
1049 {
1050   unsigned long result;
1051
1052   SAVE_1;
1053   result = load_mem (State.regs[30] + disp4, 1);
1054
1055   /* start-sanitize-v850eq */
1056   if (PSW & PSW_US) {
1057     trace_input ("sld.b", OP_LOAD16, 1);
1058
1059     State.regs[ reg2 ] = EXTEND8 (result);
1060   } else {
1061   /* end-sanitize-v850eq */
1062   trace_input ("sld.bu", OP_LOAD16, 1);
1063   State.regs[ reg2 ] = result;
1064   /* start-sanitize-v850eq */
1065   }
1066   /* end-sanitize-v850eq */
1067   trace_output (OP_LOAD16);
1068 }
1069
1070 // end-sanitize-v850e
1071 // start-sanitize-v850e
1072 rrrrr!0,0000111,dddd:IV:::sld.hu
1073 "sld.hu <disp5>[ep], r<reg2>"
1074 {
1075   COMPAT_1 (OP_70 ());
1076 }
1077
1078 // end-sanitize-v850e
1079
1080
1081 // SST
1082 rrrrr,0111,ddddddd:IV:::sst.b
1083 "sst.b r<reg2>, <disp7>[ep]"
1084 {
1085   COMPAT_1 (OP_380 ());
1086 }
1087
1088 rrrrr,1001,ddddddd:IV:::sst.h
1089 "sst.h r<reg2>, <disp8>[ep]"
1090 {
1091   COMPAT_1 (OP_480 ());
1092 }
1093
1094 rrrrr,1010,dddddd,1:IV:::sst.w
1095 "sst.w r<reg2>, <disp8>[ep]"
1096 {
1097   COMPAT_1 (OP_501 ());
1098 }
1099
1100
1101
1102 // ST
1103 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
1104 "st.b r<reg2>, <disp16>[r<reg1>]"
1105 {
1106   COMPAT_2 (OP_740 ());
1107 }
1108
1109 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
1110 "st.h r<reg2>, <disp16>[r<reg1>]"
1111 {
1112   COMPAT_2 (OP_760 ());
1113 }
1114
1115 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1116 "st.w r<reg2>, <disp16>[r<reg1>]"
1117 {
1118   COMPAT_2 (OP_10760 ());
1119 }
1120
1121
1122
1123 // STSR
1124 rrrrr,111111,regID + 0000000001000000:IX:::stsr
1125 "stsr s<regID>, r<reg2>"
1126 {
1127   TRACE_ALU_INPUT1 (SR[regID]);
1128   GR[reg2] = SR[regID];
1129   TRACE_ALU_RESULT (GR[reg2]);
1130 }
1131
1132
1133
1134 // SUB
1135 rrrrr,001101,RRRRR:I:::sub
1136 "sub r<reg1>, r<reg2>"
1137 {
1138   COMPAT_1 (OP_1A0 ());
1139 }
1140
1141
1142
1143 // SUBR
1144 rrrrr,001100,RRRRR:I:::subr
1145 "subr r<reg1>, r<reg2>"
1146 {
1147   COMPAT_1 (OP_180 ());
1148 }
1149
1150
1151
1152 // start-sanitize-v850e
1153 // SWITCH
1154 00000000010,RRRRR:I:::switch
1155 *v850e
1156 // start-sanitize-v850eq
1157 *v850eq
1158 // end-sanitize-v850eq
1159 "switch r<reg1>"
1160 {
1161   unsigned long adr;
1162   SAVE_1;
1163   trace_input ("switch", OP_REG, 0);
1164   adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1165   nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1166   trace_output (OP_REG);
1167 }
1168
1169
1170
1171 // end-sanitize-v850e
1172 // start-sanitize-v850e
1173 // SXB
1174 00000000101,RRRRR:I:::sxb
1175 *v850e
1176 // start-sanitize-v850eq
1177 *v850eq
1178 // end-sanitize-v850eq
1179 "sxb r<reg1>"
1180 {
1181   TRACE_ALU_INPUT1 (GR[reg1]);
1182   GR[reg1] = EXTEND8 (GR[reg1]);
1183   TRACE_ALU_RESULT (GR[reg1]);
1184 }
1185
1186
1187
1188 // end-sanitize-v850e
1189 // start-sanitize-v850e
1190 // SXH
1191 00000000111,RRRRR:I:::sxh
1192 *v850e
1193 // start-sanitize-v850eq
1194 *v850eq
1195 // end-sanitize-v850eq
1196 "sxh r<reg1>"
1197 {
1198   TRACE_ALU_INPUT1 (GR[reg1]);
1199   GR[reg1] = EXTEND16 (GR[reg1]);
1200   TRACE_ALU_RESULT (GR[reg1]);
1201 }
1202
1203
1204
1205 // end-sanitize-v850e
1206 // TRAP
1207 00000111111,iiiii + 0000000100000000:X:::trap
1208 "trap <vector>"
1209 {
1210   COMPAT_2 (OP_10007E0 ());
1211 }
1212
1213
1214
1215 // TST
1216 rrrrr,001011,RRRRR:I:::tst
1217 "tst r<reg1>, r<reg2>"
1218 {
1219   COMPAT_1 (OP_160 ());
1220 }
1221
1222
1223
1224 // TST1
1225 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1226 "tst1 <bit3>, <disp16>[r<reg1>]"
1227 {
1228   COMPAT_2 (OP_C7C0 ());
1229 }
1230
1231 // start-sanitize-v850e
1232 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1233 *v850e
1234 // start-sanitize-v850eq
1235 *v850eq
1236 // end-sanitize-v850eq
1237 "tst1 r<reg2>, [r<reg1>]"
1238 {
1239   COMPAT_2 (OP_E607E0 ());
1240 }
1241
1242
1243
1244 // end-sanitize-v850e
1245 // XOR
1246 rrrrr,001001,RRRRR:I:::xor
1247 "xor r<reg1>, r<reg2>"
1248 {
1249   COMPAT_1 (OP_120 ());
1250 }
1251
1252
1253
1254 // XORI
1255 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1256 "xori <uimm16>, r<reg1>, r<reg2>"
1257 {
1258   COMPAT_2 (OP_6A0 ());
1259 }
1260
1261
1262
1263 // start-sanitize-v850e
1264 // ZXB
1265 00000000100,RRRRR:I:::zxb
1266 *v850e
1267 // start-sanitize-v850eq
1268 *v850eq
1269 // end-sanitize-v850eq
1270 "zxb r<reg1>"
1271 {
1272   TRACE_ALU_INPUT1 (GR[reg1]);
1273   GR[reg1] = GR[reg1] & 0xff;
1274   TRACE_ALU_RESULT (GR[reg1]);
1275 }
1276
1277
1278
1279 // end-sanitize-v850e
1280 // start-sanitize-v850e
1281 // ZXH
1282 00000000110,RRRRR:I:::zxh
1283 *v850e
1284 // start-sanitize-v850eq
1285 *v850eq
1286 // end-sanitize-v850eq
1287 "zxh r<reg1>"
1288 {
1289   TRACE_ALU_INPUT1 (GR[reg1]);
1290   GR[reg1] = GR[reg1] & 0xffff;
1291   TRACE_ALU_RESULT (GR[reg1]);
1292 }
1293
1294
1295
1296 // end-sanitize-v850e
1297 // Special - breakpoint - illegal
1298 // Hopefully, in the future, this instruction will go away
1299 1111111111111111 + 1111111111111111:Z:::breakpoint
1300 *v850
1301 {
1302   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1303 }
1304
1305 // start-sanitize-v850e
1306 // First field could be any nonzero value.
1307 11111,000010,00000:I:::break
1308 {
1309   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1310 }
1311
1312 // end-sanitize-v850e
1313
1314
1315 // start-sanitize-v850eq
1316 // DIVHN
1317 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1318 *v850eq
1319 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1320 {
1321   signed32 quotient;
1322   signed32 remainder;
1323   signed32 divide_by;
1324   signed32 divide_this;
1325   boolean overflow = false;
1326   SAVE_2;
1327
1328   trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1329
1330   divide_by   = EXTEND16 (State.regs[ reg1 ]);
1331   divide_this = State.regs[ reg2 ];
1332
1333   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1334
1335   State.regs[ reg2 ] = quotient;
1336   State.regs[ reg3 ] = remainder;
1337
1338   /* Set condition codes.  */
1339   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1340
1341   if (overflow)      PSW |= PSW_OV;
1342   if (quotient == 0) PSW |= PSW_Z;
1343   if (quotient <  0) PSW |= PSW_S;
1344
1345   trace_output (OP_IMM_REG_REG_REG);
1346 }
1347
1348
1349
1350 // DIVHUN
1351 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1352 *v850eq
1353 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1354 {
1355   signed32 quotient;
1356   signed32 remainder;
1357   signed32 divide_by;
1358   signed32 divide_this;
1359   boolean overflow = false;
1360   SAVE_2;
1361
1362   trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1363
1364   divide_by   = State.regs[ reg1 ] & 0xffff;
1365   divide_this = State.regs[ reg2 ];
1366
1367   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1368
1369   State.regs[ reg2 ] = quotient;
1370   State.regs[ reg3 ] = remainder;
1371
1372   /* Set condition codes.  */
1373   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1374
1375   if (overflow)      PSW |= PSW_OV;
1376   if (quotient == 0) PSW |= PSW_Z;
1377   if (quotient & 0x80000000) PSW |= PSW_S;
1378
1379   trace_output (OP_IMM_REG_REG_REG);
1380 }
1381
1382
1383
1384 // DIVN
1385 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1386 *v850eq
1387 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1388 {
1389   signed32 quotient;
1390   signed32 remainder;
1391   signed32 divide_by;
1392   signed32 divide_this;
1393   boolean overflow = false;
1394   SAVE_2;
1395
1396   trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1397
1398   divide_by   = State.regs[ reg1 ];
1399   divide_this = State.regs[ reg2 ];
1400
1401   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1402
1403   State.regs[ reg2 ] = quotient;
1404   State.regs[ reg3 ] = remainder;
1405
1406   /* Set condition codes.  */
1407   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1408
1409   if (overflow)      PSW |= PSW_OV;
1410   if (quotient == 0) PSW |= PSW_Z;
1411   if (quotient <  0) PSW |= PSW_S;
1412
1413   trace_output (OP_IMM_REG_REG_REG);
1414 }
1415
1416
1417
1418 // DIVUN
1419 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1420 *v850eq
1421 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1422 {
1423   signed32 quotient;
1424   signed32 remainder;
1425   signed32 divide_by;
1426   signed32 divide_this;
1427   boolean overflow = false;
1428   SAVE_2;
1429
1430   trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1431
1432   divide_by   = State.regs[ reg1 ];
1433   divide_this = State.regs[ reg2 ];
1434
1435   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1436
1437   State.regs[ reg2 ] = quotient;
1438   State.regs[ reg3 ] = remainder;
1439
1440   /* Set condition codes.  */
1441   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1442
1443   if (overflow)      PSW |= PSW_OV;
1444   if (quotient == 0) PSW |= PSW_Z;
1445   if (quotient & 0x80000000) PSW |= PSW_S;
1446
1447   trace_output (OP_IMM_REG_REG_REG);
1448 }
1449
1450
1451
1452 // SDIVHN
1453 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1454 *v850eq
1455 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1456 {
1457   COMPAT_2 (OP_18007E0 ());
1458 }
1459
1460
1461
1462 // SDIVHUN
1463 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1464 *v850eq
1465 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1466 {
1467   COMPAT_2 (OP_18207E0 ());
1468 }
1469
1470
1471
1472 // SDIVN
1473 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1474 *v850eq
1475 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1476 {
1477   COMPAT_2 (OP_1C007E0 ());
1478 }
1479
1480
1481
1482 // SDIVUN
1483 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1484 *v850eq
1485 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1486 {
1487   COMPAT_2 (OP_1C207E0 ());
1488 }
1489
1490
1491
1492 // PUSHML
1493 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1494 *v850eq
1495 "pushml <list18>"
1496 {
1497   int i;
1498   SAVE_2;
1499
1500   trace_input ("pushml", OP_PUSHPOP3, 0);
1501
1502   /* Store the registers with lower number registers being placed at
1503      higher addresses.  */
1504
1505   for (i = 0; i < 15; i++)
1506     if ((OP[3] & (1 << type3_regs[ i ])))
1507       {
1508         SP -= 4;
1509         store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1510       }
1511
1512   if (OP[3] & (1 << 3))
1513     {
1514       SP -= 4;
1515
1516       store_mem (SP & ~ 3, 4, PSW);
1517     }
1518
1519   if (OP[3] & (1 << 19))
1520     {
1521       SP -= 8;
1522
1523       if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1524         {
1525           store_mem ((SP + 4) & ~ 3, 4, FEPC);
1526           store_mem ( SP      & ~ 3, 4, FEPSW);
1527         }
1528       else
1529         {
1530           store_mem ((SP + 4) & ~ 3, 4, EIPC);
1531           store_mem ( SP      & ~ 3, 4, EIPSW);
1532         }
1533     }
1534
1535   trace_output (OP_PUSHPOP2);
1536 }
1537
1538
1539
1540 // PUSHHML
1541 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1542 *v850eq
1543 "pushhml <list18>"
1544 {
1545   COMPAT_2 (OP_307E0 ());
1546 }
1547
1548
1549
1550 // POPML
1551 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1552 *v850eq
1553 "popml <list18>"
1554 {
1555   COMPAT_2 (OP_107F0 ());
1556 }
1557
1558
1559
1560 // POPMH
1561 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1562 *v850eq
1563 "popmh <list18>"
1564 {
1565   COMPAT_2 (OP_307F0 ());
1566 }
1567
1568
1569 // end-sanitize-v850eq