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* interp.c (sim_open): Add support for bfd_arch_v850_rh850
[binutils-gdb.git] / sim / v850 / v850.igen
1 :option:::insn-bit-size:16
2 :option:::hi-bit-nr:15
3
4
5 :option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
6 :option:::format-names:XI,XII,XIII
7 :option:::format-names:XIV,XV
8 :option:::format-names:Z
9 :option:::format-names:F_I
10
11
12 :model:::v850:v850:
13
14 :option:::multi-sim:true
15 :model:::v850e:v850e:
16 :option:::multi-sim:true
17 :model:::v850e1:v850e1:
18 :option:::multi-sim:true
19 :model:::v850e2:v850e2:
20 :option:::multi-sim:true
21 :model:::v850e2v3:v850e2v3:
22
23 // Cache macros
24
25 :cache:::unsigned:reg1:RRRRR:(RRRRR)
26 :cache:::unsigned:reg2:rrrrr:(rrrrr)
27 :cache:::unsigned:reg3:wwwww:(wwwww)
28 :cache:::unsigned:reg4:W,WWWW:(W + (WWWW << 1))
29
30 :cache:::unsigned:reg1e:RRRR:(RRRR << 1)
31 :cache:::unsigned:reg2e:rrrr:(rrrr << 1)
32 :cache:::unsigned:reg3e:wwww:(wwww << 1)
33 :cache:::unsigned:reg4e:mmmm:(mmmm << 1)
34
35 :cache:::unsigned:disp4:dddd:(dddd)
36 :cache:::unsigned:disp5:dddd:(dddd << 1)
37 :cache:::unsigned:disp7:ddddddd:ddddddd
38 :cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
39 :cache:::unsigned:disp8:dddddd:(dddddd << 2)
40 :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
41 :cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
42 :cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
43 :cache:::unsigned:disp17:d,ddddddddddddddd:SEXT32 (((d <<16) + (ddddddddddddddd << 1)), 17 - 1)
44 :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
45 :cache:::unsigned:disp23:ddddddd,dddddddddddddddd: SEXT32 ((ddddddd) + (dddddddddddddddd << 7), 23 - 1)
46 :cache:::unsigned:disp23:dddddd,dddddddddddddddd: SEXT32 ((dddddd << 1) + (dddddddddddddddd << 7), 23 - 1)
47
48 :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
49 :cache:::unsigned:imm6:iiiiii:iiiiii
50 :cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
51 :cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
52 :cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
53 :cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
54 :cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
55 :cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
56
57 :cache:::unsigned:vector:iiiii:iiiii
58
59 :cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
60 :cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
61
62 :cache:::unsigned:bit3:bbb:bbb
63 :cache:::unsigned:bit4:bbbb:bbbb
64
65
66 // What do we do with an illegal instruction?
67 :internal::::illegal:
68 {
69 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
70 (unsigned long) cia);
71 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
72 }
73
74
75
76 // ADD
77 rrrrr,001110,RRRRR:I:::add
78 "add r<reg1>, r<reg2>"
79 {
80 COMPAT_1 (OP_1C0 ());
81 }
82
83 rrrrr,010010,iiiii:II:::add
84 "add <imm5>,r<reg2>"
85 {
86 COMPAT_1 (OP_240 ());
87 }
88
89
90
91 // ADDI
92 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
93 "addi <simm16>, r<reg1>, r<reg2>"
94 {
95 COMPAT_2 (OP_600 ());
96 }
97
98
99
100 // ADF
101 rrrrr,111111,RRRRR + wwwww,011101,cccc!13,0:XI:::adf
102 *v850e2
103 *v850e2v3
104 "adf %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
105 {
106 int cond = condition_met (cccc);
107 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
108 GR[reg3] = GR[reg1] + GR[reg2] + (cond ? 1 : 0);
109 TRACE_ALU_RESULT1 (GR[reg3]);
110 }
111
112
113
114 // AND
115 rrrrr,001010,RRRRR:I:::and
116 "and r<reg1>, r<reg2>"
117 {
118 COMPAT_1 (OP_140 ());
119 }
120
121
122
123 // ANDI
124 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
125 "andi <uimm16>, r<reg1>, r<reg2>"
126 {
127 COMPAT_2 (OP_6C0 ());
128 }
129
130
131
132 // Map condition code to a string
133 :%s::::cccc:int cccc
134 {
135 switch (cccc)
136 {
137 case 0xf: return "gt";
138 case 0xe: return "ge";
139 case 0x6: return "lt";
140
141 case 0x7: return "le";
142
143 case 0xb: return "h";
144 case 0x9: return "nl";
145 case 0x1: return "l";
146
147 case 0x3: return "nh";
148
149 case 0x2: return "e";
150
151 case 0xa: return "ne";
152
153 case 0x0: return "v";
154 case 0x8: return "nv";
155 case 0x4: return "n";
156 case 0xc: return "p";
157 /* case 0x1: return "c"; */
158 /* case 0x9: return "nc"; */
159 /* case 0x2: return "z"; */
160 /* case 0xa: return "nz"; */
161 case 0x5: return "r"; /* always */
162 case 0xd: return "sa";
163 }
164 return "(null)";
165 }
166
167
168 // Bcond
169 ddddd,1011,ddd,cccc:III:::Bcond
170 "b%s<cccc> <disp9>"
171 {
172 int cond;
173 if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
174 // Special case - treat "br *" like illegal instruction
175 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
176 } else {
177 cond = condition_met (cccc);
178 if (cond)
179 nia = cia + disp9;
180 TRACE_BRANCH1 (cond);
181 }
182 }
183
184 00000111111,d,cccc + ddddddddddddddd,1:VII:::Bcond
185 "breakpoint":((disp17 == 0) && (cccc == 0x05))
186 "b%s<cccc> <disp17>"
187 *v850e2v3
188 {
189 int cond;
190 cond = condition_met (cccc);
191 if (cond)
192 nia = cia + disp17;
193 TRACE_BRANCH_INPUT1 (cond);
194 TRACE_BRANCH_RESULT (nia);
195 }
196
197
198
199 // BSH
200 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
201 *v850e
202 *v850e1
203 *v850e2
204 *v850e2v3
205 "bsh r<reg2>, r<reg3>"
206 {
207 unsigned32 value;
208 TRACE_ALU_INPUT1 (GR[reg2]);
209
210 value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
211 | MOVED32 (GR[reg2], 31, 24, 23, 16)
212 | MOVED32 (GR[reg2], 7, 0, 15, 8)
213 | MOVED32 (GR[reg2], 15, 8, 7, 0));
214
215 GR[reg3] = value;
216 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
217 if ((value & 0xffff) == 0) PSW |= PSW_Z;
218 if (value & 0x80000000) PSW |= PSW_S;
219 if (((value & 0xff) == 0) || ((value & 0xff00) == 0)) PSW |= PSW_CY;
220
221 TRACE_ALU_RESULT (GR[reg3]);
222 }
223
224
225
226 // BSW
227 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
228 *v850e
229 *v850e1
230 *v850e2
231 *v850e2v3
232 "bsw r<reg2>, r<reg3>"
233 {
234 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
235 unsigned32 value;
236 TRACE_ALU_INPUT1 (GR[reg2]);
237
238 value = GR[reg2];
239 value >>= 24;
240 value |= (GR[reg2] << 24);
241 value |= ((GR[reg2] << 8) & 0x00ff0000);
242 value |= ((GR[reg2] >> 8) & 0x0000ff00);
243 GR[reg3] = value;
244
245 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
246
247 if (value == 0) PSW |= PSW_Z;
248 if (value & 0x80000000) PSW |= PSW_S;
249 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
250
251 TRACE_ALU_RESULT (GR[reg3]);
252 }
253
254
255
256 // CALLT
257 0000001000,iiiiii:II:::callt
258 *v850e
259 *v850e1
260 *v850e2
261 *v850e2v3
262 "callt <imm6>"
263 {
264 unsigned32 adr;
265 unsigned32 off;
266 CTPC = cia + 2;
267 CTPSW = PSW;
268 adr = (CTBP & ~1) + (imm6 << 1);
269 off = load_mem (adr, 2) & ~1; /* Force alignment */
270 nia = (CTBP & ~1) + off;
271 TRACE_BRANCH3 (adr, CTBP, off);
272 }
273
274
275
276 // CAXI
277 rrrrr,111111,RRRRR + wwwww,00011101110:IX:::caxi
278 *v850e2
279 *v850e2v3
280 "caxi [reg1], reg2, reg3"
281 {
282 unsigned int z,s,cy,ov;
283 unsigned32 addr;
284 unsigned32 token,result;
285
286 addr = GR[reg1];
287
288 if (mpu_load_mem_test(sd, addr, 4, reg1)
289 && mpu_store_mem_test(sd, addr, 4, reg1))
290 {
291 token = load_data_mem (sd, addr, 4);
292
293 TRACE_ALU_INPUT2 (token, GR[reg2]);
294
295 result = GR[reg2] - token;
296
297 z = (result == 0);
298 s = (result & 0x80000000);
299 cy = (GR[reg2] < token);
300 ov = ((GR[reg2] & 0x80000000) != (token & 0x80000000)
301 && (GR[reg2] & 0x80000000) != (result & 0x80000000));
302
303 if (result == 0)
304 {
305 store_data_mem (sd, addr, 4, GR[reg3]);
306 GR[reg3] = token;
307 }
308 else
309 {
310 store_data_mem (sd, addr, 4, token);
311 GR[reg3] = token;
312 }
313
314 /* Set condition codes. */
315 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
316 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
317 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
318
319 TRACE_ALU_RESULT1 (GR[reg3]);
320 }
321 }
322
323
324 // CLR1
325 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
326 "clr1 <bit3>, <disp16>[r<reg1>]"
327 {
328 COMPAT_2 (OP_87C0 ());
329 }
330
331 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
332 *v850e
333 *v850e1
334 *v850e2
335 *v850e2v3
336 "clr1 r<reg2>, [r<reg1>]"
337 {
338 COMPAT_2 (OP_E407E0 ());
339 }
340
341
342
343 // CTRET
344 0000011111100000 + 0000000101000100:X:::ctret
345 *v850e
346 *v850e1
347 *v850e2
348 *v850e2v3
349 "ctret"
350 {
351 nia = (CTPC & ~1);
352 PSW = (CTPSW & (CPU)->psw_mask);
353 TRACE_BRANCH1 (PSW);
354 }
355
356
357
358 // CMOV
359 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
360 *v850e
361 *v850e1
362 *v850e2
363 *v850e2v3
364 "cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
365 {
366 int cond = condition_met (cccc);
367 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
368 GR[reg3] = cond ? GR[reg1] : GR[reg2];
369 TRACE_ALU_RESULT (GR[reg3]);
370 }
371
372 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
373 *v850e
374 *v850e1
375 *v850e2
376 *v850e2v3
377 "cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
378 {
379 int cond = condition_met (cccc);
380 TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
381 GR[reg3] = cond ? imm5 : GR[reg2];
382 TRACE_ALU_RESULT (GR[reg3]);
383 }
384
385
386
387 // CMP
388 rrrrr,001111,RRRRR:I:::cmp
389 "cmp r<reg1>, r<reg2>"
390 {
391 COMPAT_1 (OP_1E0 ());
392 }
393
394 rrrrr,010011,iiiii:II:::cmp
395 "cmp <imm5>, r<reg2>"
396 {
397 COMPAT_1 (OP_260 ());
398 }
399
400
401
402 // DI
403 0000011111100000 + 0000000101100000:X:::di
404 "di"
405 {
406 COMPAT_2 (OP_16007E0 ());
407 }
408
409
410
411 // DISPOSE
412 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
413 // "dispose <imm5>, <list12>"
414 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
415 *v850e
416 *v850e1
417 *v850e2
418 *v850e2v3
419 "dispose <imm5>, <list12>":RRRRR == 0
420 "dispose <imm5>, <list12>, [reg1]"
421 {
422 int i;
423 SAVE_2;
424
425 trace_input ("dispose", OP_PUSHPOP1, 0);
426
427 SP += (OP[3] & 0x3e) << 1;
428
429 /* Load the registers with lower number registers being retrieved
430 from higher addresses. */
431 for (i = 12; i--;)
432 if ((OP[3] & (1 << type1_regs[ i ])))
433 {
434 State.regs[ 20 + i ] = load_mem (SP, 4);
435 SP += 4;
436 }
437
438 if ((OP[3] & 0x1f0000) != 0)
439 {
440 nia = State.regs[ (OP[3] >> 16) & 0x1f];
441 }
442
443 trace_output (OP_PUSHPOP1);
444 }
445
446
447
448 // DIV
449 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
450 *v850e
451 *v850e1
452 *v850e2
453 *v850e2v3
454 "div r<reg1>, r<reg2>, r<reg3>"
455 {
456 COMPAT_2 (OP_2C007E0 ());
457 }
458
459
460 // DIVH
461 rrrrr!0,000010,RRRRR!0:I:::divh
462 "divh r<reg1>, r<reg2>"
463 {
464 unsigned32 ov, s, z;
465 signed long int op0, op1, result;
466
467 trace_input ("divh", OP_REG_REG, 0);
468
469 PC = cia;
470 OP[0] = instruction_0 & 0x1f;
471 OP[1] = (instruction_0 >> 11) & 0x1f;
472
473 /* Compute the result. */
474 op0 = EXTEND16 (State.regs[OP[0]]);
475 op1 = State.regs[OP[1]];
476
477 if (op0 == -1 && op1 == 0x80000000)
478 {
479 PSW &= ~PSW_Z;
480 PSW |= PSW_OV | PSW_S;
481 State.regs[OP[1]] = 0x80000000;
482 }
483 else if (op0 == 0)
484 {
485 PSW |= PSW_OV;
486 }
487 else
488 {
489 result = (signed32) op1 / op0;
490 ov = 0;
491
492 /* Compute the condition codes. */
493 z = (result == 0);
494 s = (result & 0x80000000);
495
496 /* Store the result and condition codes. */
497 State.regs[OP[1]] = result;
498 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
499 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));
500 }
501
502 trace_output (OP_REG_REG);
503
504 PC += 2;
505 nia = PC;
506 }
507
508 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
509 *v850e
510 *v850e1
511 *v850e2
512 *v850e2v3
513 "divh r<reg1>, r<reg2>, r<reg3>"
514 {
515 COMPAT_2 (OP_28007E0 ());
516 }
517
518
519 // DIVHU
520 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
521 *v850e
522 *v850e1
523 *v850e2
524 *v850e2v3
525 "divhu r<reg1>, r<reg2>, r<reg3>"
526 {
527 COMPAT_2 (OP_28207E0 ());
528 }
529
530
531 // DIVU
532 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
533 *v850e
534 *v850e1
535 *v850e2
536 *v850e2v3
537 "divu r<reg1>, r<reg2>, r<reg3>"
538 {
539 COMPAT_2 (OP_2C207E0 ());
540 }
541
542
543 // DIVQ
544 rrrrr,111111,RRRRR + wwwww,01011111100:XI:::divq
545 *v850e2
546 *v850e2v3
547 "divq r<reg1>, r<reg2>, r<reg3>"
548 {
549 unsigned int quotient;
550 unsigned int remainder;
551 unsigned int divide_by;
552 unsigned int divide_this;
553
554 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
555
556 divide_by = GR[reg1];
557 divide_this = GR[reg2];
558 v850_div (sd, divide_by, divide_this, &quotient, &remainder);
559 GR[reg2] = quotient;
560 GR[reg3] = remainder;
561
562 TRACE_ALU_RESULT2 (GR[reg2], GR[reg3]);
563 }
564
565
566 // DIVQU
567 rrrrr,111111,RRRRR + wwwww,01011111110:XI:::divqu
568 *v850e2
569 *v850e2v3
570 "divq r<reg1>, r<reg2>, r<reg3>"
571 {
572 unsigned int quotient;
573 unsigned int remainder;
574 unsigned int divide_by;
575 unsigned int divide_this;
576
577 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
578
579 divide_by = GR[reg1];
580 divide_this = GR[reg2];
581 v850_divu (sd, divide_by, divide_this, &quotient, &remainder);
582 GR[reg2] = quotient;
583 GR[reg3] = remainder;
584
585 TRACE_ALU_RESULT2 (GR[reg2], GR[reg3]);
586 }
587
588
589 // EI
590 1000011111100000 + 0000000101100000:X:::ei
591 "ei"
592 {
593 COMPAT_2 (OP_16087E0 ());
594 }
595
596
597
598 // EIRET
599 0000011111100000 + 0000000101001000:X:::eiret
600 "eiret"
601 *v850e2
602 *v850e2v3
603 {
604 TRACE_ALU_INPUT1 (MPM & MPM_AUE);
605
606 nia = EIPC; /* next PC */
607 if (MPM & MPM_AUE)
608 {
609 PSW = EIPSW;
610 }
611 else
612 {
613 PSW = (PSW & (PSW_NPV | PSW_DMP | PSW_IMP))
614 | (EIPSW & ~(PSW_NPV | PSW_DMP | PSW_IMP));
615 }
616
617 TRACE_ALU_RESULT1 (PSW);
618 TRACE_BRANCH_RESULT (nia);
619 }
620
621
622
623 // FERET
624 0000011111100000 + 0000000101001010:X:::feret
625 "feret"
626 *v850e2
627 *v850e2v3
628 {
629 TRACE_ALU_INPUT1 (MPM & MPM_AUE);
630
631 nia = FEPC; /* next PC */
632 if (MPM & MPM_AUE)
633 {
634 PSW = FEPSW;
635 }
636 else
637 {
638 PSW = (PSW & (PSW_NPV | PSW_DMP | PSW_IMP))
639 | (FEPSW & ~(PSW_NPV | PSW_DMP | PSW_IMP));
640 }
641
642 TRACE_ALU_RESULT1 (PSW);
643 TRACE_BRANCH_RESULT (nia);
644 }
645
646
647 // FETRAP
648 0,bbbb!0,00001000000:I:::fetrap
649 "fetrap"
650 *v850e2
651 *v850e2v3
652 {
653 TRACE_ALU_INPUT0 ();
654
655 FEPC = PC + 2;
656 FEPSW = PSW;
657 ECR &= ~ECR_FECC;
658 ECR |= (0x30 + bit4) << 16;
659 FEIC = 0x30 + bit4;
660 PSW |= PSW_EP | PSW_ID | PSW_NP;
661 nia = 0x30; /* next PC */
662
663 TRACE_ALU_RESULT1 (PSW);
664 TRACE_BRANCH_RESULT (nia);
665 }
666
667
668 // HALT
669 0000011111100000 + 0000000100100000:X:::halt
670 "halt"
671 {
672 COMPAT_2 (OP_12007E0 ());
673 }
674
675
676
677 // HSH
678 rrrrr,11111100000 + wwwww,01101000110:XII:::hsh
679 *v850e2
680 *v850e2v3
681 "hsh r<reg2>, r<reg3>"
682 {
683 unsigned32 value;
684 TRACE_ALU_INPUT1 (GR[reg2]);
685
686 value = 0xffff & GR[reg2];
687 GR[reg3] = GR[reg2];
688
689 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
690
691 if (value == 0) { PSW |= PSW_Z; PSW |= PSW_CY; }
692 if (value & 0x80000000) PSW |= PSW_S;
693
694 TRACE_ALU_RESULT1 (GR[reg3]);
695 }
696
697
698 // HSW
699 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
700 *v850e
701 *v850e1
702 *v850e2
703 *v850e2v3
704 "hsw r<reg2>, r<reg3>"
705 {
706 unsigned32 value;
707 TRACE_ALU_INPUT1 (GR[reg2]);
708
709 value = GR[reg2];
710 value >>= 16;
711 value |= (GR[reg2] << 16);
712
713 GR[reg3] = value;
714
715 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
716
717 if (value == 0) PSW |= PSW_Z;
718 if (value & 0x80000000) PSW |= PSW_S;
719 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
720
721 TRACE_ALU_RESULT (GR[reg3]);
722 }
723
724
725
726 // JARL
727 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
728 "jarl <disp22>, r<reg2>"
729 {
730 GR[reg2] = nia;
731 nia = cia + disp22;
732 TRACE_BRANCH1 (GR[reg2]);
733 }
734
735 00000010111,RRRRR!0 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jarl32
736 *v850e2
737 *v850e2v3
738 "jarl <imm32>, r<reg1>"
739 {
740 GR[reg1] = nia;
741 nia = (cia + imm32) & ~1;
742
743 TRACE_BRANCH_RESULT (nia);
744 }
745
746
747 // JMP
748 00000000011,RRRRR:I:::jmp
749 "jmp [r<reg1>]"
750 {
751 nia = GR[reg1] & ~1;
752 TRACE_BRANCH0 ();
753 }
754
755 00000110111,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jmp32
756 *v850e2
757 *v850e2v3
758 "jmp <imm32>[r<reg1>]"
759 {
760 nia = (GR[reg1] + imm32) & ~1;
761
762 TRACE_BRANCH_RESULT (nia);
763 }
764
765
766 // JR
767 0000011110,dddddd + ddddddddddddddd,0:V:::jr
768 "jr <disp22>"
769 {
770 nia = cia + disp22;
771 TRACE_BRANCH0 ();
772 }
773
774
775 // JR32
776 0000001011100000 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jr32
777 *v850e2
778 *v850e2v3
779 "jr <imm32>"
780 {
781 nia = (cia + imm32) & ~1;
782
783 TRACE_BRANCH_RESULT (nia);
784 }
785
786
787 // LD
788 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
789 "ld.b <disp16>[r<reg1>], r<reg2>"
790 {
791 COMPAT_2 (OP_700 ());
792 }
793
794 00000111100,RRRRR+wwwww,ddddddd,0101+dddddddddddddddd:XIV:::ld.b
795 "ld.b <disp23>[r<reg1>], r<reg3>"
796 *v850e2v3
797 {
798 unsigned32 addr = GR[reg1] + disp23;
799 unsigned32 result = EXTEND8 (load_data_mem (sd, addr, 1));
800 GR[reg3] = result;
801 TRACE_LD (addr, result);
802 }
803
804 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
805 "ld.h <disp16>[r<reg1>], r<reg2>"
806 {
807 COMPAT_2 (OP_720 ());
808 }
809
810 00000111100,RRRRR+wwwww,dddddd,00111+dddddddddddddddd:XIV:::ld.h
811 *v850e2v3
812 "ld.h <disp23>[r<reg1>], r<reg3>"
813 {
814 unsigned32 addr = GR[reg1] + disp23;
815 unsigned32 result = EXTEND16 (load_data_mem (sd, addr, 2));
816 GR[reg3] = result;
817 TRACE_LD (addr, result);
818 }
819
820 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
821 "ld.w <disp16>[r<reg1>], r<reg2>"
822 {
823 COMPAT_2 (OP_10720 ());
824 }
825
826 00000111100,RRRRR+wwwww,dddddd,01001+dddddddddddddddd:XIV:::ld.w
827 *v850e2v3
828 "ld.w <disp23>[r<reg1>], r<reg3>"
829 {
830 unsigned32 addr = GR[reg1] + disp23;
831 unsigned32 result = load_data_mem (sd, addr, 4);
832 GR[reg3] = result;
833 TRACE_LD (addr, result);
834 }
835
836 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
837 *v850e
838 *v850e1
839 *v850e2
840 *v850e2v3
841 "ld.bu <disp16>[r<reg1>], r<reg2>"
842 {
843 COMPAT_2 (OP_10780 ());
844 }
845
846 00000111101,RRRRR+wwwww,ddddddd,0101+dddddddddddddddd:XIV:::ld.bu
847 *v850e2v3
848 "ld.bu <disp23>[r<reg1>], r<reg3>"
849 {
850 unsigned32 addr = GR[reg1] + disp23;
851 unsigned32 result = load_data_mem (sd, addr, 1);
852 GR[reg3] = result;
853 TRACE_LD (addr, result);
854 }
855
856 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
857 *v850e
858 *v850e1
859 *v850e2
860 *v850e2v3
861 "ld.hu <disp16>[r<reg1>], r<reg2>"
862 {
863 COMPAT_2 (OP_107E0 ());
864 }
865
866 00000111101,RRRRR+wwwww,dddddd,00111+dddddddddddddddd:XIV:::ld.hu
867 *v850e2v3
868 "ld.hu <disp23>[r<reg1>], r<reg3>"
869 {
870 unsigned32 addr = GR[reg1] + disp23;
871 unsigned32 result = load_data_mem (sd, addr, 2);
872 GR[reg3] = result;
873 TRACE_LD (addr, result);
874 }
875
876
877
878 // LDSR
879 regID,111111,RRRRR + 0000000000100000:IX:::ldsr
880 "ldsr r<reg1>, s<regID>"
881 {
882 uint32 sreg = GR[reg1];
883 TRACE_ALU_INPUT1 (GR[reg1]);
884
885 if ((idecode_issue == idecode_v850e2_issue
886 || idecode_issue == idecode_v850e2v3_issue)
887 && regID < 28)
888 {
889 int protect_p = (PSW & PSW_NPV) ? 1 : 0;
890
891
892 switch (BSEL & 0xffff)
893 {
894 case 0x0000:
895 if ((PSW & PSW_NPV)
896 && ((regID >= 8 && regID <= 12)
897 || (regID >= 22 && regID <= 27)
898 || regID == PSW_REGNO))
899 {
900 protect_p = 0;
901 }
902 break;
903 case 0x1000: /* MPU0 */
904 break;
905 case 0x1001: /* MPU1 */
906 break;
907 case 0x2000: /* FPU */
908 if ((PSW & PSW_NPV)
909 && ((/* regID >= 0 && */ regID <= 5)
910 || regID == 8
911 || regID == 9
912 || regID == 10
913 || (regID >= 11 && regID <= 26)))
914 {
915 protect_p = 0;
916 }
917 break;
918 case 0xff00:
919 if ((PSW & PSW_NPV)
920 && (regID == 6
921 || regID == 7
922 || regID == 8
923 || regID == 9
924 || regID == 10
925 || (regID >= 11 && regID <= 15)
926 || regID == 18
927 || regID == 19
928 || (regID >= 21 && regID <= 27)))
929 {
930 protect_p = 0;
931 }
932 break;
933 case 0xffff:
934 if ((PSW & PSW_NPV)
935 && (regID == 6
936 || regID == 7
937 || regID == 8
938 || regID == 9
939 || regID == 10
940 || regID == 11
941 || regID == 12
942 || regID == 15
943 || regID == 18
944 || regID == 19
945 || (regID >= 21 && regID <= 27)))
946 {
947 protect_p = 0;
948 }
949 break;
950 }
951
952 if (!protect_p)
953 {
954 switch (BSEL & 0xffff)
955 {
956 case 0x0000:
957 case 0xff00: /* user0 bank */
958 case 0xffff: /* user1 bank */
959 if(regID == PSW_REGNO)
960 {
961 SR[regID] = sreg & ((PSW & PSW_NPV) ? 0xf : ~0);
962 }
963 else
964 {
965 SR[regID] = sreg;
966 }
967 break;
968 case 0x1000:
969 MPU0_SR[regID] = sreg;
970 break;
971 case 0x1001:
972 if (regID == MPC_REGNO)
973 {
974 PPC &= ~PPC_PPE;
975 SPAL &= ~SPAL_SPE;
976 IPA0L &= ~IPA_IPE;
977 IPA1L &= ~IPA_IPE;
978 IPA2L &= ~IPA_IPE;
979 IPA3L &= ~IPA_IPE;
980 DPA0L &= ~DPA_DPE;
981 DPA1L &= ~DPA_DPE;
982 DCC &= ~(DCC_DCE0 | DCC_DCE1);
983 }
984 else
985 {
986 MPU1_SR[regID] = sreg;
987 }
988 break;
989 case 0x2000: /* FPU */
990 if (regID == FPST_REGNO)
991 {
992 unsigned int val = FPSR & ~(FPSR_PR | FPSR_XC | FPSR_XP);
993
994 val |= ((sreg & FPST_PR) ? FPSR_PR : 0)
995 | ((sreg & FPST_XCE) ? FPSR_XCE : 0)
996 | ((sreg & FPST_XCV) ? FPSR_XCV : 0)
997 | ((sreg & FPST_XCZ) ? FPSR_XCZ : 0)
998 | ((sreg & FPST_XCO) ? FPSR_XCO : 0)
999 | ((sreg & FPST_XCU) ? FPSR_XCU : 0)
1000 | ((sreg & FPST_XCI) ? FPSR_XCI : 0)
1001 | ((sreg & FPST_XPV) ? FPSR_XPV : 0)
1002 | ((sreg & FPST_XPZ) ? FPSR_XPZ : 0)
1003 | ((sreg & FPST_XPO) ? FPSR_XPO : 0)
1004 | ((sreg & FPST_XPU) ? FPSR_XPU : 0)
1005 | ((sreg & FPST_XPI) ? FPSR_XPI : 0);
1006 FPSR = val;
1007 }
1008 else if (regID == FPCFG_REGNO)
1009 {
1010 unsigned int val = FPSR & ~(FPSR_RM | FPSR_XE);
1011
1012 val |= (((sreg & FPCFG_RM) >> 7) << 18)
1013 | ((sreg & FPCFG_XEV) ? FPSR_XEV : 0)
1014 | ((sreg & FPCFG_XEZ) ? FPSR_XEZ : 0)
1015 | ((sreg & FPCFG_XEO) ? FPSR_XEO : 0)
1016 | ((sreg & FPCFG_XEU) ? FPSR_XEU : 0)
1017 | ((sreg & FPCFG_XEI) ? FPSR_XEI : 0);
1018 FPSR = val;
1019 }
1020
1021 FPU_SR[regID] = sreg;
1022 break;
1023 }
1024 }
1025 }
1026 else
1027 {
1028 SR[regID] = sreg;
1029 }
1030
1031 TRACE_ALU_RESULT (sreg);
1032 }
1033
1034
1035
1036 // MAC
1037 rrrrr,111111,RRRRR + wwww,0011110,mmmm,0:XI:::mac
1038 *v850e2
1039 *v850e2v3
1040 "mac r<reg1>, r<reg2>, r<reg3e>, r<reg4e>"
1041 {
1042 unsigned long op0;
1043 unsigned long op1;
1044 unsigned long op2;
1045 unsigned long op2hi;
1046 unsigned long lo;
1047 unsigned long mid1;
1048 unsigned long mid2;
1049 unsigned long hi;
1050 unsigned long RdLo;
1051 unsigned long RdHi;
1052 int carry;
1053 bfd_boolean sign;
1054
1055 op0 = GR[reg1];
1056 op1 = GR[reg2];
1057 op2 = GR[reg3e];
1058 op2hi = GR[reg3e+1];
1059
1060 TRACE_ALU_INPUT4 (op0, op1, op2, op2hi);
1061
1062 sign = (op0 ^ op1) & 0x80000000;
1063
1064 if (((signed long) op0) < 0)
1065 op0 = - op0;
1066
1067 if (((signed long) op1) < 0)
1068 op1 = - op1;
1069
1070 /* We can split the 32x32 into four 16x16 operations. This ensures
1071 that we do not lose precision on 32bit only hosts: */
1072 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
1073 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
1074 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
1075 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
1076
1077 /* We now need to add all of these results together, taking care
1078 to propogate the carries from the additions: */
1079 RdLo = Add32 (lo, (mid1 << 16), & carry);
1080 RdHi = carry;
1081 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
1082 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
1083
1084 if (sign)
1085 {
1086 RdLo = ~ RdLo;
1087 RdHi = ~ RdHi;
1088 if (RdLo == 0xFFFFFFFF)
1089 {
1090 RdLo = 0;
1091 RdHi += 1;
1092 }
1093 else
1094 RdLo += 1;
1095 }
1096
1097 RdLo = Add32 (RdLo, op2, & carry);
1098 RdHi += carry + op2hi;
1099
1100 /* Store the result and condition codes. */
1101 GR[reg4e] = RdLo;
1102 GR[reg4e + 1 ] = RdHi;
1103
1104 TRACE_ALU_RESULT2 (RdLo, RdHi);
1105 }
1106
1107
1108
1109 // MACU
1110 rrrrr,111111,RRRRR + wwww,0011111,mmmm,0:XI:::macu
1111 *v850e2
1112 *v850e2v3
1113 "macu r<reg1>, r<reg2>, r<reg3e>, r<reg4e>"
1114 {
1115 unsigned long op0;
1116 unsigned long op1;
1117 unsigned long op2;
1118 unsigned long op2hi;
1119 unsigned long lo;
1120 unsigned long mid1;
1121 unsigned long mid2;
1122 unsigned long hi;
1123 unsigned long RdLo;
1124 unsigned long RdHi;
1125 int carry;
1126
1127 op0 = GR[reg1];
1128 op1 = GR[reg2];
1129 op2 = GR[reg3e];
1130 op2hi = GR[reg3e + 1];
1131
1132 TRACE_ALU_INPUT4 (op0, op1, op2, op2hi);
1133
1134 /* We can split the 32x32 into four 16x16 operations. This ensures
1135 that we do not lose precision on 32bit only hosts: */
1136 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
1137 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
1138 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
1139 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
1140
1141 /* We now need to add all of these results together, taking care
1142 to propogate the carries from the additions: */
1143 RdLo = Add32 (lo, (mid1 << 16), & carry);
1144 RdHi = carry;
1145 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
1146 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
1147
1148 RdLo = Add32 (RdLo, op2, & carry);
1149 RdHi += carry + op2hi;
1150
1151 /* Store the result and condition codes. */
1152 GR[reg4e] = RdLo;
1153 GR[reg4e+1] = RdHi;
1154
1155 TRACE_ALU_RESULT2 (RdLo, RdHi);
1156 }
1157
1158
1159
1160 // MOV
1161 rrrrr!0,000000,RRRRR:I:::mov
1162 "mov r<reg1>, r<reg2>"
1163 {
1164 TRACE_ALU_INPUT0 ();
1165 GR[reg2] = GR[reg1];
1166 TRACE_ALU_RESULT (GR[reg2]);
1167 }
1168
1169 rrrrr!0,010000,iiiii:II:::mov
1170 "mov <imm5>, r<reg2>"
1171 {
1172 COMPAT_1 (OP_200 ());
1173 }
1174
1175 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
1176 *v850e
1177 *v850e1
1178 *v850e2
1179 *v850e2v3
1180 "mov <imm32>, r<reg1>"
1181 {
1182 SAVE_2;
1183 trace_input ("mov", OP_IMM_REG, 4);
1184 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
1185 trace_output (OP_IMM_REG);
1186 }
1187
1188
1189
1190 // MOVEA
1191 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
1192 "movea <simm16>, r<reg1>, r<reg2>"
1193 {
1194 TRACE_ALU_INPUT2 (GR[reg1], simm16);
1195 GR[reg2] = GR[reg1] + simm16;
1196 TRACE_ALU_RESULT (GR[reg2]);
1197 }
1198
1199
1200
1201 // MOVHI
1202 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
1203 "movhi <uimm16>, r<reg1>, r<reg2>"
1204 {
1205 COMPAT_2 (OP_640 ());
1206 }
1207
1208
1209
1210 // MUL
1211 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
1212 *v850e
1213 *v850e1
1214 *v850e2
1215 *v850e2v3
1216 "mul r<reg1>, r<reg2>, r<reg3>"
1217 {
1218 COMPAT_2 (OP_22007E0 ());
1219 }
1220
1221 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
1222 *v850e
1223 *v850e1
1224 *v850e2
1225 *v850e2v3
1226 "mul <imm9>, r<reg2>, r<reg3>"
1227 {
1228 COMPAT_2 (OP_24007E0 ());
1229 }
1230
1231
1232 // MULH
1233 rrrrr!0,000111,RRRRR:I:::mulh
1234 "mulh r<reg1>, r<reg2>"
1235 {
1236 COMPAT_1 (OP_E0 ());
1237 }
1238
1239 rrrrr!0,010111,iiiii:II:::mulh
1240 "mulh <imm5>, r<reg2>"
1241 {
1242 COMPAT_1 (OP_2E0 ());
1243 }
1244
1245
1246
1247 // MULHI
1248 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
1249 "mulhi <uimm16>, r<reg1>, r<reg2>"
1250 {
1251 COMPAT_2 (OP_6E0 ());
1252 }
1253
1254
1255
1256 // MULU
1257 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
1258 *v850e
1259 *v850e1
1260 *v850e2
1261 *v850e2v3
1262 "mulu r<reg1>, r<reg2>, r<reg3>"
1263 {
1264 COMPAT_2 (OP_22207E0 ());
1265 }
1266
1267 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
1268 *v850e
1269 *v850e1
1270 *v850e2
1271 *v850e2v3
1272 "mulu <imm9>, r<reg2>, r<reg3>"
1273 {
1274 COMPAT_2 (OP_24207E0 ());
1275 }
1276
1277
1278
1279 // NOP
1280 0000000000000000:I:::nop
1281 "nop"
1282 {
1283 /* do nothing, trace nothing */
1284 }
1285
1286
1287
1288 // NOT
1289 rrrrr,000001,RRRRR:I:::not
1290 "not r<reg1>, r<reg2>"
1291 {
1292 COMPAT_1 (OP_20 ());
1293 }
1294
1295
1296
1297 // NOT1
1298 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
1299 "not1 <bit3>, <disp16>[r<reg1>]"
1300 {
1301 COMPAT_2 (OP_47C0 ());
1302 }
1303
1304 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
1305 *v850e
1306 *v850e1
1307 *v850e2
1308 *v850e2v3
1309 "not1 r<reg2>, r<reg1>"
1310 {
1311 COMPAT_2 (OP_E207E0 ());
1312 }
1313
1314
1315
1316 // OR
1317 rrrrr,001000,RRRRR:I:::or
1318 "or r<reg1>, r<reg2>"
1319 {
1320 COMPAT_1 (OP_100 ());
1321 }
1322
1323
1324
1325 // ORI
1326 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
1327 "ori <uimm16>, r<reg1>, r<reg2>"
1328 {
1329 COMPAT_2 (OP_680 ());
1330 }
1331
1332
1333
1334 // PREPARE
1335 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
1336 *v850e
1337 *v850e1
1338 *v850e2
1339 *v850e2v3
1340 "prepare <list12>, <imm5>"
1341 {
1342 int i;
1343 SAVE_2;
1344
1345 trace_input ("prepare", OP_PUSHPOP1, 0);
1346
1347 /* Store the registers with lower number registers being placed at
1348 higher addresses. */
1349 for (i = 0; i < 12; i++)
1350 if ((OP[3] & (1 << type1_regs[ i ])))
1351 {
1352 SP -= 4;
1353 store_mem (SP, 4, State.regs[ 20 + i ]);
1354 }
1355
1356 SP -= (OP[3] & 0x3e) << 1;
1357
1358 trace_output (OP_PUSHPOP1);
1359 }
1360
1361
1362 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
1363 *v850e
1364 *v850e1
1365 *v850e2
1366 *v850e2v3
1367 "prepare <list12>, <imm5>, sp"
1368 {
1369 COMPAT_2 (OP_30780 ());
1370 }
1371
1372 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
1373 *v850e
1374 *v850e1
1375 *v850e2
1376 *v850e2v3
1377 "prepare <list12>, <imm5>, <uimm16>"
1378 {
1379 COMPAT_2 (OP_B0780 ());
1380 }
1381
1382 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
1383 *v850e
1384 *v850e1
1385 *v850e2
1386 *v850e2v3
1387 "prepare <list12>, <imm5>, <uimm16>"
1388 {
1389 COMPAT_2 (OP_130780 ());
1390 }
1391
1392 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
1393 *v850e
1394 *v850e1
1395 *v850e2
1396 *v850e2v3
1397 "prepare <list12>, <imm5>, <uimm32>"
1398 {
1399 COMPAT_2 (OP_1B0780 ());
1400 }
1401
1402
1403
1404 // RETI
1405 0000011111100000 + 0000000101000000:X:::reti
1406 "reti"
1407 {
1408 if ((PSW & PSW_EP))
1409 {
1410 nia = (EIPC & ~1);
1411 PSW = EIPSW;
1412 }
1413 else if ((PSW & PSW_NP))
1414 {
1415 nia = (FEPC & ~1);
1416 PSW = FEPSW;
1417 }
1418 else
1419 {
1420 nia = (EIPC & ~1);
1421 PSW = EIPSW;
1422 }
1423 TRACE_BRANCH1 (PSW);
1424 }
1425
1426
1427
1428 // SAR
1429 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
1430 "sar r<reg1>, r<reg2>"
1431 {
1432 COMPAT_2 (OP_A007E0 ());
1433 }
1434
1435 rrrrr,010101,iiiii:II:::sar
1436 "sar <imm5>, r<reg2>"
1437 {
1438 COMPAT_1 (OP_2A0 ());
1439 }
1440
1441 rrrrr,111111,RRRRR + wwwww,00010100010:XI:::sar
1442 *v850e2
1443 *v850e2v3
1444 "sar r<reg1>, r<reg2>, r<reg3>"
1445 {
1446 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
1447 v850_sar(sd, GR[reg1], GR[reg2], &GR[reg3]);
1448 TRACE_ALU_RESULT1 (GR[reg3]);
1449 }
1450
1451
1452 // SASF
1453 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
1454 *v850e
1455 *v850e1
1456 *v850e2
1457 *v850e2v3
1458 "sasf %s<cccc>, r<reg2>"
1459 {
1460 COMPAT_2 (OP_20007E0 ());
1461 }
1462
1463
1464
1465 // SATADD
1466 rrrrr!0,000110,RRRRR:I:::satadd
1467 "satadd r<reg1>, r<reg2>"
1468 {
1469 COMPAT_1 (OP_C0 ());
1470 }
1471
1472 rrrrr!0,010001,iiiii:II:::satadd
1473 "satadd <imm5>, r<reg2>"
1474 {
1475 COMPAT_1 (OP_220 ());
1476 }
1477
1478 rrrrr,111111,RRRRR + wwwww,01110111010:XI:::satadd
1479 *v850e2
1480 *v850e2v3
1481 "satadd r<reg1>, r<reg2>, r<reg3>"
1482 {
1483 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
1484 v850_satadd (sd, GR[reg1], GR[reg2], &GR[reg3]);
1485 TRACE_ALU_RESULT1 (GR[reg3]);
1486 }
1487
1488
1489
1490 // SATSUB
1491 rrrrr!0,000101,RRRRR:I:::satsub
1492 "satsub r<reg1>, r<reg2>"
1493 {
1494 COMPAT_1 (OP_A0 ());
1495 }
1496
1497 rrrrr,111111,RRRRR + wwwww,01110011010:XI:::satsub
1498 *v850e2
1499 *v850e2v3
1500 "satsub r<reg1>, r<reg2>, r<reg3>"
1501 {
1502 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
1503 v850_satsub (sd, GR[reg1], GR[reg2], &GR[reg3]);
1504 TRACE_ALU_RESULT1 (GR[reg3]);
1505 }
1506
1507
1508
1509 // SATSUBI
1510 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
1511 "satsubi <simm16>, r<reg1>, r<reg2>"
1512 {
1513 COMPAT_2 (OP_660 ());
1514 }
1515
1516
1517
1518 // SATSUBR
1519 rrrrr!0,000100,RRRRR:I:::satsubr
1520 "satsubr r<reg1>, r<reg2>"
1521 {
1522 COMPAT_1 (OP_80 ());
1523 }
1524
1525
1526
1527 //SBF
1528 rrrrr,111111,RRRRR + wwwww,011100,cccc!13,0:XI:::sbf
1529 *v850e2
1530 *v850e2v3
1531 "sbf %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
1532 {
1533 int cond = condition_met (cccc);
1534 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
1535 GR[reg3] = GR[reg2] - GR[reg1] - (cond ? 1 : 0);
1536 TRACE_ALU_RESULT1 (GR[reg3]);
1537 }
1538
1539
1540
1541 // SCH0L
1542 rrrrr,11111100000 + wwwww,01101100100:IX:::sch0l
1543 *v850e2
1544 *v850e2v3
1545 "sch0l r<reg2>, r<reg3>"
1546 {
1547 unsigned int pos, op0;
1548
1549 TRACE_ALU_INPUT1 (GR[reg2]);
1550
1551 op0 = GR[reg2];
1552
1553 if (op0 == 0xffffffff)
1554 {
1555 PSW &= ~PSW_CY;
1556 PSW &= ~PSW_OV;
1557 PSW &= ~PSW_S;
1558 PSW |= PSW_Z;
1559 pos = 0;
1560 }
1561 else if (op0 == 0xfffffffe)
1562 {
1563 PSW |= PSW_CY;
1564 PSW &= ~PSW_OV;
1565 PSW &= ~PSW_S;
1566 PSW &= ~PSW_Z;
1567 pos = 32;
1568 }
1569 else
1570 {
1571 pos = 1;
1572 while (op0 & 0x80000000)
1573 {
1574 op0 <<= 1;
1575 pos++;
1576 }
1577 PSW &= ~PSW_CY;
1578 PSW &= ~PSW_OV;
1579 PSW &= ~PSW_S;
1580 PSW &= ~PSW_Z;
1581 }
1582
1583 GR[reg3] = pos;
1584
1585 TRACE_ALU_RESULT1 (GR[reg3]);
1586 }
1587
1588
1589
1590 // SCH0R
1591 rrrrr,11111100000 + wwwww,01101100000:IX:::sch0r
1592 *v850e2
1593 *v850e2v3
1594 "sch0r r<reg2>, r<reg3>"
1595 {
1596 unsigned int pos, op0;
1597
1598 TRACE_ALU_INPUT1 (GR[reg2]);
1599
1600 op0 = GR[reg2];
1601
1602 if (op0 == 0xffffffff)
1603 {
1604 PSW &= ~PSW_CY;
1605 PSW &= ~PSW_OV;
1606 PSW &= ~PSW_S;
1607 PSW |= PSW_Z;
1608 pos = 0;
1609 }
1610 else if (op0 == 0x7fffffff)
1611 {
1612 PSW |= PSW_CY;
1613 PSW &= ~PSW_OV;
1614 PSW &= ~PSW_S;
1615 PSW &= ~PSW_Z;
1616 pos = 32;
1617 }
1618 else
1619 {
1620 pos = 1;
1621 while (op0 & 0x00000001)
1622 {
1623 op0 >>= 1;
1624 pos++;
1625 }
1626 PSW &= ~PSW_CY;
1627 PSW &= ~PSW_OV;
1628 PSW &= ~PSW_S;
1629 PSW &= ~PSW_Z;
1630 }
1631
1632 GR[reg3] = pos;
1633
1634 TRACE_ALU_RESULT1 (GR[reg3]);
1635 }
1636
1637 // SCH1L
1638 rrrrr,11111100000 + wwwww,01101100110:IX:::sch1l
1639 *v850e2
1640 *v850e2v3
1641 "sch1l r<reg2>, r<reg3>"
1642 {
1643 unsigned int pos, op0;
1644
1645 TRACE_ALU_INPUT1 (GR[reg2]);
1646
1647 op0 = GR[reg2];
1648
1649 if (op0 == 0x00000000)
1650 {
1651 PSW &= ~PSW_CY;
1652 PSW &= ~PSW_OV;
1653 PSW &= ~PSW_S;
1654 PSW |= PSW_Z;
1655 pos = 0;
1656 }
1657 else if (op0 == 0x00000001)
1658 {
1659 PSW |= PSW_CY;
1660 PSW &= ~PSW_OV;
1661 PSW &= ~PSW_S;
1662 PSW &= ~PSW_Z;
1663 pos = 32;
1664 }
1665 else
1666 {
1667 pos = 1;
1668 while (!(op0 & 0x80000000))
1669 {
1670 op0 <<= 1;
1671 pos++;
1672 }
1673 PSW &= ~PSW_CY;
1674 PSW &= ~PSW_OV;
1675 PSW &= ~PSW_S;
1676 PSW &= ~PSW_Z;
1677 }
1678
1679 GR[reg3] = pos;
1680
1681 TRACE_ALU_RESULT1 (GR[reg3]);
1682 }
1683
1684 // SCH1R
1685 rrrrr,11111100000 + wwwww,01101100010:IX:::sch1r
1686 *v850e2
1687 *v850e2v3
1688 "sch1r r<reg2>, r<reg3>"
1689 {
1690 unsigned int pos, op0;
1691
1692 TRACE_ALU_INPUT1 (GR[reg2]);
1693
1694 op0 = GR[reg2];
1695
1696 if (op0 == 0x00000000)
1697 {
1698 PSW &= ~PSW_CY;
1699 PSW &= ~PSW_OV;
1700 PSW &= ~PSW_S;
1701 PSW |= PSW_Z;
1702 pos = 0;
1703 }
1704 else if (op0 == 0x80000000)
1705 {
1706 PSW |= PSW_CY;
1707 PSW &= ~PSW_OV;
1708 PSW &= ~PSW_S;
1709 PSW &= ~PSW_Z;
1710 pos = 32;
1711 }
1712 else
1713 {
1714 pos = 1;
1715 while (!(op0 & 0x00000001))
1716 {
1717 op0 >>= 1;
1718 pos++;
1719 }
1720 PSW &= ~PSW_CY;
1721 PSW &= ~PSW_OV;
1722 PSW &= ~PSW_S;
1723 PSW &= ~PSW_Z;
1724 }
1725
1726 GR[reg3] = pos;
1727
1728 TRACE_ALU_RESULT1 (GR[reg3]);
1729 }
1730
1731 //SHL
1732 rrrrr,111111,RRRRR + wwwww,00011000010:XI:::shl
1733 *v850e2
1734 *v850e2v3
1735 "shl r<reg1>, r<reg2>, r<reg3>"
1736 {
1737 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
1738 v850_shl(sd, GR[reg1], GR[reg2], &GR[reg3]);
1739 TRACE_ALU_RESULT1 (GR[reg3]);
1740 }
1741
1742 //SHR
1743 rrrrr,111111,RRRRR + wwwww,00010000010:XI:::shr
1744 *v850e2
1745 *v850e2v3
1746 "shr r<reg1>, r<reg2>, r<reg3>"
1747 {
1748 TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
1749 v850_shr(sd, GR[reg1], GR[reg2], &GR[reg3]);
1750 TRACE_ALU_RESULT1 (GR[reg3]);
1751 }
1752
1753
1754
1755 // SETF
1756 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
1757 "setf %s<cccc>, r<reg2>"
1758 {
1759 COMPAT_2 (OP_7E0 ());
1760 }
1761
1762
1763
1764 // SET1
1765 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
1766 "set1 <bit3>, <disp16>[r<reg1>]"
1767 {
1768 COMPAT_2 (OP_7C0 ());
1769 }
1770
1771 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
1772 *v850e
1773 *v850e1
1774 *v850e2
1775 *v850e2v3
1776 "set1 r<reg2>, [r<reg1>]"
1777 {
1778 COMPAT_2 (OP_E007E0 ());
1779 }
1780
1781
1782
1783 // SHL
1784 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
1785 "shl r<reg1>, r<reg2>"
1786 {
1787 COMPAT_2 (OP_C007E0 ());
1788 }
1789
1790 rrrrr,010110,iiiii:II:::shl
1791 "shl <imm5>, r<reg2>"
1792 {
1793 COMPAT_1 (OP_2C0 ());
1794 }
1795
1796
1797
1798 // SHR
1799 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
1800 "shr r<reg1>, r<reg2>"
1801 {
1802 COMPAT_2 (OP_8007E0 ());
1803 }
1804
1805 rrrrr,010100,iiiii:II:::shr
1806 "shr <imm5>, r<reg2>"
1807 {
1808 COMPAT_1 (OP_280 ());
1809 }
1810
1811
1812
1813 // SLD
1814 rrrrr,0110,ddddddd:IV:::sld.b
1815 "sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
1816 "sld.b <disp7>[ep], r<reg2>"
1817 {
1818 unsigned32 addr = EP + disp7;
1819 unsigned32 result = load_mem (addr, 1);
1820 if (PSW & PSW_US)
1821 {
1822 GR[reg2] = result;
1823 TRACE_LD_NAME ("sld.bu", addr, result);
1824 }
1825 else
1826 {
1827 result = EXTEND8 (result);
1828 GR[reg2] = result;
1829 TRACE_LD (addr, result);
1830 }
1831 }
1832
1833 rrrrr,1000,ddddddd:IV:::sld.h
1834 "sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
1835 "sld.h <disp8>[ep], r<reg2>"
1836 {
1837 unsigned32 addr = EP + disp8;
1838 unsigned32 result = load_mem (addr, 2);
1839 if (PSW & PSW_US)
1840 {
1841 GR[reg2] = result;
1842 TRACE_LD_NAME ("sld.hu", addr, result);
1843 }
1844 else
1845 {
1846 result = EXTEND16 (result);
1847 GR[reg2] = result;
1848 TRACE_LD (addr, result);
1849 }
1850 }
1851
1852 rrrrr,1010,dddddd,0:IV:::sld.w
1853 "sld.w <disp8>[ep], r<reg2>"
1854 {
1855 unsigned32 addr = EP + disp8;
1856 unsigned32 result = load_mem (addr, 4);
1857 GR[reg2] = result;
1858 TRACE_LD (addr, result);
1859 }
1860
1861 rrrrr!0,0000110,dddd:IV:::sld.bu
1862 *v850e
1863 *v850e1
1864 *v850e2
1865 *v850e2v3
1866 "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
1867 "sld.bu <disp4>[ep], r<reg2>"
1868 {
1869 unsigned32 addr = EP + disp4;
1870 unsigned32 result = load_mem (addr, 1);
1871 if (PSW & PSW_US)
1872 {
1873 result = EXTEND8 (result);
1874 GR[reg2] = result;
1875 TRACE_LD_NAME ("sld.b", addr, result);
1876 }
1877 else
1878 {
1879 GR[reg2] = result;
1880 TRACE_LD (addr, result);
1881 }
1882 }
1883
1884 rrrrr!0,0000111,dddd:IV:::sld.hu
1885 *v850e
1886 *v850e1
1887 *v850e2
1888 *v850e2v3
1889 "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
1890 "sld.hu <disp5>[ep], r<reg2>"
1891 {
1892 unsigned32 addr = EP + disp5;
1893 unsigned32 result = load_mem (addr, 2);
1894 if (PSW & PSW_US)
1895 {
1896 result = EXTEND16 (result);
1897 GR[reg2] = result;
1898 TRACE_LD_NAME ("sld.h", addr, result);
1899 }
1900 else
1901 {
1902 GR[reg2] = result;
1903 TRACE_LD (addr, result);
1904 }
1905 }
1906
1907
1908
1909 // SST
1910 rrrrr,0111,ddddddd:IV:::sst.b
1911 "sst.b r<reg2>, <disp7>[ep]"
1912 {
1913 COMPAT_1 (OP_380 ());
1914 }
1915
1916 rrrrr,1001,ddddddd:IV:::sst.h
1917 "sst.h r<reg2>, <disp8>[ep]"
1918 {
1919 COMPAT_1 (OP_480 ());
1920 }
1921
1922 rrrrr,1010,dddddd,1:IV:::sst.w
1923 "sst.w r<reg2>, <disp8>[ep]"
1924 {
1925 COMPAT_1 (OP_501 ());
1926 }
1927
1928 // ST
1929 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
1930 "st.b r<reg2>, <disp16>[r<reg1>]"
1931 {
1932 COMPAT_2 (OP_740 ());
1933 }
1934
1935 00000111100,RRRRR + wwwww,ddddddd,1101 + dddddddddddddddd:XIV:::st.b
1936 *v850e2v3
1937 "st.b r<reg3>, <disp23>[r<reg1>]"
1938 {
1939 unsigned32 addr = GR[reg1] + disp23;
1940 store_data_mem (sd, addr, 1, GR[reg3]);
1941 TRACE_ST (addr, GR[reg3]);
1942 }
1943
1944 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
1945 "st.h r<reg2>, <disp16>[r<reg1>]"
1946 {
1947 COMPAT_2 (OP_760 ());
1948 }
1949
1950 00000111101,RRRRR+wwwww,dddddd,01101+dddddddddddddddd:XIV:::st.h
1951 *v850e2v3
1952 "st.h r<reg3>, <disp23>[r<reg1>]"
1953 {
1954 unsigned32 addr = GR[reg1] + disp23;
1955 store_data_mem (sd, addr, 2, GR[reg3]);
1956 TRACE_ST (addr, GR[reg3]);
1957 }
1958
1959 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1960 "st.w r<reg2>, <disp16>[r<reg1>]"
1961 {
1962 COMPAT_2 (OP_10760 ());
1963 }
1964
1965 00000111100,RRRRR+wwwww,dddddd,01111+dddddddddddddddd:XIV:::st.w
1966 *v850e2v3
1967 "st.w r<reg3>, <disp23>[r<reg1>]"
1968 {
1969 unsigned32 addr = GR[reg1] + disp23;
1970 store_data_mem (sd, addr, 4, GR[reg3]);
1971 TRACE_ST (addr, GR[reg3]);
1972 }
1973
1974
1975 // STSR
1976 rrrrr,111111,regID + 0000000001000000:IX:::stsr
1977 "stsr s<regID>, r<reg2>"
1978 {
1979 uint32 sreg = 0;
1980
1981 if ((idecode_issue == idecode_v850e2_issue
1982 || idecode_issue == idecode_v850e2v3_issue)
1983 && regID < 28)
1984 {
1985 switch (BSEL & 0xffff)
1986 {
1987 case 0x0000:
1988 case 0xff00: /* USER 0 */
1989 case 0xffff: /* USER 1 */
1990 sreg = SR[regID];
1991 break;
1992 case 0x1000:
1993 sreg = MPU0_SR[regID];
1994 break;
1995 case 0x1001:
1996 sreg = MPU1_SR[regID];
1997 break;
1998 case 0x2000:
1999 if (regID == FPST_REGNO)
2000 {
2001 sreg = ((FPSR & FPSR_PR) ? FPST_PR : 0)
2002 | ((FPSR & FPSR_XCE) ? FPST_XCE : 0)
2003 | ((FPSR & FPSR_XCV) ? FPST_XCV : 0)
2004 | ((FPSR & FPSR_XCZ) ? FPST_XCZ : 0)
2005 | ((FPSR & FPSR_XCO) ? FPST_XCO : 0)
2006 | ((FPSR & FPSR_XCU) ? FPST_XCU : 0)
2007 | ((FPSR & FPSR_XCI) ? FPST_XCI : 0)
2008 | ((FPSR & FPSR_XPV) ? FPST_XPV : 0)
2009 | ((FPSR & FPSR_XPZ) ? FPST_XPZ : 0)
2010 | ((FPSR & FPSR_XPO) ? FPST_XPO : 0)
2011 | ((FPSR & FPSR_XPU) ? FPST_XPU : 0)
2012 | ((FPSR & FPSR_XPI) ? FPST_XPI : 0);
2013 }
2014 else if (regID == FPCFG_REGNO)
2015 {
2016 sreg = (((FPSR & FPSR_RM) >> 18) << 7)
2017 | ((FPSR & FPSR_XEV) ? FPCFG_XEV : 0)
2018 | ((FPSR & FPSR_XEZ) ? FPCFG_XEZ : 0)
2019 | ((FPSR & FPSR_XEO) ? FPCFG_XEO : 0)
2020 | ((FPSR & FPSR_XEU) ? FPCFG_XEU : 0)
2021 | ((FPSR & FPSR_XEI) ? FPCFG_XEI : 0);
2022 }
2023 else
2024 {
2025 sreg = FPU_SR[regID];
2026 }
2027 break;
2028 }
2029 }
2030 else
2031 {
2032 sreg = SR[regID];
2033 }
2034
2035 TRACE_ALU_INPUT1 (sreg);
2036 GR[reg2] = sreg;
2037 TRACE_ALU_RESULT (GR[reg2]);
2038 }
2039
2040 // SUB
2041 rrrrr,001101,RRRRR:I:::sub
2042 "sub r<reg1>, r<reg2>"
2043 {
2044 COMPAT_1 (OP_1A0 ());
2045 }
2046
2047 // SUBR
2048 rrrrr,001100,RRRRR:I:::subr
2049 "subr r<reg1>, r<reg2>"
2050 {
2051 COMPAT_1 (OP_180 ());
2052 }
2053
2054 // SWITCH
2055 00000000010,RRRRR:I:::switch
2056 *v850e
2057 *v850e1
2058 *v850e2
2059 *v850e2v3
2060 "switch r<reg1>"
2061 {
2062 unsigned long adr;
2063 SAVE_1;
2064 trace_input ("switch", OP_REG, 0);
2065 adr = (cia + 2) + (State.regs[ reg1 ] << 1);
2066 nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
2067 trace_output (OP_REG);
2068 }
2069
2070 // SXB
2071 00000000101,RRRRR:I:::sxb
2072 *v850e
2073 *v850e1
2074 *v850e2
2075 *v850e2v3
2076 "sxb r<reg1>"
2077 {
2078 TRACE_ALU_INPUT1 (GR[reg1]);
2079 GR[reg1] = EXTEND8 (GR[reg1]);
2080 TRACE_ALU_RESULT (GR[reg1]);
2081 }
2082
2083 // SXH
2084 00000000111,RRRRR:I:::sxh
2085 *v850e
2086 *v850e1
2087 *v850e2
2088 *v850e2v3
2089 "sxh r<reg1>"
2090 {
2091 TRACE_ALU_INPUT1 (GR[reg1]);
2092 GR[reg1] = EXTEND16 (GR[reg1]);
2093 TRACE_ALU_RESULT (GR[reg1]);
2094 }
2095
2096 // TRAP
2097 00000111111,iiiii + 0000000100000000:X:::trap
2098 "trap <vector>"
2099 {
2100 COMPAT_2 (OP_10007E0 ());
2101 }
2102
2103 // TST
2104 rrrrr,001011,RRRRR:I:::tst
2105 "tst r<reg1>, r<reg2>"
2106 {
2107 COMPAT_1 (OP_160 ());
2108 }
2109
2110 // TST1
2111 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
2112 "tst1 <bit3>, <disp16>[r<reg1>]"
2113 {
2114 COMPAT_2 (OP_C7C0 ());
2115 }
2116
2117 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
2118 *v850e
2119 *v850e1
2120 *v850e2
2121 *v850e2v3
2122 "tst1 r<reg2>, [r<reg1>]"
2123 {
2124 COMPAT_2 (OP_E607E0 ());
2125 }
2126
2127 // XOR
2128 rrrrr,001001,RRRRR:I:::xor
2129 "xor r<reg1>, r<reg2>"
2130 {
2131 COMPAT_1 (OP_120 ());
2132 }
2133
2134 // XORI
2135 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
2136 "xori <uimm16>, r<reg1>, r<reg2>"
2137 {
2138 COMPAT_2 (OP_6A0 ());
2139 }
2140
2141 // ZXB
2142 00000000100,RRRRR:I:::zxb
2143 *v850e
2144 *v850e1
2145 *v850e2
2146 *v850e2v3
2147 "zxb r<reg1>"
2148 {
2149 TRACE_ALU_INPUT1 (GR[reg1]);
2150 GR[reg1] = GR[reg1] & 0xff;
2151 TRACE_ALU_RESULT (GR[reg1]);
2152 }
2153
2154 // ZXH
2155 00000000110,RRRRR:I:::zxh
2156 *v850e
2157 *v850e1
2158 *v850e2
2159 *v850e2v3
2160 "zxh r<reg1>"
2161 {
2162 TRACE_ALU_INPUT1 (GR[reg1]);
2163 GR[reg1] = GR[reg1] & 0xffff;
2164 TRACE_ALU_RESULT (GR[reg1]);
2165 }
2166
2167 // Right field must be zero so that it doesn't clash with DIVH
2168 // Left field must be non-zero so that it doesn't clash with SWITCH
2169 11111,000010,00000:I:::break
2170 *v850
2171 *v850e
2172 {
2173 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
2174 }
2175
2176 11111,000010,00000:I:::dbtrap
2177 *v850e1
2178 *v850e2
2179 *v850e2v3
2180 "dbtrap"
2181 {
2182 if (STATE_OPEN_KIND (SD) == SIM_OPEN_DEBUG)
2183 {
2184 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
2185 }
2186 else
2187 {
2188 DBPC = cia + 2;
2189 DBPSW = PSW;
2190 PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
2191 PC = 0x00000060;
2192 nia = 0x00000060;
2193 TRACE_BRANCH0 ();
2194 }
2195 }
2196
2197 // New breakpoint: 0x7E0 0x7E0
2198 00000,111111,00000 + 00000,11111,100000:X:::ilgop
2199 {
2200 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
2201 }
2202
2203 // Return from debug trap: 0x146007e0
2204 0000011111100000 + 0000000101000110:X:::dbret
2205 *v850e1
2206 *v850e2
2207 *v850e2v3
2208 "dbret"
2209 {
2210 nia = DBPC;
2211 PSW = DBPSW;
2212 TRACE_BRANCH1 (PSW);
2213 }
2214
2215
2216 //
2217 // FLOAT
2218 //
2219
2220 // Map condition code to a string
2221 :%s::::FFFF:int FFFF
2222 {
2223 switch (FFFF)
2224 {
2225 case 0: return "f";
2226 case 1: return "un";
2227 case 2: return "eq";
2228 case 3: return "ueq";
2229 case 4: return "olt";
2230 case 5: return "ult";
2231 case 6: return "ole";
2232 case 7: return "ule";
2233 case 8: return "sf";
2234 case 9: return "ngle";
2235 case 10: return "seq";
2236 case 11: return "ngl";
2237 case 12: return "lt";
2238 case 13: return "nge";
2239 case 14: return "le";
2240 case 15: return "ngt";
2241 }
2242 return "(null)";
2243 }
2244
2245 // ABSF.D
2246 rrrr,011111100000 + wwww,010001011000:F_I:::absf_d
2247 *v850e2v3
2248 "absf.d r<reg2e>, r<reg3e>"
2249 {
2250 sim_fpu ans, wop;
2251 sim_fpu_status status;
2252
2253 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
2254 TRACE_FP_INPUT_FPU1 (&wop);
2255
2256 status = sim_fpu_abs (&ans, &wop);
2257 check_invalid_snan(sd, status, 1);
2258
2259 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
2260
2261 TRACE_FP_RESULT_FPU1 (&ans);
2262 }
2263
2264 // ABSF.S
2265 rrrrr,11111100000 + wwwww,10001001000:F_I:::absf_s
2266 *v850e2v3
2267 "absf.s r<reg2>, r<reg3>"
2268 {
2269 sim_fpu ans, wop;
2270 sim_fpu_status status;
2271
2272 sim_fpu_32to (&wop, GR[reg2]);
2273 TRACE_FP_INPUT_FPU1 (&wop);
2274
2275 status = sim_fpu_abs (&ans, &wop);
2276 check_invalid_snan(sd, status, 0);
2277
2278 sim_fpu_to32 (&GR[reg3], &ans);
2279 TRACE_FP_RESULT_FPU1 (&ans);
2280 }
2281
2282 // ADDF.D
2283 rrrr,0111111,RRRR,0 + wwww,010001110000:F_I:::addf_d
2284 *v850e2v3
2285 "addf.d r<reg1e>, r<reg2e>, r<reg3e>"
2286 {
2287 sim_fpu ans, wop1, wop2;
2288 sim_fpu_status status;
2289
2290 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2291 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2292 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2293
2294 status = sim_fpu_add (&ans, &wop1, &wop2);
2295 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2296
2297 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
2298
2299 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
2300 TRACE_FP_RESULT_FPU1 (&ans);
2301 }
2302
2303 // ADDF.S
2304 rrrrr,111111,RRRRR + wwwww,10001100000:F_I:::addf_s
2305 *v850e2v3
2306 "addf.s r<reg1>, r<reg2>, r<reg3>"
2307 {
2308 sim_fpu ans, wop1, wop2;
2309 sim_fpu_status status;
2310
2311 sim_fpu_32to (&wop1, GR[reg1]);
2312 sim_fpu_32to (&wop2, GR[reg2]);
2313 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2314
2315 status = sim_fpu_add (&ans, &wop1, &wop2);
2316 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2317
2318 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
2319
2320 sim_fpu_to32 (&GR[reg3], &ans);
2321 TRACE_FP_RESULT_FPU1 (&ans);
2322 }
2323
2324 // CMOVF.D
2325 rrrr,0111111,RRRR,0 + wwww!0,01000001,bbb,0:F_I:::cmovf_d
2326 *v850e2v3
2327 "cmovf.d <bbb>, r<reg1e>, r<reg2e>, r<reg3e>"
2328 {
2329 unsigned int ophi,oplow;
2330 sim_fpu ans, wop1, wop2;
2331
2332 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2333 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2334 TRACE_FP_INPUT_BOOL1_FPU2 (TEST_FPCC(bbb), &wop1, &wop2);
2335
2336 if (TEST_FPCC(bbb))
2337 {
2338 ophi = GR[reg1e+1];
2339 oplow = GR[reg1e];
2340 ans = wop1;
2341 }
2342 else
2343 {
2344 ophi = GR[reg2e+1];
2345 oplow = GR[reg2e];
2346 ans = wop2;
2347 }
2348
2349 GR[reg3e+1] = ophi;
2350 GR[reg3e] = oplow;
2351 TRACE_FP_RESULT_FPU1 (&ans);;
2352 }
2353
2354 // CMOVF.S
2355 rrrrr,111111,RRRRR!0 + wwwww!0,1000000,bbb,0:F_I:::cmovf_s
2356 *v850e2v3
2357 "cmovf.d <bbb>, r<reg1>, r<reg2>, r<reg3>"
2358 {
2359 unsigned int op;
2360 sim_fpu ans, wop1, wop2;
2361
2362 sim_fpu_32to (&wop1, GR[reg1]);
2363 sim_fpu_32to (&wop2, GR[reg2]);
2364 TRACE_FP_INPUT_BOOL1_FPU2 (TEST_FPCC(bbb), &wop1, &wop2);
2365
2366 if (TEST_FPCC(bbb))
2367 {
2368 op = GR[reg1];
2369 ans = wop1;
2370 }
2371 else
2372 {
2373 op = GR[reg2];
2374 ans = wop2;
2375 }
2376
2377 GR[reg3] = op;
2378 TRACE_FP_RESULT_FPU1 (&ans);
2379 }
2380
2381 // CMPF.D
2382 rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d
2383 *v850e2v3
2384 "cmpf.d %s<FFFF>, r<reg2e>, r<reg1e>":(bbb == 0)
2385 "cmpf.d %s<FFFF>, r<reg2e>, r<reg1e>, <bbb>"
2386 {
2387 int result;
2388 sim_fpu wop1;
2389 sim_fpu wop2;
2390
2391 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2392 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2393 TRACE_FP_INPUT_FPU2 (&wop2, &wop1);
2394
2395 result = v850_float_compare(sd, FFFF, wop2, wop1, 1);
2396
2397 if (result)
2398 SET_FPCC(bbb);
2399 else
2400 CLEAR_FPCC(bbb);
2401
2402 TRACE_FP_RESULT_BOOL (result);
2403 }
2404
2405 // CMPF.S
2406 rrrrr,111111,RRRRR + 0,FFFF,1000010,bbb,0:F_I:::cmpf_s
2407 *v850e2v3
2408 "cmpf.s %s<FFFF>, r<reg2>, r<reg1>":(bbb == 0)
2409 "cmpf.s %s<FFFF>, r<reg2>, r<reg1>, <bbb>"
2410 {
2411 int result;
2412 sim_fpu wop1;
2413 sim_fpu wop2;
2414
2415 sim_fpu_32to( &wop1, GR[reg1] );
2416 sim_fpu_32to( &wop2, GR[reg2] );
2417 TRACE_FP_INPUT_FPU2 (&wop2, &wop1);
2418
2419 result = v850_float_compare(sd, FFFF, wop2, wop1, 0);
2420
2421 if (result)
2422 SET_FPCC(bbb);
2423 else
2424 CLEAR_FPCC(bbb);
2425
2426 TRACE_FP_RESULT_BOOL (result);
2427 }
2428
2429 // CVTF.DL
2430 rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl
2431 *v850e2v3
2432 "cvtf.dl r<reg2e>, r<reg3e>"
2433 {
2434 unsigned64 ans;
2435 sim_fpu wop;
2436 sim_fpu_status status;
2437
2438 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
2439 TRACE_FP_INPUT_FPU1 (&wop);
2440
2441 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2442 status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND());
2443
2444 check_cvt_fi(sd, status, 1);
2445
2446 GR[reg3e] = ans;
2447 GR[reg3e+1] = ans>>32L;
2448 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
2449 }
2450
2451 // CVTF.DS
2452 rrrr,011111100011 + wwwww,10001010010:F_I:::cvtf_ds
2453 *v850e2v3
2454 "cvtf.ds r<reg2e>, r<reg3>"
2455 {
2456 sim_fpu wop;
2457 sim_fpu_status status;
2458
2459 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
2460 TRACE_FP_INPUT_FPU1 (&wop);
2461
2462 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2463
2464 check_cvt_fi(sd, status, 0);
2465
2466 sim_fpu_to32 (&GR[reg3], &wop);
2467 TRACE_FP_RESULT_FPU1 (&wop);
2468 }
2469
2470 // CVTF.DW
2471 rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw
2472 *v850e2v3
2473 "cvtf.dw r<reg2e>, r<reg3>"
2474 {
2475 uint32 ans;
2476 sim_fpu wop;
2477 sim_fpu_status status;
2478
2479 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
2480 TRACE_FP_INPUT_FPU1 (&wop);
2481
2482 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2483 status |= sim_fpu_to32i (&ans, &wop, FPSR_GET_ROUND());
2484
2485 check_cvt_fi(sd, status, 1);
2486
2487 GR[reg3] = ans;
2488 TRACE_FP_RESULT_WORD1 (ans);
2489 }
2490
2491 // CVTF.LD
2492 rrrr,011111100001 + wwww,010001010010:F_I:::cvtf_ld
2493 *v850e2v3
2494 "cvtf.ld r<reg2e>, r<reg3e>"
2495 {
2496 signed64 op;
2497 sim_fpu wop;
2498 sim_fpu_status status;
2499
2500 op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e];
2501 TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]);
2502
2503 sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
2504 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2505
2506 check_cvt_if(sd, status, 1);
2507
2508 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
2509 TRACE_FP_RESULT_FPU1 (&wop);
2510 }
2511
2512 // CVTF.LS
2513 rrrr,011111100001 + wwwww,10001000010:F_I:::cvtf_ls
2514 *v850e2v3
2515 "cvtf.ls r<reg2e>, r<reg3>"
2516 {
2517 signed64 op;
2518 sim_fpu wop;
2519 sim_fpu_status status;
2520
2521 op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e];
2522 TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]);
2523
2524 sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
2525 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2526
2527 check_cvt_if(sd, status, 0);
2528
2529 sim_fpu_to32 (&GR[reg3], &wop);
2530 TRACE_FP_RESULT_FPU1 (&wop);
2531 }
2532
2533 // CVTF.SD
2534 rrrrr,11111100010 + wwww,010001010010:F_I:::cvtf_sd
2535 *v850e2v3
2536 "cvtf.sd r<reg2>, r<reg3e>"
2537 {
2538 sim_fpu wop;
2539 sim_fpu_status status;
2540
2541 sim_fpu_32to (&wop, GR[reg2]);
2542 TRACE_FP_INPUT_FPU1 (&wop);
2543 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2544
2545 check_cvt_ff(sd, status, 1);
2546
2547 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
2548 TRACE_FP_RESULT_FPU1 (&wop);
2549 }
2550
2551 // CVTF.SL
2552 rrrrr,11111100100 + wwww,010001000100:F_I:::cvtf_sl
2553 *v850e2v3
2554 "cvtf.sl r<reg2>, r<reg3e>"
2555 {
2556 signed64 ans;
2557 sim_fpu wop;
2558 sim_fpu_status status;
2559
2560 sim_fpu_32to (&wop, GR[reg2]);
2561 TRACE_FP_INPUT_FPU1 (&wop);
2562
2563 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2564 status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND());
2565
2566 check_cvt_fi(sd, status, 0);
2567
2568 GR[reg3e] = ans;
2569 GR[reg3e+1] = ans >> 32L;
2570 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
2571 }
2572
2573 // CVTF.SW
2574 rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw
2575 *v850e2v3
2576 "cvtf.sw r<reg2>, r<reg3>"
2577 {
2578 uint32 ans;
2579 sim_fpu wop;
2580 sim_fpu_status status;
2581
2582 sim_fpu_32to (&wop, GR[reg2]);
2583 TRACE_FP_INPUT_FPU1 (&wop);
2584
2585 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2586 status |= sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
2587
2588 check_cvt_fi(sd, status, 0);
2589
2590 GR[reg3] = ans;
2591 TRACE_FP_RESULT_WORD1 (ans);
2592 }
2593
2594 // CVTF.WD
2595 rrrrr,11111100000 + wwww,010001010010:F_I:::cvtf_wd
2596 *v850e2v3
2597 "cvtf.wd r<reg2>, r<reg3e>"
2598 {
2599 sim_fpu wop;
2600 sim_fpu_status status;
2601
2602 TRACE_FP_INPUT_WORD1 (GR[reg2]);
2603 sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND());
2604 status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2605
2606 check_cvt_if(sd, status, 1);
2607
2608 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
2609 TRACE_FP_RESULT_FPU1 (&wop);
2610 }
2611
2612 // CVTF.WS
2613 rrrrr,11111100000 + wwwww,10001000010:F_I:::cvtf_ws
2614 *v850e2v3
2615 "cvtf.ws r<reg2>, r<reg3>"
2616 {
2617 sim_fpu wop;
2618 sim_fpu_status status;
2619
2620 TRACE_FP_INPUT_WORD1 (GR[reg2]);
2621 sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND());
2622 status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
2623
2624 check_cvt_if(sd, status, 0);
2625
2626 sim_fpu_to32 (&GR[reg3], &wop);
2627 TRACE_FP_RESULT_FPU1 (&wop);
2628 }
2629
2630 // DIVF.D
2631 rrrr,0111111,RRRR,0 + wwww,010001111110:F_I:::divf_d
2632 *v850e2v3
2633 "divf.d r<reg1e>, r<reg2e>, r<reg3e>"
2634 {
2635 sim_fpu ans, wop1, wop2;
2636 sim_fpu_status status;
2637
2638 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2639 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2640 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2641
2642 status = sim_fpu_div (&ans, &wop2, &wop1);
2643 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2644
2645 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
2646
2647 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
2648 TRACE_FP_RESULT_FPU1 (&ans);
2649 }
2650
2651 // DIVF.S
2652 rrrrr,111111,RRRRR + wwwww,10001101110:F_I:::divf_s
2653 *v850e2v3
2654 "divf.s r<reg1>, r<reg2>, r<reg3>"
2655 {
2656 sim_fpu ans, wop1, wop2;
2657 sim_fpu_status status;
2658
2659 sim_fpu_32to (&wop1, GR[reg1]);
2660 sim_fpu_32to (&wop2, GR[reg2]);
2661 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2662
2663 status = sim_fpu_div (&ans, &wop2, &wop1);
2664 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2665
2666 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
2667
2668 sim_fpu_to32 (&GR[reg3], &ans);
2669 TRACE_FP_RESULT_FPU1 (&ans);
2670 }
2671
2672 // MADDF.S
2673 rrrrr,111111,RRRRR + wwwww,101,W,00,WWWW,0:F_I:::maddf_s
2674 *v850e2v3
2675 "maddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
2676 {
2677 sim_fpu ans, wop1, wop2, wop3;
2678 sim_fpu_status status;
2679
2680 sim_fpu_32to (&wop1, GR[reg1]);
2681 sim_fpu_32to (&wop2, GR[reg2]);
2682 sim_fpu_32to (&wop3, GR[reg3]);
2683 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
2684
2685 status = sim_fpu_mul (&ans, &wop1, &wop2);
2686 wop1 = ans;
2687 status |= sim_fpu_add (&ans, &wop1, &wop3);
2688 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2689
2690 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
2691
2692 sim_fpu_to32 (&GR[reg4], &ans);
2693 TRACE_FP_RESULT_FPU1 (&ans);
2694 }
2695
2696 // MAXF.D
2697 rrrr,0111111,RRRR,0 + wwww,010001111000:F_I:::maxf_d
2698 *v850e2v3
2699 "maxf.d r<reg1e>, r<reg2e>, r<reg3e>"
2700 {
2701 sim_fpu ans, wop1, wop2;
2702
2703 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2704 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2705 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2706
2707 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
2708 {
2709 if (FPSR & FPSR_XEV)
2710 {
2711 SignalExceptionFPE(sd, 1);
2712 }
2713 else
2714 {
2715 ans = sim_fpu_qnan;
2716 }
2717 }
2718 else if (FPSR & FPSR_FS
2719 && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1))
2720 && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2))))
2721 {
2722 ans = sim_fpu_zero;
2723 }
2724 else
2725 {
2726 sim_fpu_max (&ans, &wop1, &wop2);
2727 }
2728
2729 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
2730 TRACE_FP_RESULT_FPU1 (&ans);
2731 }
2732
2733 // MAXF.S
2734 rrrrr,111111,RRRRR + wwwww,10001101000:F_I:::maxf_s
2735 *v850e2v3
2736 "maxf.s r<reg1>, r<reg2>, r<reg3>"
2737 {
2738 sim_fpu ans, wop1, wop2;
2739
2740 sim_fpu_32to (&wop1, GR[reg1]);
2741 sim_fpu_32to (&wop2, GR[reg2]);
2742 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2743
2744 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
2745 {
2746 if (FPSR & FPSR_XEV)
2747 {
2748 SignalExceptionFPE(sd, 0);
2749 }
2750 else
2751 {
2752 ans = sim_fpu_qnan;
2753 }
2754 }
2755 else if ((FPSR & FPSR_FS)
2756 && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1))
2757 && (sim_fpu_is_zero (&wop2)|| sim_fpu_is_denorm (&wop2))))
2758 {
2759 ans = sim_fpu_zero;
2760 }
2761 else
2762 {
2763 sim_fpu_max (&ans, &wop1, &wop2);
2764 }
2765
2766 sim_fpu_to32 (&GR[reg3], &ans);
2767 TRACE_FP_RESULT_FPU1 (&ans);
2768 }
2769
2770 // MINF.D
2771 rrrr,0111111,RRRR,0 + wwww,010001111010:F_I:::minf_d
2772 *v850e2v3
2773 "minf.d r<reg1e>, r<reg2e>, r<reg3e>"
2774 {
2775 sim_fpu ans, wop1, wop2;
2776
2777 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2778 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2779 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2780
2781 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
2782 {
2783 if (FPSR & FPSR_XEV)
2784 {
2785 SignalExceptionFPE(sd, 1);
2786 }
2787 else
2788 {
2789 ans = sim_fpu_qnan;
2790 }
2791 }
2792 else if (FPSR & FPSR_FS
2793 && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1))
2794 && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2))))
2795 {
2796 ans = sim_fpu_zero;
2797 }
2798 else
2799 {
2800 sim_fpu_min (&ans, &wop1, &wop2);
2801 }
2802
2803 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
2804 TRACE_FP_RESULT_FPU1 (&ans);
2805 }
2806
2807 // MINF.S
2808 rrrrr,111111,RRRRR + wwwww,10001101010:F_I:::minf_s
2809 *v850e2v3
2810 "minf.s r<reg1>, r<reg2>, r<reg3>"
2811 {
2812 sim_fpu ans, wop1, wop2;
2813
2814 sim_fpu_32to (&wop1, GR[reg1]);
2815 sim_fpu_32to (&wop2, GR[reg2]);
2816 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2817
2818 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
2819 {
2820 if (FPSR & FPSR_XEV)
2821 {
2822 SignalExceptionFPE(sd, 0);
2823 }
2824 else
2825 {
2826 ans = sim_fpu_qnan;
2827 }
2828 }
2829 else if (FPSR & FPSR_FS
2830 && ((sim_fpu_is_zero (&wop1) || sim_fpu_is_denorm (&wop1))
2831 && (sim_fpu_is_zero (&wop2) || sim_fpu_is_denorm (&wop2))))
2832 {
2833 ans = sim_fpu_zero;
2834 }
2835 else
2836 {
2837 sim_fpu_min (&ans, &wop1, &wop2);
2838 }
2839
2840 sim_fpu_to32 (&GR[reg3], &ans);
2841 TRACE_FP_RESULT_FPU1 (&ans);
2842 }
2843
2844 // MSUBF.S
2845 rrrrr,111111,RRRRR + wwwww,101,W,01,WWWW,0:F_I:::msubf_s
2846 *v850e2v3
2847 "msubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
2848 {
2849 sim_fpu ans, wop1, wop2, wop3;
2850 sim_fpu_status status;
2851
2852 sim_fpu_32to (&wop1, GR[reg1]);
2853 sim_fpu_32to (&wop2, GR[reg2]);
2854 sim_fpu_32to (&wop3, GR[reg3]);
2855 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
2856
2857 status = sim_fpu_mul (&ans, &wop1, &wop2);
2858 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2859 wop1 = ans;
2860 status |= sim_fpu_sub (&ans, &wop1, &wop3);
2861 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2862
2863 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
2864
2865 sim_fpu_to32 (&GR[reg4], &ans);
2866 TRACE_FP_RESULT_FPU1 (&ans);
2867 }
2868
2869 // MULF.D
2870 rrrr,0111111,RRRR,0 + wwww,010001110100:F_I:::mulf_d
2871 *v850e2v3
2872 "mulf.d r<reg1e>, r<reg2e>, r<reg3e>"
2873 {
2874 sim_fpu ans, wop1, wop2;
2875 sim_fpu_status status;
2876
2877 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
2878 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
2879 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2880
2881 status = sim_fpu_mul (&ans, &wop1, &wop2);
2882 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2883
2884 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
2885
2886 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
2887 TRACE_FP_RESULT_FPU1 (&ans);
2888 }
2889
2890 // MULF.S
2891 rrrrr,111111,RRRRR + wwwww,10001100100:F_I:::mulf_s
2892 *v850e2v3
2893 "mulf.s r<reg1>, r<reg2>, r<reg3>"
2894 {
2895 sim_fpu ans, wop1, wop2;
2896 sim_fpu_status status;
2897
2898 sim_fpu_32to (&wop1, GR[reg1]);
2899 sim_fpu_32to (&wop2, GR[reg2]);
2900 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
2901
2902 status = sim_fpu_mul (&ans, &wop1, &wop2);
2903 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2904
2905 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
2906
2907 sim_fpu_to32 (&GR[reg3], &ans);
2908 TRACE_FP_RESULT_FPU1 (&ans);
2909 }
2910
2911 // NEGF.D
2912 rrrr,011111100001 + wwww,010001011000:F_I:::negf_d
2913 *v850e2v3
2914 "negf.d r<reg2e>, r<reg3e>"
2915 {
2916 sim_fpu ans, wop;
2917 sim_fpu_status status;
2918
2919 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
2920 TRACE_FP_INPUT_FPU1 (&wop);
2921
2922 status = sim_fpu_neg (&ans, &wop);
2923
2924 check_invalid_snan(sd, status, 1);
2925
2926 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
2927 TRACE_FP_RESULT_FPU1 (&ans);
2928 }
2929
2930 // NEGF.S
2931 rrrrr,11111100001 + wwwww,10001001000:F_I:::negf_s
2932 *v850e2v3
2933 "negf.s r<reg2>, r<reg3>"
2934 {
2935 sim_fpu ans, wop;
2936 sim_fpu_status status;
2937
2938 sim_fpu_32to (&wop, GR[reg2]);
2939 TRACE_FP_INPUT_FPU1 (&wop);
2940
2941 status = sim_fpu_neg (&ans, &wop);
2942
2943 check_invalid_snan(sd, status, 0);
2944
2945 sim_fpu_to32 (&GR[reg3], &ans);
2946 TRACE_FP_RESULT_FPU1 (&ans);
2947 }
2948
2949 // NMADDF.S
2950 rrrrr,111111,RRRRR + wwwww,101,W,10,WWWW,0:F_I:::nmaddf_s
2951 *v850e2v3
2952 "nmaddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
2953 {
2954 sim_fpu ans, wop1, wop2, wop3;
2955 sim_fpu_status status;
2956
2957 sim_fpu_32to (&wop1, GR[reg1]);
2958 sim_fpu_32to (&wop2, GR[reg2]);
2959 sim_fpu_32to (&wop3, GR[reg3]);
2960 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
2961
2962 status = sim_fpu_mul (&ans, &wop1, &wop2);
2963 wop1 = ans;
2964 status |= sim_fpu_add (&ans, &wop1, &wop3);
2965 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2966 wop1 = ans;
2967 status |= sim_fpu_neg (&ans, &wop1);
2968
2969 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
2970
2971 sim_fpu_to32 (&GR[reg4], &ans);
2972 TRACE_FP_RESULT_FPU1 (&ans);
2973 }
2974
2975 // NMSUBF.S
2976 rrrrr,111111,RRRRR + wwwww,101,W,11,WWWW,0:F_I:::nmsubf_s
2977 *v850e2v3
2978 "nmsubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
2979 {
2980 sim_fpu ans, wop1, wop2, wop3;
2981 sim_fpu_status status;
2982
2983 sim_fpu_32to (&wop1, GR[reg1]);
2984 sim_fpu_32to (&wop2, GR[reg2]);
2985 sim_fpu_32to (&wop3, GR[reg3]);
2986 TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
2987
2988 status = sim_fpu_mul (&ans, &wop1, &wop2);
2989 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2990 wop1 = ans;
2991 status |= sim_fpu_sub (&ans, &wop1, &wop3);
2992 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
2993 wop1 = ans;
2994 status |= sim_fpu_neg (&ans, &wop1);
2995
2996 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
2997
2998 sim_fpu_to32 (&GR[reg4], &ans);
2999 TRACE_FP_RESULT_FPU1 (&ans);
3000 }
3001
3002 // RECIPF.D
3003 rrrr,011111100001 + wwww,010001011110:F_I:::recipf.d
3004 *v850e2v3
3005 "recipf.d r<reg2e>, r<reg3e>"
3006 {
3007 sim_fpu ans, wop;
3008 sim_fpu_status status;
3009
3010 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3011 TRACE_FP_INPUT_FPU1 (&wop);
3012
3013 status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
3014 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3015
3016 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
3017
3018 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
3019 TRACE_FP_RESULT_FPU1 (&ans);
3020 }
3021
3022 // RECIPF.S
3023 rrrrr,11111100001 + wwwww,10001001110:F_I:::recipf.s
3024 *v850e2v3
3025 "recipf.s r<reg2>, r<reg3>"
3026 {
3027 sim_fpu ans, wop;
3028 sim_fpu_status status;
3029
3030 sim_fpu_32to (&wop, GR[reg2]);
3031 TRACE_FP_INPUT_FPU1 (&wop);
3032
3033 status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
3034 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3035
3036 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3037
3038 sim_fpu_to32 (&GR[reg3], &ans);
3039 TRACE_FP_RESULT_FPU1 (&ans);
3040 }
3041
3042 // RSQRTF.D
3043 rrrr,011111100010 + wwww,010001011110:F_I:::rsqrtf.d
3044 *v850e2v3
3045 "rsqrtf.d r<reg2e>, r<reg3e>"
3046 {
3047 sim_fpu ans, wop;
3048 sim_fpu_status status;
3049
3050 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3051 TRACE_FP_INPUT_FPU1 (&wop);
3052
3053 status = sim_fpu_sqrt (&ans, &wop);
3054 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3055 wop = ans;
3056 status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
3057 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3058
3059 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
3060
3061 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
3062 TRACE_FP_RESULT_FPU1 (&ans);
3063 }
3064
3065 // RSQRTF.S
3066 rrrrr,11111100010 + wwwww,10001001110:F_I:::rsqrtf.s
3067 *v850e2v3
3068 "rsqrtf.s r<reg2>, r<reg3>"
3069 {
3070 sim_fpu ans, wop;
3071 sim_fpu_status status;
3072
3073 sim_fpu_32to (&wop, GR[reg2]);
3074 TRACE_FP_INPUT_FPU1 (&wop);
3075
3076 status = sim_fpu_sqrt (&ans, &wop);
3077 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3078 wop = ans;
3079 status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
3080 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3081
3082 update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3083
3084 sim_fpu_to32 (&GR[reg3], &ans);
3085 TRACE_FP_RESULT_FPU1 (&ans);
3086 }
3087
3088 // SQRTF.D
3089 rrrr,011111100000 + wwww,010001011110:F_I:::sqrtf.d
3090 *v850e2v3
3091 "sqrtf.d r<reg2e>, r<reg3e>"
3092 {
3093 sim_fpu ans, wop;
3094 sim_fpu_status status;
3095
3096 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3097 TRACE_FP_INPUT_FPU1 (&wop);
3098
3099 status = sim_fpu_sqrt (&ans, &wop);
3100 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3101
3102 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 1);
3103
3104 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
3105 TRACE_FP_RESULT_FPU1 (&ans);
3106 }
3107
3108 // SQRTF.S
3109 rrrrr,11111100000 + wwwww,10001001110:F_I:::sqrtf.s
3110 *v850e2v3
3111 "sqrtf.s r<reg2>, r<reg3>"
3112 {
3113 sim_fpu ans, wop;
3114 sim_fpu_status status;
3115
3116 sim_fpu_32to (&wop, GR[reg2]);
3117 TRACE_FP_INPUT_FPU1 (&wop);
3118
3119 status = sim_fpu_sqrt (&ans, &wop);
3120 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3121
3122 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 0);
3123
3124 sim_fpu_to32 (&GR[reg3], &ans);
3125 TRACE_FP_RESULT_FPU1 (&ans);
3126 }
3127
3128 // SUBF.D
3129 rrrr,0111111,RRRR,0 + wwww,010001110010:F_I:::subf.d
3130 *v850e2v3
3131 "subf.d r<reg1e>, r<reg2e>, r<reg3e>"
3132 {
3133 sim_fpu ans, wop1, wop2;
3134 sim_fpu_status status;
3135
3136 sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
3137 sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
3138 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
3139
3140 status = sim_fpu_sub (&ans, &wop2, &wop1);
3141 status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3142
3143 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
3144
3145 sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
3146 TRACE_FP_RESULT_FPU1 (&ans);
3147 }
3148
3149 // SUBF.S
3150 rrrrr,111111,RRRRR + wwwww,10001100010:F_I:::subf.s
3151 *v850e2v3
3152 "subf.s r<reg1>, r<reg2>, r<reg3>"
3153 {
3154 sim_fpu ans, wop1, wop2;
3155 sim_fpu_status status;
3156
3157 sim_fpu_32to (&wop1, GR[reg1]);
3158 sim_fpu_32to (&wop2, GR[reg2]);
3159 TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
3160
3161 status = sim_fpu_sub (&ans, &wop2, &wop1);
3162 status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
3163
3164 update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
3165
3166 sim_fpu_to32 (&GR[reg3], &ans);
3167 TRACE_FP_RESULT_FPU1 (&ans);
3168 }
3169
3170 // TRFSR
3171 0000011111100000 + 000001000000,bbb,0:F_I:::trfsr
3172 *v850e2v3
3173 "trfsr":(bbb == 0)
3174 "trfsr <bbb>"
3175 {
3176 TRACE_ALU_INPUT1 (GET_FPCC());
3177
3178 if (TEST_FPCC (bbb))
3179 PSW |= PSW_Z;
3180 else
3181 PSW &= ~PSW_Z;
3182
3183 TRACE_ALU_RESULT1 (PSW);
3184 }
3185
3186 // TRNCF.DL
3187 rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl
3188 *v850e2v3
3189 "trncf.dl r<reg2e>, r<reg3e>"
3190 {
3191 signed64 ans;
3192 sim_fpu wop;
3193 sim_fpu_status status;
3194
3195 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3196 TRACE_FP_INPUT_FPU1 (&wop);
3197
3198 status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero);
3199
3200 check_cvt_fi(sd, status, 1);
3201
3202 GR[reg3e] = ans;
3203 GR[reg3e+1] = ans>>32L;
3204 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
3205 }
3206
3207 // TRNCF.DUL
3208 rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul
3209 *v850e2v3
3210 "trncf.dul r<reg2e>, r<reg3e>"
3211 {
3212 signed64 ans;
3213 sim_fpu wop;
3214 sim_fpu_status status;
3215
3216 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3217 TRACE_FP_INPUT_FPU1 (&wop);
3218
3219 status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
3220
3221 check_cvt_fi(sd, status, 1);
3222
3223 GR[reg3e] = ans;
3224 GR[reg3e+1] = ans>>32L;
3225 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
3226 }
3227
3228 // TRNCF.DW
3229 rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw
3230 *v850e2v3
3231 "trncf.dw r<reg2e>, r<reg3>"
3232 {
3233 uint32 ans;
3234 sim_fpu wop;
3235 sim_fpu_status status;
3236
3237 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3238 TRACE_FP_INPUT_FPU1 (&wop);
3239
3240 status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
3241
3242 check_cvt_fi(sd, status, 1);
3243
3244 GR[reg3] = ans;
3245 TRACE_FP_RESULT_WORD1 (ans);
3246 }
3247
3248 // TRNCF.DUW
3249 rrrr,011111110001 + wwwww,10001010000:F_I:::trncf_duw
3250 *v850e2v3
3251 "trncf.duw r<reg2e>, r<reg3>"
3252 {
3253 uint32 ans;
3254 sim_fpu wop;
3255 sim_fpu_status status;
3256
3257 sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
3258 TRACE_FP_INPUT_FPU1 (&wop);
3259
3260 status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
3261
3262 check_cvt_fi(sd, status, 1);
3263
3264 GR[reg3] = ans;
3265 TRACE_FP_RESULT_WORD1 (ans);
3266 }
3267
3268 // TRNCF.SL
3269 rrrrr,11111100001 + wwww,010001000100:F_I:::trncf_sl
3270 *v850e2v3
3271 "trncf.sl r<reg2>, r<reg3e>"
3272 {
3273 signed64 ans;
3274 sim_fpu wop;
3275 sim_fpu_status status;
3276
3277 sim_fpu_32to (&wop, GR[reg2]);
3278 TRACE_FP_INPUT_FPU1 (&wop);
3279
3280 status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero);
3281
3282 GR[reg3e] = ans;
3283 GR[reg3e+1] = ans >> 32L;
3284 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
3285 }
3286
3287 // TRNCF.SUL
3288 rrrrr,11111110001 + wwww,010001000100:F_I:::trncf_sul
3289 *v850e2v3
3290 "trncf.sul r<reg2>, r<reg3e>"
3291 {
3292 signed64 ans;
3293 sim_fpu wop;
3294 sim_fpu_status status;
3295
3296 sim_fpu_32to (&wop, GR[reg2]);
3297 TRACE_FP_INPUT_FPU1 (&wop);
3298
3299 status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
3300
3301 GR[reg3e] = ans;
3302 GR[reg3e+1] = ans >> 32L;
3303 TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
3304 }
3305
3306 // TRNCF.SW
3307 rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw
3308 *v850e2v3
3309 "trncf.sw r<reg2>, r<reg3>"
3310 {
3311 uint32 ans;
3312 sim_fpu wop;
3313 sim_fpu_status status;
3314
3315 sim_fpu_32to (&wop, GR[reg2]);
3316 TRACE_FP_INPUT_FPU1 (&wop);
3317
3318 status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
3319
3320 check_cvt_fi(sd, status, 0);
3321
3322 GR[reg3] = ans;
3323 TRACE_FP_RESULT_WORD1 (ans);
3324 }
3325
3326
3327 // TRNCF.SUW
3328 rrrrr,11111110001 + wwwww,10001000000:F_I:::trncf_suw
3329 *v850e2v3
3330 "trncf.suw r<reg2>, r<reg3>"
3331 {
3332 uint32 ans;
3333 sim_fpu wop;
3334 sim_fpu_status status;
3335
3336 sim_fpu_32to (&wop, GR[reg2]);
3337 TRACE_FP_INPUT_FPU1 (&wop);
3338
3339 status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
3340
3341 check_cvt_fi(sd, status, 0);
3342
3343 GR[reg3] = ans;
3344 TRACE_FP_RESULT_WORD1 (ans);
3345 }