sim/v850/v850.igen

   1 :option::insn-bit-size:16
   2 :option::hi-bit-nr:15
   3
   4
   5 :option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
   6 # start-sanitize-v850e
   7 :option::format-names:XI,XII,XIII
   8 # end-sanitize-v850e
   9 # start-sanitize-v850eq
  10 :option::format-names:XIV,XV
  11 # end-sanitize-v850eq
  12 :option::format-names:Z
  13
  14
  15 :model::v850:v850:
  16
  17 # start-sanitize-v850e
  18 :option::multi-sim:true
  19 :model::v850e:v850e:
  20 # end-sanitize-v850e
  21
  22 # start-sanitize-v850eq
  23 :option::multi-sim:true
  24 :model::v850eq:v850eq:
  25 # end-sanitize-v850eq
  26
  27
  28
  29 // Cache macros
  30
  31 :cache::unsigned:reg1:RRRRR:(RRRRR)
  32 :cache::unsigned:reg2:rrrrr:(rrrrr)
  33 :cache::unsigned:reg3:wwwww:(wwwww)
  34
  35 :cache::unsigned:disp4:dddd:(dddd)
  36 # start-sanitize-v850e
  37 :cache::unsigned:disp5:dddd:(dddd << 1)
  38 # end-sanitize-v850e
  39 :cache::unsigned:disp7:ddddddd:ddddddd
  40 :cache::unsigned:disp8:ddddddd:(ddddddd << 1)
  41 :cache::unsigned:disp8:dddddd:(dddddd << 2)
  42 :cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
  43 :cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
  44 :cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
  45 :cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
  46 :cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
  47
  48 :cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
  49 :cache::unsigned:imm6:iiiiii:iiiiii
  50 :cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
  51 # start-sanitize-v850eq
  52 :cache::unsigned:imm5:iiii:(32 - (iiii << 1))
  53 # end-sanitize-v850eq
  54 :cache::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
  55 :cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  56 :cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
  57 # start-sanitize-v850e
  58 :cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
  59 # end-sanitize-v850e
  60
  61 :cache::unsigned:vector:iiiii:iiiii
  62
  63 # start-sanitize-v850e
  64 :cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
  65 :cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
  66 # end-sanitize-v850e
  67
  68 :cache::unsigned:bit3:bbb:bbb
  69
  70
  71 // What do we do with an illegal instruction?
  72 :internal:::illegal
  73 {
  74   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  75                   (unsigned long) cia);
  76   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  77 }
  78
  79
  80
  81 // Add
  82
  83 rrrrr,001110,RRRRR:I:::add
  84 "add r<reg1>, r<reg2>"
  85 {
  86   COMPAT_1 (OP_1C0 ());
  87 }
  88
  89 rrrrr,010010,iiiii:II:::add
  90 "add <imm5>,r<reg2>"
  91 {
  92   COMPAT_1 (OP_240 ());
  93 }
  94
  95
  96
  97 // ADDI
  98 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
  99 "addi <simm16>, r<reg1>, r<reg2>"
 100 {
 101   COMPAT_2 (OP_600 ());
 102 }
 103
 104
 105
 106 // AND
 107 rrrrr,001010,RRRRR:I:::and
 108 "and r<reg1>, r<reg2>"
 109 {
 110   COMPAT_1 (OP_140 ());
 111 }
 112
 113
 114
 115 // ANDI
 116 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
 117 "andi <uimm16>, r<reg1>, r<reg2>"
 118 {
 119   COMPAT_2 (OP_6C0 ());
 120 }
 121
 122
 123
 124 // Bcond
 125 // ddddd,1011,ddd,cccc:III:::Bcond
 126 // "b<cond> disp9"
 127
 128 ddddd,1011,ddd,0000:III:::bv
 129 "bv <disp9>"
 130 {
 131   COMPAT_1 (OP_580 ());
 132 }
 133
 134 ddddd,1011,ddd,0001:III:::bl
 135 "bl <disp9>"
 136 {
 137   COMPAT_1 (OP_581 ());
 138 }
 139
 140 ddddd,1011,ddd,0010:III:::be
 141 "be <disp9>"
 142 {
 143   COMPAT_1 (OP_582 ());
 144 }
 145
 146 ddddd,1011,ddd,0011:III:::bnh
 147 "bnh <disp9>"
 148 {
 149   COMPAT_1 (OP_583 ());
 150 }
 151
 152 ddddd,1011,ddd,0100:III:::bn
 153 "bn <disp9>"
 154 {
 155   COMPAT_1 (OP_584 ());
 156 }
 157
 158 ddddd,1011,ddd,0101:III:::br
 159 "br <disp9>"
 160 {
 161   COMPAT_1 (OP_585 ());
 162 }
 163
 164 ddddd,1011,ddd,0110:III:::blt
 165 "blt <disp9>"
 166 {
 167   COMPAT_1 (OP_586 ());
 168 }
 169
 170 ddddd,1011,ddd,0111:III:::ble
 171 "ble <disp9>"
 172 {
 173   COMPAT_1 (OP_587 ());
 174 }
 175
 176 ddddd,1011,ddd,1000:III:::bnv
 177 "bnv <disp9>"
 178 {
 179   COMPAT_1 (OP_588 ());
 180 }
 181
 182 ddddd,1011,ddd,1001:III:::bnl
 183 "bnl <disp9>"
 184 {
 185   COMPAT_1 (OP_589 ());
 186 }
 187
 188 ddddd,1011,ddd,1010:III:::bne
 189 "bne <disp9>"
 190 {
 191   COMPAT_1 (OP_58A ());
 192 }
 193
 194 ddddd,1011,ddd,1011:III:::bh
 195 "bh <disp9>"
 196 {
 197   COMPAT_1 (OP_58B ());
 198 }
 199
 200 ddddd,1011,ddd,1100:III:::bp
 201 "bp <disp9>"
 202 {
 203   COMPAT_1 (OP_58C ());
 204 }
 205
 206 ddddd,1011,ddd,1101:III:::bsa
 207 "bsa <disp9>"
 208 {
 209   COMPAT_1 (OP_58D ());
 210 }
 211
 212 ddddd,1011,ddd,1110:III:::bge
 213 "bge <disp9>"
 214 {
 215   COMPAT_1 (OP_58E ());
 216 }
 217
 218 ddddd,1011,ddd,1111:III:::bgt
 219 "bgt <disp9>"
 220 {
 221   COMPAT_1 (OP_58F ());
 222 }
 223
 224
 225
 226 // start-sanitize-v850e
 227 // BSH
 228 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 229 *v850e
 230 // start-sanitize-v850eq
 231 *v850eq
 232 // end-sanitize-v850eq
 233 "bsh r<reg2>, r<reg3>"
 234 {
 235   unsigned32 value;
 236   TRACE_ALU_INPUT1 (GR[reg2]);
 237
 238   value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
 239            | MOVED32 (GR[reg2], 31, 24, 23, 16)
 240            | MOVED32 (GR[reg2], 7, 0, 15, 8)
 241            | MOVED32 (GR[reg2], 15, 8, 7, 0));
 242
 243   GR[reg3] = value;
 244   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 245   if (value == 0) PSW |= PSW_Z;
 246   if (value & 0x80000000) PSW |= PSW_S;
 247   if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
 248
 249   TRACE_ALU_RESULT (GR[reg3]);
 250 }
 251
 252
 253
 254 // end-sanitize-v850e
 255 // start-sanitize-v850e
 256 // BSW
 257 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 258 *v850e
 259 // start-sanitize-v850eq
 260 *v850eq
 261 // end-sanitize-v850eq
 262 "bsw r<reg2>, r<reg3>"
 263 {
 264 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
 265   unsigned32 value;
 266   TRACE_ALU_INPUT1 (GR[reg2]);
 267
 268   value = GR[reg2];
 269   value >>= 24;
 270   value |= (GR[reg2] << 24);
 271   value |= ((GR[reg2] << 8) & 0x00ff0000);
 272   value |= ((GR[reg2] >> 8) & 0x0000ff00);
 273   GR[reg3] = value;
 274
 275   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 276
 277   if (value == 0) PSW |= PSW_Z;
 278   if (value & 0x80000000) PSW |= PSW_S;
 279   if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
 280
 281   TRACE_ALU_RESULT (GR[reg3]);
 282 }
 283
 284
 285
 286 // end-sanitize-v850e
 287 // start-sanitize-v850e
 288 // CALLT
 289 0000001000,iiiiii:II:::callt
 290 *v850e
 291 // start-sanitize-v850eq
 292 *v850eq
 293 // end-sanitize-v850eq
 294 "callt <imm6>"
 295 {
 296   unsigned32 adr;
 297   unsigned32 off;
 298   CTPC  = cia + 2;
 299   CTPSW = PSW;
 300   adr = (CTBP & ~1) + (imm6 << 1);
 301   off = load_mem (adr, 2) & ~1; /* Force alignment */
 302   nia = (CTBP & ~1) + off;
 303   TRACE_BRANCH3 (adr, CTBP, off);
 304 }
 305
 306
 307
 308 // end-sanitize-v850e
 309 // CLR1
 310 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
 311 "clr1 <bit3>, <disp16>[r<reg1>]"
 312 {
 313   COMPAT_2 (OP_87C0 ());
 314 }
 315
 316 // start-sanitize-v850e
 317 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 318 *v850e
 319 // start-sanitize-v850eq
 320 *v850eq
 321 // end-sanitize-v850eq
 322 "clr1 r<reg2>, [r<reg1>]"
 323 {
 324   COMPAT_2 (OP_E407E0 ());
 325 }
 326
 327
 328
 329 // end-sanitize-v850e
 330 // start-sanitize-v850e
 331 // CTRET
 332 0000011111100000 + 0000000101000100:X:::ctret
 333 *v850e
 334 // start-sanitize-v850eq
 335 *v850eq
 336 // end-sanitize-v850eq
 337 "ctret"
 338 {
 339   nia  = (CTPC & ~1);
 340   PSW = (CTPSW & (CPU)->psw_mask);
 341   TRACE_BRANCH1 (PSW);
 342 }
 343
 344
 345
 346 // end-sanitize-v850e
 347 // start-sanitize-v850e
 348 // CMOV
 349 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 350 *v850e
 351 // start-sanitize-v850eq
 352 *v850eq
 353 // end-sanitize-v850eq
 354 "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
 355 {
 356   COMPAT_2 (OP_32007E0 ());
 357 }
 358
 359 // end-sanitize-v850e
 360 // start-sanitize-v850e
 361 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 362 *v850e
 363 // start-sanitize-v850eq
 364 *v850eq
 365 // end-sanitize-v850eq
 366 "cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
 367 {
 368   COMPAT_2 (OP_30007E0 ());
 369 }
 370
 371
 372
 373 // end-sanitize-v850e
 374 // CMP
 375 rrrrr,001111,RRRRR:I:::cmp
 376 "cmp r<reg1>, r<reg2>"
 377 {
 378   COMPAT_1 (OP_1E0 ());
 379 }
 380
 381 rrrrr,010011,iiiii:II:::cmp
 382 "cmp <imm5>, r<reg2>"
 383 {
 384   COMPAT_1 (OP_260 ());
 385 }
 386
 387
 388
 389 // DI
 390 0000011111100000 + 0000000101100000:X:::di
 391 "di"
 392 {
 393   COMPAT_2 (OP_16007E0 ());
 394 }
 395
 396
 397
 398 // start-sanitize-v850e
 399 // DISPOSE
 400 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
 401 // "dispose <imm5>, <list12>"
 402 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
 403 *v850e
 404 // start-sanitize-v850eq
 405 *v850eq
 406 // end-sanitize-v850eq
 407 "dispose <imm5>, <list12>":RRRRR == 0
 408 "dispose <imm5>, <list12>, [reg1]"
 409 {
 410   int i;
 411   SAVE_2;
 412
 413   trace_input ("dispose", OP_PUSHPOP1, 0);
 414
 415   SP += (OP[3] & 0x3e) << 1;
 416
 417   /* Load the registers with lower number registers being retrieved
 418      from higher addresses.  */
 419   for (i = 12; i--;)
 420     if ((OP[3] & (1 << type1_regs[ i ])))
 421       {
 422         State.regs[ 20 + i ] = load_mem (SP, 4);
 423         SP += 4;
 424       }
 425
 426   if ((OP[3] & 0x1f0000) != 0)
 427     {
 428       nia = State.regs[ (OP[3] >> 16) & 0x1f];
 429     }
 430
 431   trace_output (OP_PUSHPOP1);
 432 }
 433
 434
 435
 436 // end-sanitize-v850e
 437 // start-sanitize-v850e
 438 // DIV
 439 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 440 *v850e
 441 "div r<reg1>, r<reg2>, r<reg3>"
 442 {
 443   COMPAT_2 (OP_2C007E0 ());
 444 }
 445
 446
 447
 448
 449 // end-sanitize-v850e
 450 // DIVH
 451 rrrrr!0,000010,RRRRR!0:I:::divh
 452 "divh r<reg1>, r<reg2>"
 453 {
 454   COMPAT_1 (OP_40 ());
 455 }
 456
 457 // start-sanitize-v850e
 458 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 459 *v850e
 460 "divh r<reg1>, r<reg2>, r<reg3>"
 461 {
 462   COMPAT_2 (OP_28007E0 ());
 463 }
 464
 465
 466
 467 // end-sanitize-v850e
 468 // start-sanitize-v850e
 469 // DIVHU
 470 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 471 *v850e
 472 "divhu r<reg1>, r<reg2>, r<reg3>"
 473 {
 474   COMPAT_2 (OP_28207E0 ());
 475 }
 476
 477
 478
 479 // end-sanitize-v850e
 480 // start-sanitize-v850e
 481 // DIVU
 482 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 483 *v850e
 484 "divu r<reg1>, r<reg2>, r<reg3>"
 485 {
 486   COMPAT_2 (OP_2C207E0 ());
 487 }
 488
 489
 490
 491 // end-sanitize-v850e
 492 // EI
 493 1000011111100000 + 0000000101100000:X:::ei
 494 "ei"
 495 {
 496   COMPAT_2 (OP_16087E0 ());
 497 }
 498
 499
 500
 501 // HALT
 502 0000011111100000 + 0000000100100000:X:::halt
 503 "halt"
 504 {
 505   COMPAT_2 (OP_12007E0 ());
 506 }
 507
 508
 509
 510 // start-sanitize-v850e
 511 // HSW
 512 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 513 *v850e
 514 // start-sanitize-v850eq
 515 *v850eq
 516 // end-sanitize-v850eq
 517 "hsw r<reg2>, r<reg3>"
 518 {
 519   unsigned32 value;
 520   TRACE_ALU_INPUT1 (GR[reg2]);
 521
 522   value = GR[reg2];
 523   value >>= 16;
 524   value |= (GR[reg2] << 16);
 525
 526   GR[reg3] = value;
 527
 528   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 529
 530   if (value == 0) PSW |= PSW_Z;
 531   if (value & 0x80000000) PSW |= PSW_S;
 532   if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
 533
 534   TRACE_ALU_RESULT (GR[reg3]);
 535 }
 536
 537
 538
 539 // end-sanitize-v850e
 540 // JARL
 541 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 542 "jarl <disp22>, r<reg2>"
 543 {
 544   COMPAT_2 (OP_780 ());
 545 }
 546
 547
 548
 549 // JMP
 550 00000000011,RRRRR:I:::jmp
 551 "jmp [r<reg1>]"
 552 {
 553   SAVE_1;
 554   trace_input ("jmp", OP_REG, 0);
 555   nia = State.regs[ reg1 ];
 556   trace_output (OP_REG);
 557 }
 558
 559
 560
 561 // JR
 562 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 563 "jr <disp22>"
 564 {
 565   COMPAT_2 (OP_780 ());
 566 }
 567
 568
 569
 570 // LD
 571 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 572 "ld.b <disp16>[r<reg1>, r<reg2>"
 573 {
 574   COMPAT_2 (OP_700 ());
 575 }
 576
 577 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 578 "ld.h <disp16>[r<reg1>], r<reg2>"
 579 {
 580   COMPAT_2 (OP_720 ());
 581 }
 582
 583 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 584 "ld.w <disp16>[r<reg1>], r<reg2>"
 585 {
 586   COMPAT_2 (OP_10720 ());
 587 }
 588
 589 // start-sanitize-v850e
 590 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 591 *v850e
 592 // start-sanitize-v850eq
 593 *v850eq
 594 // end-sanitize-v850eq
 595 "ld.bu <disp16>[r<reg1>], r<reg2>"
 596 {
 597   COMPAT_2 (OP_10780 ());
 598 }
 599
 600 // end-sanitize-v850e
 601 // start-sanitize-v850e
 602 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 603 *v850e
 604 // start-sanitize-v850eq
 605 *v850eq
 606 // end-sanitize-v850eq
 607 "ld.hu <disp16>[r<reg1>], r<reg2>"
 608 {
 609   COMPAT_2 (OP_107E0 ());
 610 }
 611
 612
 613 // end-sanitize-v850e
 614 // LDSR
 615 regID,111111,RRRRR + 0000000000100000:IX:::ldsr
 616 "ldsr r<reg1>, s<regID>"
 617 {
 618   TRACE_ALU_INPUT1 (GR[reg1]);
 619
 620   if (&PSW == &SR[regID])
 621     PSW = (GR[reg1] & (CPU)->psw_mask);
 622   else
 623     SR[regID] = GR[reg1];
 624
 625   TRACE_ALU_RESULT (SR[regID]);
 626 }
 627
 628
 629
 630 // MOV
 631 rrrrr!0,000000,RRRRR:I:::mov
 632 "mov r<reg1>, r<reg2>"
 633 {
 634   TRACE_ALU_INPUT0 ();
 635   GR[reg2] = GR[reg1];
 636   TRACE_ALU_RESULT (GR[reg2]);
 637 }
 638
 639
 640 rrrrr!0,010000,iiiii:II:::mov
 641 "mov <imm5>, r<reg2>"
 642 {
 643   COMPAT_1 (OP_200 ());
 644 }
 645
 646 // start-sanitize-v850e
 647 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
 648 *v850e
 649 // start-sanitize-v850eq
 650 *v850eq
 651 // end-sanitize-v850eq
 652 "mov <imm32>, r<reg1>"
 653 {
 654   SAVE_2;
 655   trace_input ("mov", OP_IMM_REG, 4);
 656   State.regs[ OP[0] ] = load_mem (PC + 2, 4);
 657   trace_output (OP_IMM_REG);
 658 }
 659
 660
 661
 662 // end-sanitize-v850e
 663 // MOVEA
 664 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
 665 "movea <simm16>, r<reg1>, r<reg2>"
 666 {
 667   TRACE_ALU_INPUT2 (GR[reg1], simm16);
 668   GR[reg2] = GR[reg1] + simm16;
 669   TRACE_ALU_RESULT (GR[reg2]);
 670 }
 671
 672
 673
 674 // MOVHI
 675 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
 676 "movhi <uimm16>, r<reg1>, r<reg2>"
 677 {
 678   COMPAT_2 (OP_640 ());
 679 }
 680
 681
 682
 683 // start-sanitize-v850e
 684 // MUL
 685 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 686 *v850e
 687 // start-sanitize-v850eq
 688 *v850eq
 689 // end-sanitize-v850eq
 690 "mul r<reg1>, r<reg2>, r<reg3>"
 691 {
 692   COMPAT_2 (OP_22007E0 ());
 693 }
 694
 695 // end-sanitize-v850e
 696 // start-sanitize-v850e
 697 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 698 *v850e
 699 // start-sanitize-v850eq
 700 *v850eq
 701 // end-sanitize-v850eq
 702 "mul <imm9>, r<reg2>, r<reg3>"
 703 {
 704   COMPAT_2 (OP_24007E0 ());
 705 }
 706
 707
 708
 709 // end-sanitize-v850e
 710 // MULH
 711 rrrrr!0,000111,RRRRR:I:::mulh
 712 "mulh r<reg1>, r<reg2>"
 713 {
 714   COMPAT_1 (OP_E0 ());
 715 }
 716
 717 rrrrr!0,010111,iiiii:II:::mulh
 718 "mulh <imm5>, r<reg2>"
 719 {
 720   COMPAT_1 (OP_2E0 ());
 721 }
 722
 723
 724
 725 // MULHI
 726 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
 727 "mulhi <uimm16>, r<reg1>, r<reg2>"
 728 {
 729   COMPAT_2 (OP_6E0 ());
 730 }
 731
 732
 733
 734 // start-sanitize-v850e
 735 // MULU
 736 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 737 *v850e
 738 // start-sanitize-v850eq
 739 *v850eq
 740 // end-sanitize-v850eq
 741 "mulu r<reg1>, r<reg2>, r<reg3>"
 742 {
 743   COMPAT_2 (OP_22207E0 ());
 744 }
 745
 746 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 747 *v850e
 748 // start-sanitize-v850eq
 749 *v850eq
 750 // end-sanitize-v850eq
 751 "mulu <imm9>, r<reg2>, r<reg3>"
 752 {
 753   COMPAT_2 (OP_24207E0 ());
 754 }
 755
 756
 757
 758 // end-sanitize-v850e
 759 // NOP
 760 0000000000000000:I:::nop
 761 "nop"
 762 {
 763   /* do nothing, trace nothing */
 764 }
 765
 766
 767
 768 // NOT
 769 rrrrr,000001,RRRRR:I:::not
 770 "not r<reg1>, r<reg2>"
 771 {
 772   COMPAT_1 (OP_20 ());
 773 }
 774
 775
 776
 777 // NOT1
 778 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
 779 "not1 <bit3>, <disp16>[r<reg1>]"
 780 {
 781   COMPAT_2 (OP_47C0 ());
 782 }
 783
 784 // start-sanitize-v850e
 785 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 786 *v850e
 787 // start-sanitize-v850eq
 788 *v850eq
 789 // end-sanitize-v850eq
 790 "not1 r<reg2>, r<reg1>"
 791 {
 792   COMPAT_2 (OP_E207E0 ());
 793 }
 794
 795
 796
 797 // end-sanitize-v850e
 798 // OR
 799 rrrrr,001000,RRRRR:I:::or
 800 "or r<reg1>, r<reg2>"
 801 {
 802   COMPAT_1 (OP_100 ());
 803 }
 804
 805
 806
 807 // ORI
 808 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 809 "ori <uimm16>, r<reg1>, r<reg2>"
 810 {
 811   COMPAT_2 (OP_680 ());
 812 }
 813
 814
 815
 816 // start-sanitize-v850e
 817 // PREPARE
 818 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
 819 *v850e
 820 // start-sanitize-v850eq
 821 *v850eq
 822 // end-sanitize-v850eq
 823 "prepare <list12>, <imm5>"
 824 {
 825   int  i;
 826   SAVE_2;
 827
 828   trace_input ("prepare", OP_PUSHPOP1, 0);
 829
 830   /* Store the registers with lower number registers being placed at
 831      higher addresses.  */
 832   for (i = 0; i < 12; i++)
 833     if ((OP[3] & (1 << type1_regs[ i ])))
 834       {
 835         SP -= 4;
 836         store_mem (SP, 4, State.regs[ 20 + i ]);
 837       }
 838
 839   SP -= (OP[3] & 0x3e) << 1;
 840
 841   trace_output (OP_PUSHPOP1);
 842 }
 843
 844
 845 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
 846 *v850e
 847 // start-sanitize-v850eq
 848 *v850eq
 849 // end-sanitize-v850eq
 850 "prepare <list12>, <imm5>, sp"
 851 {
 852   COMPAT_2 (OP_30780 ());
 853 }
 854
 855 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
 856 *v850e
 857 // start-sanitize-v850eq
 858 *v850eq
 859 // end-sanitize-v850eq
 860 "prepare <list12>, <imm5>, <uimm16>"
 861 {
 862   COMPAT_2 (OP_B0780 ());
 863 }
 864
 865 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
 866 *v850e
 867 // start-sanitize-v850eq
 868 *v850eq
 869 // end-sanitize-v850eq
 870 "prepare <list12>, <imm5>, <uimm16>"
 871 {
 872   COMPAT_2 (OP_130780 ());
 873 }
 874
 875 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
 876 *v850e
 877 // start-sanitize-v850eq
 878 *v850eq
 879 // end-sanitize-v850eq
 880 "prepare <list12>, <imm5>, <uimm32>"
 881 {
 882   COMPAT_2 (OP_1B0780 ());
 883 }
 884
 885
 886
 887 // end-sanitize-v850e
 888 // RETI
 889 0000011111100000 + 0000000101000000:X:::reti
 890 "reti"
 891 {
 892   if ((PSW & PSW_EP))
 893     {
 894       nia = (EIPC & ~1);
 895       PSW = EIPSW;
 896     }
 897   else if ((PSW & PSW_NP))
 898     {
 899       nia = (FEPC & ~1);
 900       PSW = FEPSW;
 901     }
 902   else
 903     {
 904       nia = (EIPC & ~1);
 905       PSW = EIPSW;
 906     }
 907   TRACE_BRANCH1 (PSW);
 908 }
 909
 910
 911
 912 // SAR
 913 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
 914 "sar r<reg1>, r<reg2>"
 915 {
 916   COMPAT_2 (OP_A007E0 ());
 917 }
 918
 919 rrrrr,010101,iiiii:II:::sar
 920 "sar <imm5>, r<reg2>"
 921 {
 922   COMPAT_1 (OP_2A0 ());
 923 }
 924
 925
 926
 927 // start-sanitize-v850e
 928 // SASF
 929 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
 930 *v850e
 931 // start-sanitize-v850eq
 932 *v850eq
 933 // end-sanitize-v850eq
 934 "sasf <cccc>, r<reg2>"
 935 {
 936   COMPAT_2 (OP_20007E0 ());
 937 }
 938
 939
 940
 941
 942 // end-sanitize-v850e
 943 // SATADD
 944 rrrrr!0,000110,RRRRR:I:::satadd
 945 "satadd r<reg1>, r<reg2>"
 946 {
 947   COMPAT_1 (OP_C0 ());
 948 }
 949
 950 rrrrr!0,010001,iiiii:II:::satadd
 951 "satadd <imm5>, r<reg2>"
 952 {
 953   COMPAT_1 (OP_220 ());
 954 }
 955
 956
 957
 958 // SATSUB
 959 rrrrr!0,000101,RRRRR:I:::satsub
 960 "satsub r<reg1>, r<reg2>"
 961 {
 962   COMPAT_1 (OP_A0 ());
 963 }
 964
 965
 966
 967 // SATSUBI
 968 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
 969 "satsubi <simm16>, r<reg1>, r<reg2>"
 970 {
 971   COMPAT_2 (OP_660 ());
 972 }
 973
 974
 975
 976 // SATSUBR
 977 rrrrr!0,000100,RRRRR:I:::satsubr
 978 "satsubr r<reg1>, r<reg2>"
 979 {
 980   COMPAT_1 (OP_80 ());
 981 }
 982
 983
 984
 985 // SETF
 986 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
 987 "setf <cccc>, r<reg2>"
 988 {
 989   COMPAT_2 (OP_7E0 ());
 990 }
 991
 992
 993
 994 // SET1
 995 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
 996 "set1 <bit3>, <disp16>[r<reg1>]"
 997 {
 998   COMPAT_2 (OP_7C0 ());
 999 }
1000
1001 // start-sanitize-v850e
1002 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
1003 *v850e
1004 // start-sanitize-v850eq
1005 *v850eq
1006 // end-sanitize-v850eq
1007 "set1 r<reg2>, [r<reg1>]"
1008 {
1009   COMPAT_2 (OP_E007E0 ());
1010 }
1011
1012
1013
1014 // end-sanitize-v850e
1015 // SHL
1016 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
1017 "shl r<reg1>, r<reg2>"
1018 {
1019   COMPAT_2 (OP_C007E0 ());
1020 }
1021
1022 rrrrr,010110,iiiii:II:::shl
1023 "shl <imm5>, r<reg2>"
1024 {
1025   COMPAT_1 (OP_2C0 ());
1026 }
1027
1028
1029
1030 // SHR
1031 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
1032 "shr r<reg1>, r<reg2>"
1033 {
1034   COMPAT_2 (OP_8007E0 ());
1035 }
1036
1037 rrrrr,010100,iiiii:II:::shr
1038 "shr <imm5>, r<reg2>"
1039 {
1040   COMPAT_1 (OP_280 ());
1041 }
1042
1043
1044
1045 // SLD
1046 rrrrr,0110,ddddddd:IV:::sld.b
1047 "sld.b <disp7>[ep], r<reg2>"
1048 {
1049   COMPAT_1 (OP_300 ());
1050 }
1051
1052 rrrrr,1000,ddddddd:IV:::sld.h
1053 "sld.h <disp8>[ep], r<reg2>"
1054 {
1055   COMPAT_1 (OP_400 ());
1056 }
1057
1058 rrrrr,1010,dddddd,0:IV:::sld.w
1059 "sld.w <disp8>[ep], r<reg2>"
1060 {
1061   COMPAT_1 (OP_500 ());
1062 }
1063
1064 // start-sanitize-v850e
1065 rrrrr!0,0000110,dddd:IV:::sld.bu
1066 "sld.bu <disp4>[ep], r<reg2>"
1067 {
1068   unsigned long result;
1069
1070   SAVE_1;
1071   result = load_mem (State.regs[30] + disp4, 1);
1072
1073   /* start-sanitize-v850eq */
1074   if (PSW & PSW_US) {
1075     trace_input ("sld.b", OP_LOAD16, 1);
1076
1077     State.regs[ reg2 ] = EXTEND8 (result);
1078   } else {
1079   /* end-sanitize-v850eq */
1080   trace_input ("sld.bu", OP_LOAD16, 1);
1081   State.regs[ reg2 ] = result;
1082   /* start-sanitize-v850eq */
1083   }
1084   /* end-sanitize-v850eq */
1085   trace_output (OP_LOAD16);
1086 }
1087
1088 // end-sanitize-v850e
1089 // start-sanitize-v850e
1090 rrrrr!0,0000111,dddd:IV:::sld.hu
1091 "sld.hu <disp5>[ep], r<reg2>"
1092 {
1093   COMPAT_1 (OP_70 ());
1094 }
1095
1096 // end-sanitize-v850e
1097
1098
1099 // SST
1100 rrrrr,0111,ddddddd:IV:::sst.b
1101 "sst.b r<reg2>, <disp7>[ep]"
1102 {
1103   COMPAT_1 (OP_380 ());
1104 }
1105
1106 rrrrr,1001,ddddddd:IV:::sst.h
1107 "sst.h r<reg2>, <disp8>[ep]"
1108 {
1109   COMPAT_1 (OP_480 ());
1110 }
1111
1112 rrrrr,1010,dddddd,1:IV:::sst.w
1113 "sst.w r<reg2>, <disp8>[ep]"
1114 {
1115   COMPAT_1 (OP_501 ());
1116 }
1117
1118
1119
1120 // ST
1121 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
1122 "st.b r<reg2>, <disp16>[r<reg1>]"
1123 {
1124   COMPAT_2 (OP_740 ());
1125 }
1126
1127 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
1128 "st.h r<reg2>, <disp16>[r<reg1>]"
1129 {
1130   COMPAT_2 (OP_760 ());
1131 }
1132
1133 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1134 "st.w r<reg2>, <disp16>[r<reg1>]"
1135 {
1136   COMPAT_2 (OP_10760 ());
1137 }
1138
1139
1140
1141 // STSR
1142 rrrrr,111111,regID + 0000000001000000:IX:::stsr
1143 "stsr s<regID>, r<reg2>"
1144 {
1145   TRACE_ALU_INPUT1 (SR[regID]);
1146   GR[reg2] = SR[regID];
1147   TRACE_ALU_RESULT (GR[reg2]);
1148 }
1149
1150
1151
1152 // SUB
1153 rrrrr,001101,RRRRR:I:::sub
1154 "sub r<reg1>, r<reg2>"
1155 {
1156   COMPAT_1 (OP_1A0 ());
1157 }
1158
1159
1160
1161 // SUBR
1162 rrrrr,001100,RRRRR:I:::subr
1163 "subr r<reg1>, r<reg2>"
1164 {
1165   COMPAT_1 (OP_180 ());
1166 }
1167
1168
1169
1170 // start-sanitize-v850e
1171 // SWITCH
1172 00000000010,RRRRR:I:::switch
1173 *v850e
1174 // start-sanitize-v850eq
1175 *v850eq
1176 // end-sanitize-v850eq
1177 "switch r<reg1>"
1178 {
1179   unsigned long adr;
1180   SAVE_1;
1181   trace_input ("switch", OP_REG, 0);
1182   adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1183   nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1184   trace_output (OP_REG);
1185 }
1186
1187
1188
1189 // end-sanitize-v850e
1190 // start-sanitize-v850e
1191 // SXB
1192 00000000101,RRRRR:I:::sxb
1193 *v850e
1194 // start-sanitize-v850eq
1195 *v850eq
1196 // end-sanitize-v850eq
1197 "sxb r<reg1>"
1198 {
1199   TRACE_ALU_INPUT1 (GR[reg1]);
1200   GR[reg1] = EXTEND8 (GR[reg1]);
1201   TRACE_ALU_RESULT (GR[reg1]);
1202 }
1203
1204
1205
1206 // end-sanitize-v850e
1207 // start-sanitize-v850e
1208 // SXH
1209 00000000111,RRRRR:I:::sxh
1210 *v850e
1211 // start-sanitize-v850eq
1212 *v850eq
1213 // end-sanitize-v850eq
1214 "sxh r<reg1>"
1215 {
1216   TRACE_ALU_INPUT1 (GR[reg1]);
1217   GR[reg1] = EXTEND16 (GR[reg1]);
1218   TRACE_ALU_RESULT (GR[reg1]);
1219 }
1220
1221
1222
1223 // end-sanitize-v850e
1224 // TRAP
1225 00000111111,iiiii + 0000000100000000:X:::trap
1226 "trap <vector>"
1227 {
1228   COMPAT_2 (OP_10007E0 ());
1229 }
1230
1231
1232
1233 // TST
1234 rrrrr,001011,RRRRR:I:::tst
1235 "tst r<reg1>, r<reg2>"
1236 {
1237   COMPAT_1 (OP_160 ());
1238 }
1239
1240
1241
1242 // TST1
1243 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1244 "tst1 <bit3>, <disp16>[r<reg1>]"
1245 {
1246   COMPAT_2 (OP_C7C0 ());
1247 }
1248
1249 // start-sanitize-v850e
1250 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1251 *v850e
1252 // start-sanitize-v850eq
1253 *v850eq
1254 // end-sanitize-v850eq
1255 "tst1 r<reg2>, [r<reg1>]"
1256 {
1257   COMPAT_2 (OP_E607E0 ());
1258 }
1259
1260
1261
1262 // end-sanitize-v850e
1263 // XOR
1264 rrrrr,001001,RRRRR:I:::xor
1265 "xor r<reg1>, r<reg2>"
1266 {
1267   COMPAT_1 (OP_120 ());
1268 }
1269
1270
1271
1272 // XORI
1273 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1274 "xori <uimm16>, r<reg1>, r<reg2>"
1275 {
1276   COMPAT_2 (OP_6A0 ());
1277 }
1278
1279
1280
1281 // start-sanitize-v850e
1282 // ZXB
1283 00000000100,RRRRR:I:::zxb
1284 *v850e
1285 // start-sanitize-v850eq
1286 *v850eq
1287 // end-sanitize-v850eq
1288 "zxb r<reg1>"
1289 {
1290   TRACE_ALU_INPUT1 (GR[reg1]);
1291   GR[reg1] = GR[reg1] & 0xff;
1292   TRACE_ALU_RESULT (GR[reg1]);
1293 }
1294
1295
1296
1297 // end-sanitize-v850e
1298 // start-sanitize-v850e
1299 // ZXH
1300 00000000110,RRRRR:I:::zxh
1301 *v850e
1302 // start-sanitize-v850eq
1303 *v850eq
1304 // end-sanitize-v850eq
1305 "zxh r<reg1>"
1306 {
1307   TRACE_ALU_INPUT1 (GR[reg1]);
1308   GR[reg1] = GR[reg1] & 0xffff;
1309   TRACE_ALU_RESULT (GR[reg1]);
1310 }
1311
1312
1313
1314 // end-sanitize-v850e
1315 // Special - breakpoint - illegal
1316 // Hopefully, in the future, this instruction will go away
1317 1111111111111111 + 1111111111111111:Z:::breakpoint
1318 *v850
1319 {
1320   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1321 }
1322
1323 // start-sanitize-v850e
1324 // First field could be any nonzero value.
1325 11111,000010,00000:I:::break
1326 {
1327   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1328 }
1329
1330 // end-sanitize-v850e
1331
1332
1333 // start-sanitize-v850eq
1334 // DIVHN
1335 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1336 *v850eq
1337 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1338 {
1339   signed32 quotient;
1340   signed32 remainder;
1341   signed32 divide_by;
1342   signed32 divide_this;
1343   boolean overflow = false;
1344   SAVE_2;
1345
1346   trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1347
1348   divide_by   = EXTEND16 (State.regs[ reg1 ]);
1349   divide_this = State.regs[ reg2 ];
1350
1351   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1352
1353   State.regs[ reg2 ] = quotient;
1354   State.regs[ reg3 ] = remainder;
1355
1356   /* Set condition codes.  */
1357   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1358
1359   if (overflow)      PSW |= PSW_OV;
1360   if (quotient == 0) PSW |= PSW_Z;
1361   if (quotient <  0) PSW |= PSW_S;
1362
1363   trace_output (OP_IMM_REG_REG_REG);
1364 }
1365
1366
1367
1368 // DIVHUN
1369 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1370 *v850eq
1371 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1372 {
1373   signed32 quotient;
1374   signed32 remainder;
1375   signed32 divide_by;
1376   signed32 divide_this;
1377   boolean overflow = false;
1378   SAVE_2;
1379
1380   trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1381
1382   divide_by   = State.regs[ reg1 ] & 0xffff;
1383   divide_this = State.regs[ reg2 ];
1384
1385   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1386
1387   State.regs[ reg2 ] = quotient;
1388   State.regs[ reg3 ] = remainder;
1389
1390   /* Set condition codes.  */
1391   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1392
1393   if (overflow)      PSW |= PSW_OV;
1394   if (quotient == 0) PSW |= PSW_Z;
1395   if (quotient & 0x80000000) PSW |= PSW_S;
1396
1397   trace_output (OP_IMM_REG_REG_REG);
1398 }
1399
1400
1401
1402 // DIVN
1403 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1404 *v850eq
1405 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1406 {
1407   signed32 quotient;
1408   signed32 remainder;
1409   signed32 divide_by;
1410   signed32 divide_this;
1411   boolean overflow = false;
1412   SAVE_2;
1413
1414   trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1415
1416   divide_by   = State.regs[ reg1 ];
1417   divide_this = State.regs[ reg2 ];
1418
1419   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1420
1421   State.regs[ reg2 ] = quotient;
1422   State.regs[ reg3 ] = remainder;
1423
1424   /* Set condition codes.  */
1425   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1426
1427   if (overflow)      PSW |= PSW_OV;
1428   if (quotient == 0) PSW |= PSW_Z;
1429   if (quotient <  0) PSW |= PSW_S;
1430
1431   trace_output (OP_IMM_REG_REG_REG);
1432 }
1433
1434
1435
1436 // DIVUN
1437 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1438 *v850eq
1439 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1440 {
1441   signed32 quotient;
1442   signed32 remainder;
1443   signed32 divide_by;
1444   signed32 divide_this;
1445   boolean overflow = false;
1446   SAVE_2;
1447
1448   trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1449
1450   divide_by   = State.regs[ reg1 ];
1451   divide_this = State.regs[ reg2 ];
1452
1453   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1454
1455   State.regs[ reg2 ] = quotient;
1456   State.regs[ reg3 ] = remainder;
1457
1458   /* Set condition codes.  */
1459   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1460
1461   if (overflow)      PSW |= PSW_OV;
1462   if (quotient == 0) PSW |= PSW_Z;
1463   if (quotient & 0x80000000) PSW |= PSW_S;
1464
1465   trace_output (OP_IMM_REG_REG_REG);
1466 }
1467
1468
1469
1470 // SDIVHN
1471 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1472 *v850eq
1473 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1474 {
1475   COMPAT_2 (OP_18007E0 ());
1476 }
1477
1478
1479
1480 // SDIVHUN
1481 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1482 *v850eq
1483 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1484 {
1485   COMPAT_2 (OP_18207E0 ());
1486 }
1487
1488
1489
1490 // SDIVN
1491 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1492 *v850eq
1493 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1494 {
1495   COMPAT_2 (OP_1C007E0 ());
1496 }
1497
1498
1499
1500 // SDIVUN
1501 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1502 *v850eq
1503 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1504 {
1505   COMPAT_2 (OP_1C207E0 ());
1506 }
1507
1508
1509
1510 // PUSHML
1511 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1512 *v850eq
1513 "pushml <list18>"
1514 {
1515   int i;
1516   SAVE_2;
1517
1518   trace_input ("pushml", OP_PUSHPOP3, 0);
1519
1520   /* Store the registers with lower number registers being placed at
1521      higher addresses.  */
1522
1523   for (i = 0; i < 15; i++)
1524     if ((OP[3] & (1 << type3_regs[ i ])))
1525       {
1526         SP -= 4;
1527         store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1528       }
1529
1530   if (OP[3] & (1 << 3))
1531     {
1532       SP -= 4;
1533
1534       store_mem (SP & ~ 3, 4, PSW);
1535     }
1536
1537   if (OP[3] & (1 << 19))
1538     {
1539       SP -= 8;
1540
1541       if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1542         {
1543           store_mem ((SP + 4) & ~ 3, 4, FEPC);
1544           store_mem ( SP      & ~ 3, 4, FEPSW);
1545         }
1546       else
1547         {
1548           store_mem ((SP + 4) & ~ 3, 4, EIPC);
1549           store_mem ( SP      & ~ 3, 4, EIPSW);
1550         }
1551     }
1552
1553   trace_output (OP_PUSHPOP2);
1554 }
1555
1556
1557
1558 // PUSHHML
1559 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1560 *v850eq
1561 "pushhml <list18>"
1562 {
1563   COMPAT_2 (OP_307E0 ());
1564 }
1565
1566
1567
1568 // POPML
1569 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1570 *v850eq
1571 "popml <list18>"
1572 {
1573   COMPAT_2 (OP_107F0 ());
1574 }
1575
1576
1577
1578 // POPMH
1579 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1580 *v850eq
1581 "popmh <list18>"
1582 {
1583   COMPAT_2 (OP_307F0 ());
1584 }
1585
1586
1587 // end-sanitize-v850eq