sim/v850/v850.igen

   1 :option:::insn-bit-size:16
   2 :option:::hi-bit-nr:15
   3
   4
   5 :option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
   6 :option:::format-names:XI,XII,XIII
   7 :option:::format-names:XIV,XV
   8 :option:::format-names:Z
   9
  10
  11 :model:::v850:v850:
  12
  13 :option:::multi-sim:true
  14 :model:::v850e:v850e:
  15
  16 // Cache macros
  17
  18 :cache:::unsigned:reg1:RRRRR:(RRRRR)
  19 :cache:::unsigned:reg2:rrrrr:(rrrrr)
  20 :cache:::unsigned:reg3:wwwww:(wwwww)
  21
  22 :cache:::unsigned:disp4:dddd:(dddd)
  23 :cache:::unsigned:disp5:dddd:(dddd << 1)
  24 :cache:::unsigned:disp7:ddddddd:ddddddd
  25 :cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
  26 :cache:::unsigned:disp8:dddddd:(dddddd << 2)
  27 :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
  28 :cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
  29 :cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
  30 :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
  31
  32 :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
  33 :cache:::unsigned:imm6:iiiiii:iiiiii
  34 :cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
  35 :cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
  36 :cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
  37 :cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  38 :cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
  39 :cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
  40
  41 :cache:::unsigned:vector:iiiii:iiiii
  42
  43 :cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
  44 :cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
  45
  46 :cache:::unsigned:bit3:bbb:bbb
  47
  48
  49 // What do we do with an illegal instruction?
  50 :internal::::illegal:
  51 {
  52   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  53                   (unsigned long) cia);
  54   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
  55 }
  56
  57
  58
  59 // Add
  60
  61 rrrrr,001110,RRRRR:I:::add
  62 "add r<reg1>, r<reg2>"
  63 {
  64   COMPAT_1 (OP_1C0 ());
  65 }
  66
  67 rrrrr,010010,iiiii:II:::add
  68 "add <imm5>,r<reg2>"
  69 {
  70   COMPAT_1 (OP_240 ());
  71 }
  72
  73
  74
  75 // ADDI
  76 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
  77 "addi <simm16>, r<reg1>, r<reg2>"
  78 {
  79   COMPAT_2 (OP_600 ());
  80 }
  81
  82
  83
  84 // AND
  85 rrrrr,001010,RRRRR:I:::and
  86 "and r<reg1>, r<reg2>"
  87 {
  88   COMPAT_1 (OP_140 ());
  89 }
  90
  91
  92
  93 // ANDI
  94 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
  95 "andi <uimm16>, r<reg1>, r<reg2>"
  96 {
  97   COMPAT_2 (OP_6C0 ());
  98 }
  99
 100
 101
 102 // Map condition code to a string
 103 :%s::::cccc:int cccc
 104 {
 105   switch (cccc)
 106     {
 107     case 0xf: return "gt";
 108     case 0xe: return "ge";
 109     case 0x6: return "lt";
 110
 111     case 0x7: return "le";
 112
 113     case 0xb: return "h";
 114     case 0x9: return "nl";
 115     case 0x1: return "l";
 116
 117     case 0x3: return "nh";
 118
 119     case 0x2: return "e";
 120
 121     case 0xa: return "ne";
 122
 123     case 0x0: return "v";
 124     case 0x8: return "nv";
 125     case 0x4: return "n";
 126     case 0xc: return "p";
 127       /* case 0x1: return "c"; */
 128       /* case 0x9: return "nc"; */
 129       /* case 0x2: return "z"; */
 130       /* case 0xa: return "nz"; */
 131     case 0x5: return "r"; /* always */
 132     case 0xd: return "sa";
 133     }
 134   return "(null)";
 135 }
 136
 137
 138 // Bcond
 139 ddddd,1011,ddd,cccc:III:::Bcond
 140 "b%s<cccc> <disp9>"
 141 {
 142   int cond;
 143   if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
 144     // Special case - treat "br *" like illegal instruction
 145     sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
 146   } else {
 147     cond = condition_met (cccc);
 148     if (cond)
 149       nia = cia + disp9;
 150     TRACE_BRANCH1 (cond);
 151   }
 152 }
 153
 154
 155
 156 // BSH
 157 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 158 *v850e
 159 "bsh r<reg2>, r<reg3>"
 160 {
 161   unsigned32 value;
 162   TRACE_ALU_INPUT1 (GR[reg2]);
 163
 164   value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
 165            | MOVED32 (GR[reg2], 31, 24, 23, 16)
 166            | MOVED32 (GR[reg2], 7, 0, 15, 8)
 167            | MOVED32 (GR[reg2], 15, 8, 7, 0));
 168
 169   GR[reg3] = value;
 170   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 171   if (value == 0) PSW |= PSW_Z;
 172   if (value & 0x80000000) PSW |= PSW_S;
 173   if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
 174
 175   TRACE_ALU_RESULT (GR[reg3]);
 176 }
 177
 178 // BSW
 179 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 180 *v850e
 181 "bsw r<reg2>, r<reg3>"
 182 {
 183 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
 184   unsigned32 value;
 185   TRACE_ALU_INPUT1 (GR[reg2]);
 186
 187   value = GR[reg2];
 188   value >>= 24;
 189   value |= (GR[reg2] << 24);
 190   value |= ((GR[reg2] << 8) & 0x00ff0000);
 191   value |= ((GR[reg2] >> 8) & 0x0000ff00);
 192   GR[reg3] = value;
 193
 194   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 195
 196   if (value == 0) PSW |= PSW_Z;
 197   if (value & 0x80000000) PSW |= PSW_S;
 198   if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
 199
 200   TRACE_ALU_RESULT (GR[reg3]);
 201 }
 202
 203 // CALLT
 204 0000001000,iiiiii:II:::callt
 205 *v850e
 206 "callt <imm6>"
 207 {
 208   unsigned32 adr;
 209   unsigned32 off;
 210   CTPC  = cia + 2;
 211   CTPSW = PSW;
 212   adr = (CTBP & ~1) + (imm6 << 1);
 213   off = load_mem (adr, 2) & ~1; /* Force alignment */
 214   nia = (CTBP & ~1) + off;
 215   TRACE_BRANCH3 (adr, CTBP, off);
 216 }
 217
 218
 219 // CLR1
 220 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
 221 "clr1 <bit3>, <disp16>[r<reg1>]"
 222 {
 223   COMPAT_2 (OP_87C0 ());
 224 }
 225
 226 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 227 *v850e
 228 "clr1 r<reg2>, [r<reg1>]"
 229 {
 230   COMPAT_2 (OP_E407E0 ());
 231 }
 232
 233
 234 // CTRET
 235 0000011111100000 + 0000000101000100:X:::ctret
 236 *v850e
 237 "ctret"
 238 {
 239   nia  = (CTPC & ~1);
 240   PSW = (CTPSW & (CPU)->psw_mask);
 241   TRACE_BRANCH1 (PSW);
 242 }
 243
 244 // CMOV
 245 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 246 *v850e
 247 "cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
 248 {
 249   int cond = condition_met (cccc);
 250   TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
 251   GR[reg3] = cond ? GR[reg1] : GR[reg2];
 252   TRACE_ALU_RESULT (GR[reg3]);
 253 }
 254
 255 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 256 *v850e
 257 "cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
 258 {
 259   int cond = condition_met (cccc);
 260   TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
 261   GR[reg3] = cond ? imm5 : GR[reg2];
 262   TRACE_ALU_RESULT (GR[reg3]);
 263 }
 264
 265 // CMP
 266 rrrrr,001111,RRRRR:I:::cmp
 267 "cmp r<reg1>, r<reg2>"
 268 {
 269   COMPAT_1 (OP_1E0 ());
 270 }
 271
 272 rrrrr,010011,iiiii:II:::cmp
 273 "cmp <imm5>, r<reg2>"
 274 {
 275   COMPAT_1 (OP_260 ());
 276 }
 277
 278
 279
 280 // DI
 281 0000011111100000 + 0000000101100000:X:::di
 282 "di"
 283 {
 284   COMPAT_2 (OP_16007E0 ());
 285 }
 286
 287
 288
 289 // DISPOSE
 290 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
 291 // "dispose <imm5>, <list12>"
 292 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
 293 *v850e
 294 "dispose <imm5>, <list12>":RRRRR == 0
 295 "dispose <imm5>, <list12>, [reg1]"
 296 {
 297   int i;
 298   SAVE_2;
 299
 300   trace_input ("dispose", OP_PUSHPOP1, 0);
 301
 302   SP += (OP[3] & 0x3e) << 1;
 303
 304   /* Load the registers with lower number registers being retrieved
 305      from higher addresses.  */
 306   for (i = 12; i--;)
 307     if ((OP[3] & (1 << type1_regs[ i ])))
 308       {
 309         State.regs[ 20 + i ] = load_mem (SP, 4);
 310         SP += 4;
 311       }
 312
 313   if ((OP[3] & 0x1f0000) != 0)
 314     {
 315       nia = State.regs[ (OP[3] >> 16) & 0x1f];
 316     }
 317
 318   trace_output (OP_PUSHPOP1);
 319 }
 320
 321
 322 // DIV
 323 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 324 *v850e
 325 "div r<reg1>, r<reg2>, r<reg3>"
 326 {
 327   COMPAT_2 (OP_2C007E0 ());
 328 }
 329
 330
 331 // DIVH
 332 rrrrr!0,000010,RRRRR!0:I:::divh
 333 "divh r<reg1>, r<reg2>"
 334 {
 335   unsigned32 ov, s, z;
 336   signed long int op0, op1, result;
 337
 338   trace_input ("divh", OP_REG_REG, 0);
 339
 340   PC = cia;
 341   OP[0] = instruction_0 & 0x1f;
 342   OP[1] = (instruction_0 >> 11) & 0x1f;
 343
 344   /* Compute the result.  */
 345   op0 = EXTEND16 (State.regs[OP[0]]);
 346   op1 = State.regs[OP[1]];
 347
 348   if (op0 == 0xffffffff && op1 == 0x80000000)
 349     {
 350       result = 0x80000000;
 351       ov = 1;
 352     }
 353   else if (op0 != 0)
 354     {
 355       result = op1 / op0;
 356       ov = 0;
 357     }
 358   else
 359     {
 360       result = 0x0;
 361       ov = 1;
 362     }
 363
 364   /* Compute the condition codes.  */
 365   z = (result == 0);
 366   s = (result & 0x80000000);
 367
 368   /* Store the result and condition codes.  */
 369   State.regs[OP[1]] = result;
 370   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
 371   PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));
 372
 373   trace_output (OP_REG_REG);
 374
 375   PC += 2;
 376   nia = PC;
 377 }
 378
 379 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 380 *v850e
 381 "divh r<reg1>, r<reg2>, r<reg3>"
 382 {
 383   COMPAT_2 (OP_28007E0 ());
 384 }
 385
 386
 387 // DIVHU
 388 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 389 *v850e
 390 "divhu r<reg1>, r<reg2>, r<reg3>"
 391 {
 392   COMPAT_2 (OP_28207E0 ());
 393 }
 394
 395
 396 // DIVU
 397 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 398 *v850e
 399 "divu r<reg1>, r<reg2>, r<reg3>"
 400 {
 401   COMPAT_2 (OP_2C207E0 ());
 402 }
 403
 404
 405 // EI
 406 1000011111100000 + 0000000101100000:X:::ei
 407 "ei"
 408 {
 409   COMPAT_2 (OP_16087E0 ());
 410 }
 411
 412
 413
 414 // HALT
 415 0000011111100000 + 0000000100100000:X:::halt
 416 "halt"
 417 {
 418   COMPAT_2 (OP_12007E0 ());
 419 }
 420
 421
 422
 423 // HSW
 424 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 425 *v850e
 426 "hsw r<reg2>, r<reg3>"
 427 {
 428   unsigned32 value;
 429   TRACE_ALU_INPUT1 (GR[reg2]);
 430
 431   value = GR[reg2];
 432   value >>= 16;
 433   value |= (GR[reg2] << 16);
 434
 435   GR[reg3] = value;
 436
 437   PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 438
 439   if (value == 0) PSW |= PSW_Z;
 440   if (value & 0x80000000) PSW |= PSW_S;
 441   if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
 442
 443   TRACE_ALU_RESULT (GR[reg3]);
 444 }
 445
 446
 447
 448 // JARL
 449 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 450 "jarl <disp22>, r<reg2>"
 451 {
 452   GR[reg2] = nia;
 453   nia = cia + disp22;
 454   TRACE_BRANCH1 (GR[reg2]);
 455 }
 456
 457
 458
 459 // JMP
 460 00000000011,RRRRR:I:::jmp
 461 "jmp [r<reg1>]"
 462 {
 463   nia = GR[reg1] & ~1;
 464   TRACE_BRANCH0 ();
 465 }
 466
 467
 468
 469 // JR
 470 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 471 "jr <disp22>"
 472 {
 473   nia = cia + disp22;
 474   TRACE_BRANCH0 ();
 475 }
 476
 477
 478
 479 // LD
 480 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 481 "ld.b <disp16>[r<reg1>], r<reg2>"
 482 {
 483   COMPAT_2 (OP_700 ());
 484 }
 485
 486 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 487 "ld.h <disp16>[r<reg1>], r<reg2>"
 488 {
 489   COMPAT_2 (OP_720 ());
 490 }
 491
 492 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 493 "ld.w <disp16>[r<reg1>], r<reg2>"
 494 {
 495   COMPAT_2 (OP_10720 ());
 496 }
 497
 498 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 499 *v850e
 500 "ld.bu <disp16>[r<reg1>], r<reg2>"
 501 {
 502   COMPAT_2 (OP_10780 ());
 503 }
 504
 505 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 506 *v850e
 507 "ld.hu <disp16>[r<reg1>], r<reg2>"
 508 {
 509   COMPAT_2 (OP_107E0 ());
 510 }
 511
 512
 513 // LDSR
 514 regID,111111,RRRRR + 0000000000100000:IX:::ldsr
 515 "ldsr r<reg1>, s<regID>"
 516 {
 517   TRACE_ALU_INPUT1 (GR[reg1]);
 518
 519   if (&PSW == &SR[regID])
 520     PSW = (GR[reg1] & (CPU)->psw_mask);
 521   else
 522     SR[regID] = GR[reg1];
 523
 524   TRACE_ALU_RESULT (SR[regID]);
 525 }
 526
 527
 528
 529 // MOV
 530 rrrrr!0,000000,RRRRR:I:::mov
 531 "mov r<reg1>, r<reg2>"
 532 {
 533   TRACE_ALU_INPUT0 ();
 534   GR[reg2] = GR[reg1];
 535   TRACE_ALU_RESULT (GR[reg2]);
 536 }
 537
 538
 539 rrrrr!0,010000,iiiii:II:::mov
 540 "mov <imm5>, r<reg2>"
 541 {
 542   COMPAT_1 (OP_200 ());
 543 }
 544
 545 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
 546 *v850e
 547 "mov <imm32>, r<reg1>"
 548 {
 549   SAVE_2;
 550   trace_input ("mov", OP_IMM_REG, 4);
 551   State.regs[ OP[0] ] = load_mem (PC + 2, 4);
 552   trace_output (OP_IMM_REG);
 553 }
 554
 555
 556
 557 // MOVEA
 558 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
 559 "movea <simm16>, r<reg1>, r<reg2>"
 560 {
 561   TRACE_ALU_INPUT2 (GR[reg1], simm16);
 562   GR[reg2] = GR[reg1] + simm16;
 563   TRACE_ALU_RESULT (GR[reg2]);
 564 }
 565
 566
 567
 568 // MOVHI
 569 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
 570 "movhi <uimm16>, r<reg1>, r<reg2>"
 571 {
 572   COMPAT_2 (OP_640 ());
 573 }
 574
 575
 576
 577 // MUL
 578 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 579 *v850e
 580 "mul r<reg1>, r<reg2>, r<reg3>"
 581 {
 582   COMPAT_2 (OP_22007E0 ());
 583 }
 584
 585 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 586 *v850e
 587 "mul <imm9>, r<reg2>, r<reg3>"
 588 {
 589   COMPAT_2 (OP_24007E0 ());
 590 }
 591
 592
 593 // MULH
 594 rrrrr!0,000111,RRRRR:I:::mulh
 595 "mulh r<reg1>, r<reg2>"
 596 {
 597   COMPAT_1 (OP_E0 ());
 598 }
 599
 600 rrrrr!0,010111,iiiii:II:::mulh
 601 "mulh <imm5>, r<reg2>"
 602 {
 603   COMPAT_1 (OP_2E0 ());
 604 }
 605
 606
 607
 608 // MULHI
 609 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
 610 "mulhi <uimm16>, r<reg1>, r<reg2>"
 611 {
 612   COMPAT_2 (OP_6E0 ());
 613 }
 614
 615
 616
 617 // MULU
 618 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 619 *v850e
 620 "mulu r<reg1>, r<reg2>, r<reg3>"
 621 {
 622   COMPAT_2 (OP_22207E0 ());
 623 }
 624
 625 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 626 *v850e
 627 "mulu <imm9>, r<reg2>, r<reg3>"
 628 {
 629   COMPAT_2 (OP_24207E0 ());
 630 }
 631
 632
 633
 634 // NOP
 635 0000000000000000:I:::nop
 636 "nop"
 637 {
 638   /* do nothing, trace nothing */
 639 }
 640
 641
 642
 643 // NOT
 644 rrrrr,000001,RRRRR:I:::not
 645 "not r<reg1>, r<reg2>"
 646 {
 647   COMPAT_1 (OP_20 ());
 648 }
 649
 650
 651
 652 // NOT1
 653 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
 654 "not1 <bit3>, <disp16>[r<reg1>]"
 655 {
 656   COMPAT_2 (OP_47C0 ());
 657 }
 658
 659 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 660 *v850e
 661 "not1 r<reg2>, r<reg1>"
 662 {
 663   COMPAT_2 (OP_E207E0 ());
 664 }
 665
 666
 667
 668 // OR
 669 rrrrr,001000,RRRRR:I:::or
 670 "or r<reg1>, r<reg2>"
 671 {
 672   COMPAT_1 (OP_100 ());
 673 }
 674
 675
 676
 677 // ORI
 678 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 679 "ori <uimm16>, r<reg1>, r<reg2>"
 680 {
 681   COMPAT_2 (OP_680 ());
 682 }
 683
 684
 685
 686 // PREPARE
 687 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
 688 *v850e
 689 "prepare <list12>, <imm5>"
 690 {
 691   int  i;
 692   SAVE_2;
 693
 694   trace_input ("prepare", OP_PUSHPOP1, 0);
 695
 696   /* Store the registers with lower number registers being placed at
 697      higher addresses.  */
 698   for (i = 0; i < 12; i++)
 699     if ((OP[3] & (1 << type1_regs[ i ])))
 700       {
 701         SP -= 4;
 702         store_mem (SP, 4, State.regs[ 20 + i ]);
 703       }
 704
 705   SP -= (OP[3] & 0x3e) << 1;
 706
 707   trace_output (OP_PUSHPOP1);
 708 }
 709
 710
 711 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
 712 *v850e
 713 "prepare <list12>, <imm5>, sp"
 714 {
 715   COMPAT_2 (OP_30780 ());
 716 }
 717
 718 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
 719 *v850e
 720 "prepare <list12>, <imm5>, <uimm16>"
 721 {
 722   COMPAT_2 (OP_B0780 ());
 723 }
 724
 725 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
 726 *v850e
 727 "prepare <list12>, <imm5>, <uimm16>"
 728 {
 729   COMPAT_2 (OP_130780 ());
 730 }
 731
 732 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
 733 *v850e
 734 "prepare <list12>, <imm5>, <uimm32>"
 735 {
 736   COMPAT_2 (OP_1B0780 ());
 737 }
 738
 739
 740
 741 // RETI
 742 0000011111100000 + 0000000101000000:X:::reti
 743 "reti"
 744 {
 745   if ((PSW & PSW_EP))
 746     {
 747       nia = (EIPC & ~1);
 748       PSW = EIPSW;
 749     }
 750   else if ((PSW & PSW_NP))
 751     {
 752       nia = (FEPC & ~1);
 753       PSW = FEPSW;
 754     }
 755   else
 756     {
 757       nia = (EIPC & ~1);
 758       PSW = EIPSW;
 759     }
 760   TRACE_BRANCH1 (PSW);
 761 }
 762
 763
 764
 765 // SAR
 766 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
 767 "sar r<reg1>, r<reg2>"
 768 {
 769   COMPAT_2 (OP_A007E0 ());
 770 }
 771
 772 rrrrr,010101,iiiii:II:::sar
 773 "sar <imm5>, r<reg2>"
 774 {
 775   COMPAT_1 (OP_2A0 ());
 776 }
 777
 778
 779
 780 // SASF
 781 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
 782 *v850e
 783 "sasf %s<cccc>, r<reg2>"
 784 {
 785   COMPAT_2 (OP_20007E0 ());
 786 }
 787
 788
 789
 790
 791 // SATADD
 792 rrrrr!0,000110,RRRRR:I:::satadd
 793 "satadd r<reg1>, r<reg2>"
 794 {
 795   COMPAT_1 (OP_C0 ());
 796 }
 797
 798 rrrrr!0,010001,iiiii:II:::satadd
 799 "satadd <imm5>, r<reg2>"
 800 {
 801   COMPAT_1 (OP_220 ());
 802 }
 803
 804
 805
 806 // SATSUB
 807 rrrrr!0,000101,RRRRR:I:::satsub
 808 "satsub r<reg1>, r<reg2>"
 809 {
 810   COMPAT_1 (OP_A0 ());
 811 }
 812
 813
 814
 815 // SATSUBI
 816 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
 817 "satsubi <simm16>, r<reg1>, r<reg2>"
 818 {
 819   COMPAT_2 (OP_660 ());
 820 }
 821
 822
 823
 824 // SATSUBR
 825 rrrrr!0,000100,RRRRR:I:::satsubr
 826 "satsubr r<reg1>, r<reg2>"
 827 {
 828   COMPAT_1 (OP_80 ());
 829 }
 830
 831
 832
 833 // SETF
 834 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
 835 "setf %s<cccc>, r<reg2>"
 836 {
 837   COMPAT_2 (OP_7E0 ());
 838 }
 839
 840
 841
 842 // SET1
 843 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
 844 "set1 <bit3>, <disp16>[r<reg1>]"
 845 {
 846   COMPAT_2 (OP_7C0 ());
 847 }
 848
 849 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
 850 *v850e
 851 "set1 r<reg2>, [r<reg1>]"
 852 {
 853   COMPAT_2 (OP_E007E0 ());
 854 }
 855
 856
 857
 858 // SHL
 859 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
 860 "shl r<reg1>, r<reg2>"
 861 {
 862   COMPAT_2 (OP_C007E0 ());
 863 }
 864
 865 rrrrr,010110,iiiii:II:::shl
 866 "shl <imm5>, r<reg2>"
 867 {
 868   COMPAT_1 (OP_2C0 ());
 869 }
 870
 871
 872
 873 // SHR
 874 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
 875 "shr r<reg1>, r<reg2>"
 876 {
 877   COMPAT_2 (OP_8007E0 ());
 878 }
 879
 880 rrrrr,010100,iiiii:II:::shr
 881 "shr <imm5>, r<reg2>"
 882 {
 883   COMPAT_1 (OP_280 ());
 884 }
 885
 886
 887
 888 // SLD
 889 rrrrr,0110,ddddddd:IV:::sld.b
 890 "sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
 891 "sld.b <disp7>[ep], r<reg2>"
 892 {
 893   unsigned32 addr = EP + disp7;
 894   unsigned32 result = load_mem (addr, 1);
 895   if (PSW & PSW_US)
 896     {
 897       GR[reg2] = result;
 898       TRACE_LD_NAME ("sld.bu", addr, result);
 899     }
 900   else
 901     {
 902       result = EXTEND8 (result);
 903       GR[reg2] = result;
 904       TRACE_LD (addr, result);
 905     }
 906 }
 907
 908 rrrrr,1000,ddddddd:IV:::sld.h
 909 "sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
 910 "sld.h <disp8>[ep], r<reg2>"
 911 {
 912   unsigned32 addr = EP + disp8;
 913   unsigned32 result = load_mem (addr, 2);
 914   if (PSW & PSW_US)
 915     {
 916       GR[reg2] = result;
 917       TRACE_LD_NAME ("sld.hu", addr, result);
 918     }
 919   else
 920     {
 921       result = EXTEND16 (result);
 922       GR[reg2] = result;
 923       TRACE_LD (addr, result);
 924     }
 925 }
 926
 927 rrrrr,1010,dddddd,0:IV:::sld.w
 928 "sld.w <disp8>[ep], r<reg2>"
 929 {
 930   unsigned32 addr = EP + disp8;
 931   unsigned32 result = load_mem (addr, 4);
 932   GR[reg2] = result;
 933   TRACE_LD (addr, result);
 934 }
 935
 936 rrrrr!0,0000110,dddd:IV:::sld.bu
 937 *v850e
 938 "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
 939 "sld.bu <disp4>[ep], r<reg2>"
 940 {
 941   unsigned32 addr = EP + disp4;
 942   unsigned32 result = load_mem (addr, 1);
 943   if (PSW & PSW_US)
 944     {
 945       result = EXTEND8 (result);
 946       GR[reg2] = result;
 947       TRACE_LD_NAME ("sld.b", addr, result);
 948     }
 949   else
 950     {
 951       GR[reg2] = result;
 952       TRACE_LD (addr, result);
 953     }
 954 }
 955
 956 rrrrr!0,0000111,dddd:IV:::sld.hu
 957 *v850e
 958 "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
 959 "sld.hu <disp5>[ep], r<reg2>"
 960 {
 961   unsigned32 addr = EP + disp5;
 962   unsigned32 result = load_mem (addr, 2);
 963   if (PSW & PSW_US)
 964     {
 965       result = EXTEND16 (result);
 966       GR[reg2] = result;
 967       TRACE_LD_NAME ("sld.h", addr, result);
 968     }
 969   else
 970     {
 971       GR[reg2] = result;
 972       TRACE_LD (addr, result);
 973     }
 974 }
 975
 976 // SST
 977 rrrrr,0111,ddddddd:IV:::sst.b
 978 "sst.b r<reg2>, <disp7>[ep]"
 979 {
 980   COMPAT_1 (OP_380 ());
 981 }
 982
 983 rrrrr,1001,ddddddd:IV:::sst.h
 984 "sst.h r<reg2>, <disp8>[ep]"
 985 {
 986   COMPAT_1 (OP_480 ());
 987 }
 988
 989 rrrrr,1010,dddddd,1:IV:::sst.w
 990 "sst.w r<reg2>, <disp8>[ep]"
 991 {
 992   COMPAT_1 (OP_501 ());
 993 }
 994
 995 // ST
 996 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
 997 "st.b r<reg2>, <disp16>[r<reg1>]"
 998 {
 999   COMPAT_2 (OP_740 ());
1000 }
1001
1002 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
1003 "st.h r<reg2>, <disp16>[r<reg1>]"
1004 {
1005   COMPAT_2 (OP_760 ());
1006 }
1007
1008 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1009 "st.w r<reg2>, <disp16>[r<reg1>]"
1010 {
1011   COMPAT_2 (OP_10760 ());
1012 }
1013
1014 // STSR
1015 rrrrr,111111,regID + 0000000001000000:IX:::stsr
1016 "stsr s<regID>, r<reg2>"
1017 {
1018   TRACE_ALU_INPUT1 (SR[regID]);
1019   GR[reg2] = SR[regID];
1020   TRACE_ALU_RESULT (GR[reg2]);
1021 }
1022
1023 // SUB
1024 rrrrr,001101,RRRRR:I:::sub
1025 "sub r<reg1>, r<reg2>"
1026 {
1027   COMPAT_1 (OP_1A0 ());
1028 }
1029
1030 // SUBR
1031 rrrrr,001100,RRRRR:I:::subr
1032 "subr r<reg1>, r<reg2>"
1033 {
1034   COMPAT_1 (OP_180 ());
1035 }
1036
1037 // SWITCH
1038 00000000010,RRRRR:I:::switch
1039 *v850e
1040 "switch r<reg1>"
1041 {
1042   unsigned long adr;
1043   SAVE_1;
1044   trace_input ("switch", OP_REG, 0);
1045   adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1046   nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1047   trace_output (OP_REG);
1048 }
1049
1050 // SXB
1051 00000000101,RRRRR:I:::sxb
1052 *v850e
1053 "sxb r<reg1>"
1054 {
1055   TRACE_ALU_INPUT1 (GR[reg1]);
1056   GR[reg1] = EXTEND8 (GR[reg1]);
1057   TRACE_ALU_RESULT (GR[reg1]);
1058 }
1059
1060 // SXH
1061 00000000111,RRRRR:I:::sxh
1062 *v850e
1063 "sxh r<reg1>"
1064 {
1065   TRACE_ALU_INPUT1 (GR[reg1]);
1066   GR[reg1] = EXTEND16 (GR[reg1]);
1067   TRACE_ALU_RESULT (GR[reg1]);
1068 }
1069
1070 // TRAP
1071 00000111111,iiiii + 0000000100000000:X:::trap
1072 "trap <vector>"
1073 {
1074   COMPAT_2 (OP_10007E0 ());
1075 }
1076
1077 // TST
1078 rrrrr,001011,RRRRR:I:::tst
1079 "tst r<reg1>, r<reg2>"
1080 {
1081   COMPAT_1 (OP_160 ());
1082 }
1083
1084 // TST1
1085 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1086 "tst1 <bit3>, <disp16>[r<reg1>]"
1087 {
1088   COMPAT_2 (OP_C7C0 ());
1089 }
1090
1091 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1092 *v850e
1093 "tst1 r<reg2>, [r<reg1>]"
1094 {
1095   COMPAT_2 (OP_E607E0 ());
1096 }
1097
1098 // XOR
1099 rrrrr,001001,RRRRR:I:::xor
1100 "xor r<reg1>, r<reg2>"
1101 {
1102   COMPAT_1 (OP_120 ());
1103 }
1104
1105 // XORI
1106 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1107 "xori <uimm16>, r<reg1>, r<reg2>"
1108 {
1109   COMPAT_2 (OP_6A0 ());
1110 }
1111
1112 // ZXB
1113 00000000100,RRRRR:I:::zxb
1114 *v850e
1115 "zxb r<reg1>"
1116 {
1117   TRACE_ALU_INPUT1 (GR[reg1]);
1118   GR[reg1] = GR[reg1] & 0xff;
1119   TRACE_ALU_RESULT (GR[reg1]);
1120 }
1121
1122 // ZXH
1123 00000000110,RRRRR:I:::zxh
1124 *v850e
1125 "zxh r<reg1>"
1126 {
1127   TRACE_ALU_INPUT1 (GR[reg1]);
1128   GR[reg1] = GR[reg1] & 0xffff;
1129   TRACE_ALU_RESULT (GR[reg1]);
1130 }
1131
1132 // Right field must be zero so that it doesn't clash with DIVH
1133 // Left field must be non-zero so that it doesn't clash with SWITCH
1134 11111,000010,00000:I:::break
1135 {
1136   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1137 }
1138
1139 // New breakpoint: 0x7E0 0x7E0
1140 00000,111111,00000 + 00000,11111,100000:X:::ilgop
1141 {
1142   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1143 }