sim-unisim/BSCANE2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.ALL;
   4
   5 library unisim;
   6 use unisim.vcomponents.all;
   7
   8 entity BSCANE2 is
   9     generic(jtag_chain: INTEGER);
  10     port(capture : out std_logic;
  11          drck    : out std_logic;
  12          reset   : out std_logic;
  13          runtest : out std_logic;
  14          sel     : out std_logic;
  15          shift   : out std_logic;
  16          tck     : out std_logic;
  17          tdi     : out std_logic;
  18          tms     : out std_logic;
  19          update  : out std_logic;
  20          tdo     : in std_logic
  21          );
  22 end BSCANE2;
  23
  24 architecture behaviour of BSCANE2 is
  25     alias j : glob_jtag_t is glob_jtag;
  26 begin
  27     sel <= j.sel(jtag_chain);
  28     tck <= j.tck;
  29     drck <= tck and sel and (capture or shift);
  30     capture <= j.capture;
  31     reset <= j.reset;
  32     runtest <= j.runtest;
  33     shift <= j.shift;
  34     tdi <= j.tdi;
  35     tms <= j.tms;
  36     update <= j.update;
  37     j.tdo <= tdo;
  38 end architecture behaviour;
  39