1 -- Single port Block RAM with one cycle output buffer
3 -- Simulated via C helpers
6 use ieee.std_logic_1164.all;
7 use ieee.numeric_std.all;
12 use work.sim_bram_helpers.all;
16 WIDTH : natural := 64;
17 HEIGHT_BITS : natural := 1024;
18 MEMORY_SIZE : natural := 65536;
19 RAM_INIT_FILE : string
23 addr : in std_logic_vector(HEIGHT_BITS - 1 downto 0) ;
24 di : in std_logic_vector(WIDTH-1 downto 0);
25 do : out std_logic_vector(WIDTH-1 downto 0);
26 sel : in std_logic_vector((WIDTH/8)-1 downto 0);
32 architecture sim of main_bram is
34 constant WIDTH_BYTES : natural := WIDTH / 8;
35 constant pad_zeros : std_ulogic_vector(log2(WIDTH_BYTES)-1 downto 0)
38 signal identifier : integer := behavioural_initialize(filename => RAM_INIT_FILE,
41 signal obuf : std_logic_vector(WIDTH-1 downto 0);
44 -- Actual RAM template
45 memory_0: process(clk)
46 variable ret_dat_v : std_ulogic_vector(63 downto 0);
47 variable addr64 : std_ulogic_vector(63 downto 0);
49 if rising_edge(clk) then
50 addr64 := (others => '0');
51 addr64(HEIGHT_BITS + 2 downto 3) := addr;
53 report "RAM writing " & to_hstring(di) & " to " &
54 to_hstring(addr & pad_zeros) & " sel:" & to_hstring(sel);
55 behavioural_write(di, addr64, to_integer(unsigned(sel)), identifier);
58 behavioural_read(ret_dat_v, addr64, to_integer(unsigned(sel)), identifier);
59 report "RAM reading from " & to_hstring(addr & pad_zeros) &
60 " returns " & to_hstring(ret_dat_v);
61 obuf <= ret_dat_v(obuf'left downto 0);