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37 * Authors: Andreas Hansson
43 * SimpleDRAM declaration
46 #ifndef __MEM_SIMPLE_DRAM_HH__
47 #define __MEM_SIMPLE_DRAM_HH__
51 #include "base/statistics.hh"
52 #include "enums/AddrMap.hh"
53 #include "enums/MemSched.hh"
54 #include "enums/PageManage.hh"
55 #include "mem/abstract_mem.hh"
56 #include "mem/qport.hh"
57 #include "params/SimpleDRAM.hh"
58 #include "sim/eventq.hh"
61 * The simple DRAM is a basic single-channel memory controller aiming
62 * to mimic a high-level DRAM controller and the most important timing
63 * constraints associated with the DRAM. The focus is really on
64 * modelling the impact on the system rather than the DRAM itself,
65 * hence the focus is on the controller model and not on the
66 * memory. By adhering to the correct timing constraints, ultimately
67 * there is no need for a memory model in addition to the controller
70 * As a basic design principle, this controller is not cycle callable,
71 * but instead uses events to decide when new decisions can be made,
72 * when resources become available, when things are to be considered
73 * done, and when to send things back. Through these simple
74 * principles, we achieve a performant model that is not
75 * cycle-accurate, but enables us to evaluate the system impact of a
76 * wide range of memory technologies, and also collect statistics
77 * about the use of the memory.
79 class SimpleDRAM : public AbstractMemory
84 // For now, make use of a queued slave port to avoid dealing with
85 // flow control for the responses being sent back
86 class MemoryPort : public QueuedSlavePort
89 SlavePacketQueue queue;
94 MemoryPort(const std::string& name, SimpleDRAM& _memory);
98 Tick recvAtomic(PacketPtr pkt);
100 void recvFunctional(PacketPtr pkt);
102 bool recvTimingReq(PacketPtr);
104 virtual AddrRangeList getAddrRanges() const;
109 * Our incoming port, for a multi-ported controller add a crossbar
115 * Remember if we have to retry a request when available.
121 * Remember that a row buffer hit occured
126 * Use this flag to shutoff reads, i.e. do not schedule any reads
127 * beyond those already done so that we can turn the bus around
128 * and do a few writes, or refresh, or whatever
132 /** List to keep track of activate ticks */
133 std::deque<Tick> actTicks;
136 * A basic class to track the bank state indirectly via
137 * times "freeAt" and "tRASDoneAt" and what page is currently open
144 static const uint32_t INVALID_ROW = -1;
151 Bank() : openRow(INVALID_ROW), freeAt(0), tRASDoneAt(0)
156 * A DRAM packet stores packets along with the timestamp of when
157 * the packet entered the queue, and also the decoded address.
163 /** When did request enter the controller */
164 const Tick entryTime;
166 /** When will request leave the controller */
169 /** This comes from the outside world */
172 /** Will be populated by address decoder */
179 DRAMPacket(PacketPtr _pkt, uint8_t _rank,
180 uint16_t _bank, uint16_t _row, Addr _addr, Bank& _bank_ref)
181 : entryTime(curTick()), readyTime(curTick()),
182 pkt(_pkt), rank(_rank), bank(_bank), row(_row), addr(_addr),
189 * Bunch of things requires to setup "events" in gem5
190 * When event "writeEvent" occurs for example, the method
191 * processWriteEvent is called; no parameters are allowed
194 void processWriteEvent();
195 EventWrapper<SimpleDRAM, &SimpleDRAM::processWriteEvent> writeEvent;
197 void processRespondEvent();
198 EventWrapper<SimpleDRAM, &SimpleDRAM::processRespondEvent> respondEvent;
200 void processRefreshEvent();
201 EventWrapper<SimpleDRAM, &SimpleDRAM::processRefreshEvent> refreshEvent;
203 void processNextReqEvent();
204 EventWrapper<SimpleDRAM,&SimpleDRAM::processNextReqEvent> nextReqEvent;
208 * Check if the read queue has room for more entries
210 * @return true if read queue is full, false otherwise
212 bool readQueueFull() const;
215 * Check if the write queue has room for more entries
217 * @return true if write queue is full, false otherwise
219 bool writeQueueFull() const;
222 * When a new read comes in, first check if the write q has a
223 * pending request to the same address.\ If not, decode the
224 * address to populate rank/bank/row, create a "dram_pkt", and
225 * push it to the back of the read queue.\ If this is the only
226 * read request in the system, schedule an event to start
229 * @param pkt The request packet from the outside world
231 void addToReadQueue(PacketPtr pkt);
234 * Decode the incoming pkt, create a dram_pkt and push to the
235 * back of the write queue. \If the write q length is more than
236 * the threshold specified by the user, ie the queue is beginning
237 * to get full, stop reads, and start draining writes.
239 * @param pkt The request packet from the outside world
241 void addToWriteQueue(PacketPtr pkt);
244 * Actually do the DRAM access - figure out the latency it
245 * will take to service the req based on bank state, channel state etc
246 * and then update those states to account for this request.\ Based
247 * on this, update the packet's "readyTime" and move it to the
248 * response q from where it will eventually go back to the outside
251 * @param pkt The DRAM packet created from the outside world pkt
253 void doDRAMAccess(DRAMPacket* dram_pkt);
256 * Check when the channel is free to turnaround, add turnaround
257 * delay and schedule a whole bunch of writes.
259 void triggerWrites();
262 * When a packet reaches its "readyTime" in the response Q,
263 * use the "access()" method in AbstractMemory to actually
264 * create the response packet, and send it back to the outside
267 * @param pkt The packet from the outside world
269 void accessAndRespond(PacketPtr pkt);
272 * Address decoder to figure out physical mapping onto ranks,
275 * @param pkt The packet from the outside world
276 * @return A DRAMPacket pointer with the decoded information
278 DRAMPacket* decodeAddr(PacketPtr pkt);
281 * The memory schduler/arbiter - picks which read request needs to
282 * go next, based on the specified policy such as FCFS or FR-FCFS
283 * and moves it to the head of the read queue.
285 * @return True if a request was chosen and false if queue is empty
287 bool chooseNextRead();
290 * Calls chooseNextReq() to pick the right request, then calls
291 * doDRAMAccess on that request in order to actually service
294 void scheduleNextReq();
297 *Looks at the state of the banks, channels, row buffer hits etc
298 * to estimate how long a request will take to complete.
300 * @param dram_pkt The request for which we want to estimate latency
301 * @param inTime The tick at which you want to probe the memory
303 * @return A pair of ticks, one indicating how many ticks *after*
304 * inTime the request require, and the other indicating how
305 * much of that was just the bank access time, ignoring the
306 * ticks spent simply waiting for resources to become free
308 std::pair<Tick, Tick> estimateLatency(DRAMPacket* dram_pkt, Tick inTime);
311 * Move the request at the head of the read queue to the response
312 * queue, sorting by readyTime.\ If it is the only packet in the
313 * response queue, schedule a respond event to send it back to the
319 * Scheduling policy within the write queue
321 void chooseNextWrite();
324 * Looking at all banks, determine the moment in time when they
327 * @return The tick when all banks are free
329 Tick maxBankFreeAt() const;
333 * Keep track of when row activations happen, in order to enforce
334 * the maximum number of activations in the activation window. The
335 * method updates the time that the banks become available based
336 * on the current limits.
338 void recordActivate(Tick act_tick);
340 void printParams() const;
341 void printQs() const;
344 * The controller's main read and write queues
346 std::list<DRAMPacket*> readQueue;
347 std::list<DRAMPacket*> writeQueue;
350 * Response queue where read packets wait after we're done working
351 * with them, but it's not time to send the response yet. The
352 * responses are stored seperately mostly to keep the code clean
353 * and help with events scheduling. For all logical purposes such
354 * as sizing the read queue, this and the main read queue need to
357 std::list<DRAMPacket*> respQueue;
360 * If we need to drain, keep the drain manager around until we're
363 DrainManager *drainManager;
366 * Multi-dimensional vector of banks, first dimension is ranks,
369 std::vector<std::vector<Bank> > banks;
372 * The following are basic design parameters of the memory
373 * controller, and are initialized based on parameter values. The
374 * bytesPerCacheLine is based on the neighbouring ports cache line
375 * size and thus determined outside the constructor. Similarly,
376 * the rowsPerBank is determined based on the capacity, number of
377 * ranks and banks, the cache line size, and the row buffer size.
379 uint32_t bytesPerCacheLine;
380 const uint32_t linesPerRowBuffer;
381 const uint32_t ranksPerChannel;
382 const uint32_t banksPerRank;
383 const uint32_t channels;
384 uint32_t rowsPerBank;
385 const uint32_t readBufferSize;
386 const uint32_t writeBufferSize;
387 const double writeThresholdPerc;
388 uint32_t writeThreshold;
391 * Basic memory timing parameters initialized based on parameter
402 const uint32_t activationLimit;
405 * Memory controller configuration initialized based on parameter
408 Enums::MemSched memSchedPolicy;
409 Enums::AddrMap addrMapping;
410 Enums::PageManage pageMgmt;
413 * Till when has the main data bus been spoken for already?
421 // All statistics that the model needs to capture
422 Stats::Scalar readReqs;
423 Stats::Scalar writeReqs;
424 Stats::Scalar cpuReqs;
425 Stats::Scalar bytesRead;
426 Stats::Scalar bytesWritten;
427 Stats::Scalar bytesConsumedRd;
428 Stats::Scalar bytesConsumedWr;
429 Stats::Scalar servicedByWrQ;
430 Stats::Scalar neitherReadNorWrite;
431 Stats::Vector perBankRdReqs;
432 Stats::Vector perBankWrReqs;
433 Stats::Scalar numRdRetry;
434 Stats::Scalar numWrRetry;
435 Stats::Scalar totGap;
436 Stats::Vector readPktSize;
437 Stats::Vector writePktSize;
438 Stats::Vector rdQLenPdf;
439 Stats::Vector wrQLenPdf;
442 // Latencies summed over all requests
443 Stats::Scalar totQLat;
444 Stats::Scalar totMemAccLat;
445 Stats::Scalar totBusLat;
446 Stats::Scalar totBankLat;
448 // Average latencies per request
449 Stats::Formula avgQLat;
450 Stats::Formula avgBankLat;
451 Stats::Formula avgBusLat;
452 Stats::Formula avgMemAccLat;
455 Stats::Formula avgRdBW;
456 Stats::Formula avgWrBW;
457 Stats::Formula avgConsumedRdBW;
458 Stats::Formula avgConsumedWrBW;
459 Stats::Formula peakBW;
460 Stats::Formula busUtil;
462 // Average queue lengths
463 Stats::Average avgRdQLen;
464 Stats::Average avgWrQLen;
466 // Row hit count and rate
467 Stats::Scalar readRowHits;
468 Stats::Scalar writeRowHits;
469 Stats::Formula readRowHitRate;
470 Stats::Formula writeRowHitRate;
471 Stats::Formula avgGap;
473 /** @todo this is a temporary workaround until the 4-phase code is
474 * committed. upstream caches needs this packet until true is returned, so
475 * hold onto it for deletion until a subsequent call
477 std::vector<PacketPtr> pendingDelete;
483 SimpleDRAM(const SimpleDRAMParams* p);
485 unsigned int drain(DrainManager* dm);
487 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
488 PortID idx = InvalidPortID);
491 virtual void startup();
495 Tick recvAtomic(PacketPtr pkt);
496 void recvFunctional(PacketPtr pkt);
497 bool recvTimingReq(PacketPtr pkt);
501 #endif //__MEM_SIMPLE_DRAM_HH__