3492360cdc4cd898a6ebd84161a2d7820c529749
2 * Copyright (c) 2010-2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
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21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Ron Dreslinski
45 #include "base/random.hh"
46 #include "mem/simple_mem.hh"
50 SimpleMemory::SimpleMemory(const SimpleMemoryParams
* p
) :
52 port(name() + ".port", *this), lat(p
->latency
),
53 lat_var(p
->latency_var
), bandwidth(p
->bandwidth
),
54 isBusy(false), retryReq(false), releaseEvent(this)
61 // allow unconnected memories as this is used in several ruby
62 // systems at the moment
63 if (port
.isConnected()) {
64 port
.sendRangeChange();
69 SimpleMemory::calculateLatency(PacketPtr pkt
)
71 if (pkt
->memInhibitAsserted()) {
76 latency
+= random_mt
.random
<Tick
>(0, lat_var
);
82 SimpleMemory::doAtomicAccess(PacketPtr pkt
)
85 return calculateLatency(pkt
);
89 SimpleMemory::doFunctionalAccess(PacketPtr pkt
)
91 functionalAccess(pkt
);
95 SimpleMemory::recvTimingReq(PacketPtr pkt
)
97 /// @todo temporary hack to deal with memory corruption issues until
98 /// 4-phase transactions are complete
99 for (int x
= 0; x
< pendingDelete
.size(); x
++)
100 delete pendingDelete
[x
];
101 pendingDelete
.clear();
103 if (pkt
->memInhibitAsserted()) {
104 // snooper will supply based on copy of packet
105 // still target's responsibility to delete packet
106 pendingDelete
.push_back(pkt
);
110 // we should never get a new request after committing to retry the
111 // current one, the bus violates the rule as it simply sends a
112 // retry to the next one waiting on the retry list, so simply
117 // if we are busy with a read or write, remember that we have to
124 // @todo someone should pay for this
125 pkt
->busFirstWordDelay
= pkt
->busLastWordDelay
= 0;
127 // update the release time according to the bandwidth limit, and
128 // do so with respect to the time it takes to finish this request
129 // rather than long term as it is the short term data rate that is
130 // limited for any real memory
132 // only look at reads and writes when determining if we are busy,
133 // and for how long, as it is not clear what to regulate for the
134 // other types of commands
135 if (pkt
->isRead() || pkt
->isWrite()) {
136 // calculate an appropriate tick to release to not exceed
137 // the bandwidth limit
138 Tick duration
= pkt
->getSize() * bandwidth
;
140 // only consider ourselves busy if there is any need to wait
141 // to avoid extra events being scheduled for (infinitely) fast
144 schedule(releaseEvent
, curTick() + duration
);
149 // go ahead and deal with the packet and put the response in the
150 // queue if there is one
151 bool needsResponse
= pkt
->needsResponse();
152 Tick latency
= doAtomicAccess(pkt
);
153 // turn packet around to go back to requester if response expected
155 // doAtomicAccess() should already have turned packet into
157 assert(pkt
->isResponse());
158 port
.schedTimingResp(pkt
, curTick() + latency
);
160 pendingDelete
.push_back(pkt
);
167 SimpleMemory::release()
178 SimpleMemory::getSlavePort(const std::string
&if_name
, PortID idx
)
180 if (if_name
!= "port") {
181 return MemObject::getSlavePort(if_name
, idx
);
188 SimpleMemory::drain(DrainManager
*dm
)
190 int count
= port
.drain(dm
);
193 setDrainState(Drainable::Draining
);
195 setDrainState(Drainable::Drained
);
199 SimpleMemory::MemoryPort::MemoryPort(const std::string
& _name
,
200 SimpleMemory
& _memory
)
201 : QueuedSlavePort(_name
, &_memory
, queueImpl
),
202 queueImpl(_memory
, *this), memory(_memory
)
206 SimpleMemory::MemoryPort::getAddrRanges() const
208 AddrRangeList ranges
;
209 ranges
.push_back(memory
.getAddrRange());
214 SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt
)
216 return memory
.doAtomicAccess(pkt
);
220 SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt
)
222 pkt
->pushLabel(memory
.name());
224 if (!queue
.checkFunctional(pkt
)) {
225 // Default implementation of SimpleTimingPort::recvFunctional()
226 // calls recvAtomic() and throws away the latency; we can save a
227 // little here by just not calculating the latency.
228 memory
.doFunctionalAccess(pkt
);
235 SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt
)
237 return memory
.recvTimingReq(pkt
);
241 SimpleMemoryParams::create()
243 return new SimpleMemory(this);