simple_v_extension/daxpy_example.mdwn

   1 # c code
   2
   3 ```
   4     void daxpy(size_t n, double a, const double x[], double y[])
   5     {
   6      for (size_t i = 0; i < n; i++) {
   7        y[i] = a*x[i] + y[i];
   8      }
   9     }
  10 ```
  11
  12 # SVP64 Power ISA version
  13
  14 Summary: 9 instructions (see below, 8 instructions) 5 of which are 64-bit
  15 for a total of 14 "words".
  16
  17 ```
  18     # r5: n count
  19     # r6: x ptr
  20     # r7: y ptr
  21     # fp1: a mul-scalar
  22     1  mtctr 5                # move n to CTR
  23     2  addi r10,r6,0          # copy y-ptr into r10 (y')
  24     3  .L2
  25     4  setvl MAXVL=32,VL=CTR  # actually VL=MIN(MAXVL,CTR)
  26     5  sv.lfdup *32,8(6)      # load x into fp32-63, inc x
  27     6  sv.lfdup *64,8(7)      # load y into fp64-95, inc y
  28     7  sv.fmadd *64,*64,1,*32 # (*y) = (*y) * (*x) + fp1
  29     8  sv.stfdup *64,8(10)    # store at y-copy, inc y'
  30     9  sv.bc/ctr .L2          # decrement CTR by VL
  31     10 blr                    # return
  32 ```
  33
  34 A refinement, reducing 1 instruction and register port usage.
  35 Relies on post-increment, relies on no overlap between x and y
  36 in memory, and critically relies on y overwrite.
  37
  38 ```
  39     # r5: n count
  40     # r6: x ptr
  41     # r7: y ptr
  42     # fp1: a mul-scalar
  43     1  mtctr 5                # move n to CTR
  44     2  .L2
  45     3  setvl MAXVL=32,VL=CTR  # actually VL=MIN(MAXVL,CTR)
  46     4  sv.lfdup *32,8(6)      # load x into fp32-63, incr x
  47     5  sv.lfd *64,8(7)        # load y into fp64-95, NO INC
  48     6  sv.fmadd *64,*64,1,*32 # (*y) = (*y) * (*x) + fp1
  49     7  sv.stfdup *64,8(7)     # store at y, incr y
  50     8  sv.bc/ctr .L2          # decrement CTR by VL
  51     9  blr                    # return
  52 ```
  53
  54 # RVV version
  55
  56 Summary: 12 instructions, 7 32-bit and 5 16-bit for a total of 9.5 "words"
  57
  58 ```
  59     # a0 is n, a1 is pointer to x[0], a2 is pointer to y[0], fa0 is a
  60       li t0, 2<<25
  61       vsetdcfg t0             # enable 2 64b Fl.Pt. registers
  62     loop:
  63       setvl  t0, a0           # vl = t0 = min(mvl, n)
  64       vld    v0, a1           # load vector x
  65       c.slli   t1, t0, 3      # t1 = vl * 8 (in bytes)
  66       vld    v1, a2           # load vector y
  67       c.add    a1, a1, t1     # increment pointer to x by vl*8
  68       vfmadd v1, v0, fa0, v1  # v1 += v0 * fa0 (y = a * x + y)
  69       c.sub    a0, a0, t0     # n -= vl (t0)
  70       vst    v1, a2           # store Y
  71       c.add    a2, a2, t1     # increment pointer to y by vl*8
  72       c.bnez   a0, loop       # repeat if n != 0
  73       c.ret                   # return
  74 ```
  75
  76 # SVE Version
  77
  78 ```
  79     1  // x0 = &x[0], x1 = &y[0], x2 = &a, x3 = &n
  80     2  daxpy_:
  81     3  ldrswx3, [x3]                     // x3=*n
  82     4  movx4, #0                         // x4=i=0
  83     5  whilelt p0.d, x4, x3              // p0=while(i++<n)
  84     6  ld1rdz0.d, p0/z, [x2]             // p0:z0=bcast(*a)
  85     7  .loop:
  86     8  ld1d z1.d, p0/z, [x0, x4, lsl #3] // p0:z1=x[i]
  87     9  ld1d z2.d, p0/z, [x1, x4, lsl #3] // p0:z2=y[i]
  88     10 fmla z2.d, p0/m, z1.d, z0.d       // p0?z2+=x[i]*a
  89     11 st1d z2.d, p0, [x1, x4, lsl #3]   // p0?y[i]=z2
  90     12 incd x4                           // i+=(VL/64)
  91     13 .latch:
  92     14 whilelt p0.d, x4, x3             // p0=while(i++<n)
  93     15 b.first .loop                    // more to do?
  94     16 ret
  95 ```