1 # SimpleV Instruction Categorisation
3 Based on information from Michael Clark's riscv-meta opcodes table, this
4 page categorises and identifies the type of parallelism that SimpleV
5 indirectly adds on each RISC-V **standard** opcode. These are note-form:
6 see [[specification]] for full details.
8 * **-** no change of behaviour takes place: operation remains
9 **completely scalar** as an **unmodified**, unaugmented standard RISC-V
10 opcode, even if it has registers.
11 * **sv** - a standard contiguous (optionally predicated, optionally
12 indirected) multi-register operation where the predication register
13 to be used for the sequence of contiguous operations is taken from the
14 **destination** register's predication lookup entry.
15 * **2v** - a standard contiguous (optionally twin-predicated, optionally
16 indirected) twin-register operation (distinct source and destination)
17 where either or both of source or destination may be redirected,
18 vectorised, or **independently** predicated. This behaviour
19 covers the *entire* MV, VSPLAT, VINSERT, VREDUCE, VSCATTER, VGATHER
21 * **vld** - a standard contiguous (optionally twin-predicated, optionally
22 indirected) multi-register load operation where either or both of
23 destination register or load-from-address register may be redirected,
24 vectorised or **independently** predicated.
25 * **vst** - a matching multi-register store operation matching **vld**.
26 * **VLU** - a "Unit Stride" variant of **vld** where instead of the
27 source-address register number being (optionally) incremented
28 (and redirected, and predicated) it is the **immediate offset**
29 that is incremented (by the element width of the **source** register)
30 * **VSU** - a similarly "Unit Stride" variant of **vst**.
31 * **VBR** - a standard branch operation (optionally predicated, optionally
32 indirected) multi-register operation where the (optional) predication for the
33 compare is taken from the destination register, and where (optionally)
34 if the results of the multi-comparison are to be recorded, the **source**
35 register's predication target is used. On completion of all compares,
36 if the tests carried out succeeded (de-predicated compares not being included
37 in this assessment), the branch operation is carried out.
39 # RV32I/RV64I/RV128I "RV32I/RV64I/RV128I Base Integer Instruction Set"
41 | (23..18) | (17..12) | (11..6) | (5...0) | |
42 | -------- | -------- | ------- | ------- | |
43 |auipc | rd oimm20 | u+o | rv32i rv64i rv128i | - |
44 |jal | rd jimm20 | uj | rv32i rv64i rv128i | - |
45 |jalr | rd rs1 oimm12 | i+o | rv32i rv64i rv128i | - |
46 |fence | | r·f | rv32i rv64i rv128i | - |
47 |fence.i | | none | rv32i rv64i rv128i | - |
48 |lui | rd imm20 | u | rv32i rv64i rv128i | sv |
49 |beq | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR |
50 |bne | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR |
51 |blt | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR |
52 |bge | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR |
53 |bltu | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR |
54 |bgeu | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | VBR |
55 |lb | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vld |
56 |lh | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vld |
57 |lw | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vld |
58 |lbu | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vld |
59 |lhu | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | vld |
60 |lwu | rd rs1 oimm12 | i+l | rv64i rv128i | vld |
61 |ld | rd rs1 oimm12 | i+l | rv64i rv128i | vld |
62 |ldu | rd rs1 oimm12 | i+l | rv128i | vld |
63 |lq | rd rs1 oimm12 | i+l | rv128i | vld |
64 |sb | rs1 rs2 simm12 | s | rv32i rv64i rv128i | vst |
65 |sh | rs1 rs2 simm12 | s | rv32i rv64i rv128i | vst |
66 |sw | rs1 rs2 simm12 | s | rv32i rv64i rv128i | vst |
67 |sd | rs1 rs2 simm12 | s | rv64i rv128i | vst |
68 |sq | rs1 rs2 simm12 | s | rv128i | vst |
69 |addi | rd rs1 imm12 | i | rv32i rv64i rv128i | sv |
70 |slti | rd rs1 imm12 | i | rv32i rv64i rv128i | sv |
71 |sltiu | rd rs1 imm12 | i | rv32i rv64i rv128i | sv |
72 |xori | rd rs1 imm12 | i | rv32i rv64i rv128i | sv |
73 |ori | rd rs1 imm12 | i | rv32i rv64i rv128i | sv |
74 |andi | rd rs1 imm12 | i | rv32i rv64i rv128i | sv |
75 |slli | rd rs1 shamt5 | i·sh5 | rv32i | sv |
76 |srli | rd rs1 shamt5 | i·sh5 | rv32i | sv |
77 |srai | rd rs1 shamt5 | i·sh5 | rv32i | sv |
78 |add | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
79 |sub | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
80 |sll | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
81 |slt | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
82 |sltu | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
83 |xor | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
84 |srl | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
85 |sra | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
86 |or | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
87 |and | rd rs1 rs2 | r | rv32i rv64i rv128i | sv |
88 |slli | rd rs1 shamt6 | i·sh6 | rv64i | sv |
89 |srli | rd rs1 shamt6 | i·sh6 | rv64i | sv |
90 |srai | rd rs1 shamt6 | i·sh6 | rv64i | sv |
91 |addiw | rd rs1 imm12 | i | rv64i rv128i | sv |
92 |slliw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | sv |
93 |srliw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | sv |
94 |sraiw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | sv |
95 |addw | rd rs1 rs2 | r | rv64i rv128i | sv |
96 |subw | rd rs1 rs2 | r | rv64i rv128i | sv |
97 |sllw | rd rs1 rs2 | r | rv64i rv128i | sv |
98 |srlw | rd rs1 rs2 | r | rv64i rv128i | sv |
99 |sraw | rd rs1 rs2 | r | rv64i rv128i | sv |
100 |slli | rd rs1 shamt7 | i·sh7 | rv128i | sv |
101 |srli | rd rs1 shamt7 | i·sh7 | rv128i | sv |
102 |srai | rd rs1 shamt7 | i·sh7 | rv128i | sv |
103 |addid | rd rs1 imm12 | i | rv128i | sv |
104 |sllid | rd rs1 shamt6 | i·sh6 | rv128i | sv |
105 |srlid | rd rs1 shamt6 | i·sh6 | rv128i | sv |
106 |sraid | rd rs1 shamt6 | i·sh6 | rv128i | sv |
107 |addd | rd rs1 rs2 | r | rv128i | sv |
108 |subd | rd rs1 rs2 | r | rv128i | sv |
109 |slld | rd rs1 rs2 | r | rv128i | sv |
110 |srld | rd rs1 rs2 | r | rv128i | sv |
111 |srad | rd rs1 rs2 | r | rv128i | sv |
113 # RV32M "RV32M Standard Extension for Integer Multiply and Divide"
115 | (23..18) | (17..12) | (11..6) | (5...0) | |
116 | -------- | -------- | ------- | ------- | |
117 |mul | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
118 |mulh | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
119 |mulhsu | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
120 |mulhu | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
121 |div | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
122 |divu | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
123 |rem | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
124 |remu | rd rs1 rs2 | r | rv32m rv64m rv128m | sv |
126 # RV64M "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)"
128 | (23..18) | (17..12) | (11..6) | (5...0) | |
129 | -------- | -------- | ------- | ------- | |
130 |mulw | rd rs1 rs2 | r | rv64m rv128m | sv |
131 |divw | rd rs1 rs2 | r | rv64m rv128m | sv |
132 |divuw | rd rs1 rs2 | r | rv64m rv128m | sv |
133 |remw | rd rs1 rs2 | r | rv64m rv128m | sv |
134 |remuw | rd rs1 rs2 | r | rv64m rv128m | sv |
136 # RV128M "RV128M Standard Extension for Integer Multiply and Divide (in addition to RV64M)"
138 | (23..18) | (17..12) | (11..6) | (5...0) | |
139 | -------- | -------- | ------- | ------- | |
140 |muld | rd rs1 rs2 | r | rv128m | sv |
141 |divd | rd rs1 rs2 | r | rv128m | sv |
142 |divud | rd rs1 rs2 | r | rv128m | sv |
143 |remd | rd rs1 rs2 | r | rv128m | sv |
144 |remud | rd rs1 rs2 | r | rv128m | sv |
146 # RV32A "RV32A Standard Extension for Atomic Instructions"
148 | (23..18) | (17..12) | (11..6) | (5...0) | |
149 | -------- | -------- | ------- | ------- | |
150 |lr.w | rd rs1 | r·l | rv32a rv64a rv128a | - |
151 |sc.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | - |
152 |amoswap.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
153 |amoadd.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
154 |amoxor.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
155 |amoor.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
156 |amoand.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
157 |amomin.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
158 |amomax.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
159 |amominu.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
160 |amomaxu.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | sv |
162 # RV64A "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)"
164 | (23..18) | (17..12) | (11..6) | (5...0) | |
165 | -------- | -------- | ------- | ------- | |
166 |lr.d | rd rs1 | r·l | rv64a rv128a | - |
167 |sc.d | rd rs1 rs2 | r·a | rv64a rv128a | - |
168 |amoswap.d| rd rs1 rs2 | r·a | rv64a rv128a | sv |
169 |amoadd.d | rd rs1 rs2 | r·a | rv64a rv128a | sv |
170 |amoxor.d | rd rs1 rs2 | r·a | rv64a rv128a | sv |
171 |amoor.d | rd rs1 rs2 | r·a | rv64a rv128a | sv |
172 |amoand.d | rd rs1 rs2 | r·a | rv64a rv128a | sv |
173 |amomin.d | rd rs1 rs2 | r·a | rv64a rv128a | sv |
174 |amomax.d | rd rs1 rs2 | r·a | rv64a rv128a | sv |
175 |amominu.d| rd rs1 rs2 | r·a | rv64a rv128a | sv |
176 |amomaxu.d| rd rs1 rs2 | r·a | rv64a rv128a | sv |
178 # RV128A "RV128A Standard Extension for Atomic Instructions (in addition to RV64A)"
180 | (23..18) | (17..12) | (11..6) | (5...0) | |
181 | -------- | -------- | ------- | ------- | |
182 |lr.q | rd rs1 | r·l | rv128a | - |
183 |sc.q | rd rs1 rs2 | r·a | rv128a | - |
184 |amoswap.q| rd rs1 rs2 | r·a | rv128a | sv |
185 |amoadd.q | rd rs1 rs2 | r·a | rv128a | sv |
186 |amoxor.q | rd rs1 rs2 | r·a | rv128a | sv |
187 |amoor.q | rd rs1 rs2 | r·a | rv128a | sv |
188 |amoand.q | rd rs1 rs2 | r·a | rv128a | sv |
189 |amomin.q | rd rs1 rs2 | r·a | rv128a | sv |
190 |amomax.q | rd rs1 rs2 | r·a | rv128a | sv |
191 |amominu.q| rd rs1 rs2 | r·a | rv128a | sv |
192 |amomaxu.q| rd rs1 rs2 | r·a | rv128a | sv |
194 # RV32S "RV32S Standard Extension for Supervisor-level Instructions"
196 | (23..18) | (17..12) | (11..6) | (5...0) | |
197 | -------- | -------- | ------- | ------- | |
198 |ecall | | none | rv32s rv64s rv128s | - |
199 |ebreak | | none | rv32s rv64s rv128s | - |
200 |uret | | none | rv32s rv64s rv128s | - |
201 |sret | | none | rv32s rv64s rv128s | - |
202 |hret | | none | rv32s rv64s rv128s | - |
203 |mret | | none | rv32s rv64s rv128s | - |
204 |dret | | none | rv32s rv64s rv128s | - |
205 |sfence.vm | rs1 | r+sf | rv32s rv64s rv128s | - |
206 |sfence.vma| rs1 rs2 | r+sfa | rv32s rv64s rv128s | - |
207 |wfi | | none | rv32s rv64s rv128s | - |
208 |csrrw | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | ? |
209 |csrrs | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | ? |
210 |csrrc | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | ? |
211 |csrrwi | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | ? |
212 |csrrsi | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | ? |
213 |csrrci | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | ? |
215 # RV32F "RV32F Standard Extension for Single-Precision Floating-Point"
217 | (23..18) | (17..12) | (11..6) | (5...0) | |
218 | -------- | -------- | ------- | ------- | |
219 |flw | frd rs1 oimm12 | i+lf | rv32f rv64f rv128f | vld |
220 |fsw | rs1 frs2 simm12 | s+f | rv32f rv64f rv128f | vld |
221 |fmadd.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | sv |
222 |fmsub.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | sv |
223 |fnmsub.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | sv |
224 |fnmadd.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | sv |
225 |fadd.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | sv |
226 |fsub.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | sv |
227 |fmul.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | sv |
228 |fdiv.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | sv |
229 |fmin.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | sv |
230 |fmax.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | sv |
231 |fsqrt.s | frd frs1 rm | r·m+ff | rv32f rv64f rv128f | sv |
232 |fle.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | sv |
233 |flt.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | sv |
234 |feq.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | sv |
235 |fclass.s | rd frs1 | r+rf | rv32f rv64f rv128f | sv |
236 |fsgnj.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | 2v |
237 |fsgnjn.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | 2v |
238 |fsgnjx.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | 2v |
239 |fcvt.w.s | rd frs1 rm | r·m+rf | rv32f rv64f rv128f | 2v |
240 |fcvt.wu.s| rd frs1 rm | r·m+rf | rv32f rv64f rv128f | 2v |
241 |fcvt.s.w | frd rs1 rm | r·m+fr | rv32f rv64f rv128f | 2v |
242 |fcvt.s.wu| frd rs1 rm | r·m+fr | rv32f rv64f rv128f | 2v |
243 |fmv.x.s | rd frs1 | r+rf | rv32f rv64f rv128f | 2v |
244 |fmv.s.x | frd rs1 | r+fr | rv32f rv64f rv128f | 2v |
246 # RV64F "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)"
248 | (23..18) | (17..12) | (11..6) | (5...0) | |
249 | -------- | -------- | ------- | ------- | |
250 |fcvt.l.s | rd frs1 rm | r·m+rf | rv64f rv128f | 2v |
251 |fcvt.lu.s| rd frs1 rm | r·m+rf | rv64f rv128f | 2v |
252 |fcvt.s.l | frd rs1 rm | r·m+fr | rv64f rv128f | 2v |
253 |fcvt.s.lu| frd rs1 rm | r·m+fr | rv64f rv128f | 2v |
255 # RV32D "RV32D Standard Extension for Double-Precision Floating-Point"
257 | (23..18) | (17..12) | (11..6) | (5...0) | |
258 | -------- | -------- | ------- | ------- | |
259 |fld | frd rs1 oimm12 | i+lf | rv32d rv64d rv128d | vld |
260 |fsd | rs1 frs2 simm12 | s+f | rv32d rv64d rv128d | vld |
261 |fmadd.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | sv |
262 |fmsub.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | sv |
263 |fnmsub.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | sv |
264 |fnmadd.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | sv |
265 |fadd.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | sv |
266 |fsub.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | sv |
267 |fmul.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | sv |
268 |fdiv.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | sv |
269 |fmin.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | sv |
270 |fmax.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | sv |
271 |fsqrt.d | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | sv |
272 |fle.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | sv |
273 |flt.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | sv |
274 |feq.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | sv |
275 |fclass.d | rd frs1 | r+rf | rv32d rv64d rv128d | sv |
276 |fsgnj.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | 2v |
277 |fsgnjn.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | 2v |
278 |fsgnjx.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | 2v |
279 |fcvt.s.d | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | 2v |
280 |fcvt.d.s | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | 2v |
281 |fcvt.w.d | rd frs1 rm | r·m+rf | rv32d rv64d rv128d | 2v |
282 |fcvt.wu.d| rd frs1 rm | r·m+rf | rv32d rv64d rv128d | 2v |
283 |fcvt.d.w | frd rs1 rm | r·m+fr | rv32d rv64d rv128d | 2v |
284 |fcvt.d.wu| frd rs1 rm | r·m+fr | rv32d rv64d rv128d | 2v |
286 # RV64D "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)"
288 | (23..18) | (17..12) | (11..6) | (5...0) | |
289 | -------- | -------- | ------- | ------- | |
290 |fcvt.l.d | rd frs1 rm | r·m+rf | rv64d rv128d | 2v |
291 |fcvt.lu.d| rd frs1 rm | r·m+rf | rv64d rv128d | 2v |
292 |fmv.x.d | rd frs1 | r+rf | rv64d rv128d | 2v |
293 |fcvt.d.l | frd rs1 rm | r·m+fr | rv64d rv128d | 2v |
294 |fcvt.d.lu| frd rs1 rm | r·m+fr | rv64d rv128d | 2v |
295 |fmv.d.x | frd rs1 | r+fr | rv64d rv128d | 2v |
297 # RV32Q "RV32Q Standard Extension for Quad-Precision Floating-Point"
299 | (23..18) | (17..12) | (11..6) | (5...0) | |
300 | -------- | -------- | ------- | ------- | |
301 |flq | frd rs1 oimm12 | i+lf | rv32q rv64q rv128q | vld |
302 |fsq | rs1 frs2 simm12 | s+f | rv32q rv64q rv128q | vst |
303 |fmadd.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | sv |
304 |fmsub.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | sv |
305 |fnmsub.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | sv |
306 |fnmadd.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | sv |
307 |fadd.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | sv |
308 |fsub.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | sv |
309 |fmul.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | sv |
310 |fdiv.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | sv |
311 |fmin.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | sv |
312 |fmax.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | sv |
313 |fsqrt.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | sv |
314 |fle.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | sv |
315 |flt.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | sv |
316 |feq.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | sv |
317 |fclass.q | rd frs1 | r+rf | rv32q rv64q rv128q | sv |
318 |fsgnj.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | 2v |
319 |fsgnjn.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | 2v |
320 |fsgnjx.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | 2v |
321 |fcvt.s.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | 2v |
322 |fcvt.q.s | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | 2v |
323 |fcvt.d.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | 2v |
324 |fcvt.q.d | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | 2v |
325 |fcvt.w.q | rd frs1 rm | r·m+rf | rv32q rv64q rv128q | 2v |
326 |fcvt.wu.q| rd frs1 rm | r·m+rf | rv32q rv64q rv128q | 2v |
327 |fcvt.q.w | frd rs1 rm | r·m+fr | rv32q rv64q rv128q | 2v |
328 |fcvt.q.wu| frd rs1 rm | r·m+fr | rv32q rv64q rv128q | 2v |
330 # RV64Q "RV64Q Standard Extension for Quad-Precision Floating-Point (in addition to RV32Q)"
332 | (23..18) | (17..12) | (11..6) | (5...0) | |
333 | -------- | -------- | ------- | ------- | |
334 |fcvt.l.q | rd frs1 rm | r·m+rf | rv64q rv128q | 2v |
335 |fcvt.lu.q| rd frs1 rm | r·m+rf | rv64q rv128q | 2v |
336 |fcvt.q.l | frd rs1 rm | r·m+fr | rv64q rv128q | 2v |
337 |fcvt.q.lu| frd rs1 rm | r·m+fr | rv64q rv128q | 2v |
339 # RV128Q "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)"
341 | (23..18) | (17..12) | (11..6) | (5...0) | |
342 | -------- | -------- | ------- | ------- | |
343 |fmv.x.q | rd frs1 | r+rf | rv64q rv128q | 2v |
344 |fmv.q.x | frd rs1 | r+fr | rv64q rv128q | 2v |
346 # RV32C/RV64C/RV128C "RV32C/RV64C/RV128C Standard Extension for Compressed Instructions"
348 | (23..18) | (17..12) | (11..6) | (5...0) | |
349 | -------- | -------- | ------- | ------- | |
350 |c.addi4spn|crdq cimm4spn | ciw·4spn | rv32c rv64c | - |
351 |c.nop | | ci·none | rv32c rv64c | - |
352 |c.jal | cimmj | cj·jal | rv32c | - |
353 |c.j | cimmj | cj | rv32c rv64c | - |
354 |c.jr | crd0 crs1 | cr·jr | rv32c rv64c | - |
355 |c.ebreak | | ci·none | rv32c rv64c | - |
356 |c.jalr | crd0 crs1 | cr·jalr | rv32c rv64c | - |
357 |c.mv | crd crs2 | cr·mv | rv32c rv64c | 2v |
358 |c.fld | cfrdq crs1q cimmd | cl·ld+f | rv32c rv64c | vld |
359 |c.lw | crdq crs1q cimmw | cl·lw | rv32c rv64c | vld |
360 |c.flw | cfrdq crs1q cimmw | cl·lw+f | rv32c | vld |
361 |c.ld | crdq crs1q cimmd | cl·ld | rv64c | vld |
362 |c.lq | crdq crs1q cimmq | cl·lq | rv128c | vld |
363 |c.fsd | crs1q cfrs2q cimmd | cs·sd+f | rv32c rv64c | vst |
364 |c.sw | crs1q crs2q cimmw | cs·sw | rv32c rv64c | vst |
365 |c.fsw | crs1q cfrs2q cimmw | cs·sw+f | rv32c | vst |
366 |c.sd | crs1q crs2q cimmd | cs·sd | rv64c | vst |
367 |c.sq | crs1q crs2q cimmq | cs·sq | rv128c | vst |
368 |c.addi16sp|crs1rd cimm16sp | ci·16sp | rv32c rv64c | TODO: special-case in spike-sv (disable SV mode) |
369 |c.addi | crs1rd cnzimmi | ci | rv32c rv64c | sv |
370 |c.li | crs1rd cimmi | ci·li | rv32c rv64c | sv |
371 |c.lui | crd cimmui | ci·lui | rv32c rv64c | sv |
372 |c.srli | crs1rdq cimmsh5 | cb·sh5 | rv32c | sv |
373 |c.srai | crs1rdq cimmsh5 | cb·sh5 | rv32c | sv |
374 |c.slli | crs1rd cimmsh5 | ci·sh5 | rv32c | sv |
375 |c.andi | crs1rdq cnzimmi | cb·imm | rv32c rv64c | sv |
376 |c.sub | crs1rdq crs2q | cs | rv32c rv64c | sv |
377 |c.xor | crs1rdq crs2q | cs | rv32c rv64c | sv |
378 |c.or | crs1rdq crs2q | cs | rv32c rv64c | sv |
379 |c.and | crs1rdq crs2q | cs | rv32c rv64c | sv |
380 |c.subw | crs1rdq crs2q | cs | rv32c rv64c | sv |
381 |c.addw | crs1rdq crs2q | cs | rv32c rv64c | sv |
382 |c.add | crs1rd crs2 | cr | rv32c rv64c | sv |
383 |c.addiw | crs1rd cimmi | ci | rv64c | sv |
384 |c.srli | crs1rdq cimmsh6 | cb·sh6 | rv64c | sv |
385 |c.srai | crs1rdq cimmsh6 | cb·sh6 | rv64c | sv |
386 |c.slli | crs1rd cimmsh6 | ci·sh6 | rv64c | sv |
387 |c.beqz | crs1q cimmb | cb | rv32c rv64c | VBR |
388 |c.bnez | crs1q cimmb | cb | rv32c rv64c | VBR |
389 |c.fldsp | cfrd cimmldsp | ci·ldsp+f | rv32c rv64c | VLU |
390 |c.lwsp | crd cimmlwsp | ci·lwsp | rv32c rv64c | VLU |
391 |c.flwsp | cfrd cimmlwsp | ci·lwsp+f | rv32c | VLU |
392 |c.ldsp | crd cimmldsp | ci·ldsp | rv64c | VLU |
393 |c.lqsp | crd cimmlqsp | ci·lqsp | rv128c | VLU |
394 |c.fsdsp | cfrs2 cimmsdsp | css·sdsp+f | rv32c rv64c | VSU |
395 |c.swsp | crs2 cimmswsp | css·swsp | rv32c rv64c | VSU |
396 |c.fswsp | cfrs2 cimmswsp | css·swsp+f | rv32c | VSU |
397 |c.sdsp | crs2 cimmsdsp | css·sdsp | rv64c | VSU |
398 |c.sqsp | crs2 cimmsqsp | css·sqsp | rv128c | VSU |
projects / libreriscv.git / blob