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8 \title{The Libre-SOC Hybrid
3D CPU
}
9 \author{Luke Kenneth Casson Leighton
}
16 \huge{The Libre-SOC Hybrid
3D CPU
}\\
18 \Large{Augmenting the OpenPOWER ISA
}\\
19 \Large{to provide
3D and Video instructions
}\\
20 \Large{(properly and officially)
}\\
22 \Large{[proposed for
] OpenPOWER Summit
2020}\\
24 \large{Sponsored by NLnet's PET Programme
}\\
31 \frame{\frametitle{Why another SoC?
}
36 \item Intel Management Engine, QA issues, Spectre
\vspace{15pt
}
37 \item Endless proprietary drivers \\
38 (affects product development cost)
\vspace{15pt
}
39 \item Opportunity to drastically simplify driver development\\
40 and engage in "long-tail" markets
\vspace{15pt
}
41 \item Because for
30 years I Always Wanted To Design A CPU
\vspace{10pt
}
46 \frame{\frametitle{Why OpenPOWER? (but first: Evaluation Criteria)
}
51 \item Good ecosystem essential\\
52 linux kernel, u-boot, compilers, OSes,\\
53 Reference Implementation(s)
\vspace{12pt
}
54 \item Supportive Foundation and Members\\
55 need to be able to submit ISA augmentations\\
56 (for proper peer review)
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}
57 \item No NDAs, full transparency must be acceptable\\
58 due to being funded under NLnet's PET Programme
\vspace{12pt
}
62 \frame{\frametitle{Why OpenPOWER?
}
66 \item RISC-V: closed secretive mailing lists, closed secretive\\
67 ISA Working Groups, no acceptance of transparency\\
68 requirements, not well-established enough
69 \item MIPS Open Initiative website was offline
70 \item ARM and x86 are proprietary (x86 too complex)
71 \item OpenRISC
1200 not enough adoption
72 \item Nyuzi GPU too specialist (not a general-purpose ISA)
73 \item MIAOW GPU is not a GPU (it's an AMD Vector Engine)
74 \item "rolling your own" out of the question (
20+ man-years)
75 \item OpenPOWER: established for decades, excellent Foundation,\\
76 Microwatt as Reference, approachable and friendly.
80 \frame{\frametitle{What goes into a typical SoC?
}
83 \item 15 to
20mm BGA package:
2.5 to
5 watt power consumption\\
84 heat sink normally not required (simplifies overall design)
86 \item Fully-integrated peripherals (not Northbridge/Southbridge)\\
87 USB, HDMI, RGB/TTL, SD/MMC, I2C, UART, SPI, GPIO etc. etc.
89 \item Built-in GPU (shared memory bus,
3rd party licensed)
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}
90 \item Build-in VPU (likewise)
\vspace{10pt
}
91 \item Target price between \$
2.50 and \$
30 depending on market\\
92 Radically different from IBM POWER9 Core (
200 Watt)
99 \frame{\frametitle{Simple SBC-style SoC
}
102 \includegraphics[width=
0.9\textwidth]{shakti_libre_soc.jpg
}
108 \frame{\frametitle{Where to start? (roadmap)
}
111 \item First thing: get a basic core working on an FPGA\\
112 (use Microwatt as a reference)
113 \item Next: create a low-cost test ASIC (
180nm).\\
114 (first OpenPOWER ASIC since IBM's POWER9,
10 years ago)
115 \item (in parallel): Develop Vector ISA with
3D and Video\\
116 extensions, under watchful eye of OpenPOWER Foundation
117 \item Implement Vector ISA in simulator, then HDL, then FPGA\\
118 and finally (only when ratified by OPF) into silicon
119 \item Sell chips, make \$\$\$.
123 \frame{\frametitle{What's different about Libre-SOC?
}
126 \item Hybrid - integrated. The CPU
\textit{is
} the GPU.\\
127 The GPU
\textit{is
} the CPU. The VPU
\textit{is
} the CPU.\\
128 \textit{There is No Separate VPU/GPU Pipeline
}
130 \item written in nmigen (a python-based HDL). Not VHDL\\
131 not Verilog (definitely not Chisel3/Scala)\\
132 This is an extremely important strategic decision.
134 \item Simple-V Vector Extension. See "SIMD Considered harmful".\\
135 SV effectively a "hardware for-loop" on standard scalar ISA\\
136 (conceptually similar to Zero-Overhead Loops in DSPs)
141 \frame{\frametitle{Hybrid Architecture: Augmented
6600}
144 \item CDC
6600 is a design from
1965. The
\textit{augmentations
} are not.\\
145 Help from Mitch Alsup includes "precise exceptions", \\
146 multi-issue and more. Academic literature on
6600 utterly misleading.
147 6600 Scoreboards completely underestimated.
148 \item Front-end Vector ISA, back-end "Predicated (masked) SIMD"\\
149 nmigen (python OO) strategically critical to achieving this.
150 \item Out-of-order combined with Simple-V allows scalar operations\\
151 at the developer end to be turned into SIMD at the back-end\\
152 \textit{without the developer needing to do SIMD
}
153 \item IEEE754 sin / cos / atan2, Texturisation opcodes, YUV2RGB\\
154 all automatically vectorised.
159 \frame{\frametitle{Summary
}
162 \item Actually about parallelism, not Vectors (or SIMD) per se\\
163 and NOT about adding new ALU/logic/functionality.
170 {\Huge The end
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}\\
171 Thank you
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}\\
172 Questions?
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}
177 \item Discussion: Libre-SOC-dev mailing list
178 \item Freenode IRC \#libre-soc
179 \item http://libre-soc.org/