simple_v_extension/simple_v_chennai_2018.tex

   1 \documentclass[slidestop]{beamer}
   2 \usepackage{beamerthemesplit}
   3 \usepackage{graphics}
   4 \usepackage{pstricks}
   5
   6 \title{Simple-V RISC-V Extension for Vectorisation and SIMD}
   7 \author{Luke Kenneth Casson Leighton}
   8
   9
  10 \begin{document}
  11
  12 \frame{
  13    \begin{center}
  14     \huge{Simple-V RISC-V Extension for Vectors and SIMD}\\
  15     \vspace{32pt}
  16     \Large{Flexible Vectorisation}\\
  17     \Large{(aka not so Simple-V?)}\\
  18     \vspace{24pt}
  19     \Large{Chennai 9th RISC-V Workshop}\\
  20     \vspace{24pt}
  21     \large{\today}
  22   \end{center}
  23 }
  24
  25 \frame{\frametitle{Why another Vector Extension?}
  26
  27  \begin{itemize}
  28    \item RVV very heavy-duty (excellent for supercomputing)\vspace{10pt}
  29    \item Simple-V abstracts parallelism (based on best of RVV)\vspace{10pt}
  30    \item Graded levels: hardware, hybrid or traps\vspace{10pt}
  31    \item Even Compressed instructions become vectorised\vspace{10pt}
  32   \end{itemize}
  33   What Simple-V is not:\vspace{10pt}
  34    \begin{itemize}
  35    \item A full supercomputer-level Vector Proposal\vspace{10pt}
  36    \item A replacement for RVV (designed to be augmented)\vspace{10pt}
  37   \end{itemize}
  38 }
  39
  40 \frame{\frametitle{Quick refresher on SIMD}
  41
  42  \begin{itemize}
  43    \item SIMD very easy to implement (and very seductive)\vspace{10pt}
  44    \item Parallelism is in the ALU\vspace{10pt}
  45    \item Zero-to-Negligeable impact for rest of core\vspace{10pt}
  46   \end{itemize}
  47   Where SIMD Goes Wrong:\vspace{10pt}
  48    \begin{itemize}
  49    \item See "Why SIMD considered harmful"\vspace{10pt}
  50    \item (Corner-cases alone are extremely complex)\vspace{10pt}
  51    \item O($N^{6}$) ISA opcode proliferation!\vspace{10pt}
  52   \end{itemize}
  53 }
  54
  55 \frame{\frametitle{Quick refresher on RVV}
  56
  57  \begin{itemize}
  58    \item Extremely powerful (extensible to 256 registers)\vspace{10pt}
  59    \item Supports polymorphism, several datatypes (inc. FP16)\vspace{10pt}
  60    \item Requires a separate Register File\vspace{10pt}
  61    \item Can be implemented as a separate pipeline\vspace{10pt}
  62   \end{itemize}
  63   However...\vspace{10pt}
  64    \begin{itemize}
  65    \item 98 percent opcode duplication with rest of RV (CLIP)\vspace{10pt}
  66    \item Extending RVV requires customisation\vspace{10pt}
  67   \end{itemize}
  68 }
  69
  70
  71 \frame{\frametitle{How is Parallelism abstracted?}
  72
  73  \begin{itemize}
  74    \item Almost all opcodes removed in favour of implicit "typing"\vspace{10pt}
  75    \item Primarily at the Instruction issue phase (except SIMD)\vspace{10pt}
  76    \item Standard (and future, and custom) opcodes now parallel\vspace{10pt}
  77   \end{itemize}
  78   Notes:\vspace{10pt}
  79    \begin{itemize}
  80    \item LOAD/STORE (inc. C.LD and C.ST, LDX: everything)\vspace{10pt}
  81    \item All ALU ops (soft / hybrid / full HW, on per-op basis)\vspace{10pt}
  82    \item All branches become predication targets (C.FNE added)\vspace{10pt}
  83   \end{itemize}
  84 }
  85
  86
  87 \frame{\frametitle{How are SIMD Instructions Vectorised?}
  88
  89  \begin{itemize}
  90    \item SIMD ALU(s) primarily unchanged\vspace{10pt}
  91    \item Predication is added to each SIMD element (NO ZEROING!)\vspace{10pt}
  92    \item End of Vector enables predication (NO ZEROING!)\vspace{10pt}
  93   \end{itemize}
  94   Considerations:\vspace{10pt}
  95    \begin{itemize}
  96    \item Many SIMD ALUs possible (parallel execution)\vspace{10pt}
  97    \item Very long SIMD ALUs could waste die area (short vectors)\vspace{10pt}
  98    \item Implementor free to choose (API remains the same)\vspace{10pt}
  99   \end{itemize}
 100 }
 101
 102 \frame{\frametitle{What's the deal / juice / score?}
 103
 104  \begin{itemize}
 105    \item Standard Register File(s) overloaded with "vector span"\vspace{10pt}
 106    \item Element width and type concepts remain same as RVV\vspace{10pt}
 107    \item CSRs are key-value tables (overlaps allowed)\vspace{10pt}
 108   \end{itemize}
 109   Key differences from RVV:\vspace{10pt}
 110    \begin{itemize}
 111    \item Predication in INT regs as a BIT field (max VL=XLEN)\vspace{10pt}
 112    \item Minimum VL must be Num Regs - 1 (all regs single LD/ST)\vspace{10pt}
 113    \item NO ZEROING: non-predicated elements are skipped\vspace{10pt}
 114   \end{itemize}
 115 }
 116
 117 \frame{\frametitle{Why are overlaps allowed in Regfiles?}
 118
 119  \begin{itemize}
 120    \item Same register(s) can have multiple "interpretations"\vspace{10pt}
 121    \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops\vspace{10pt}
 122    \item (32-bit GREV plus 4-wide 32-bit SIMD plus 32-bit GREVI)\vspace{10pt}
 123    \item 32-bit op followed by 16-bit op w/ 2x VL, 1/2 predicated\vspace{10pt}
 124   \end{itemize}
 125   Note:\vspace{10pt}
 126    \begin{itemize}
 127    \item xBitManip reduces O($N^{6}$) SIMD down to O($N^{3}$) \vspace{10pt}
 128    \item Hi-Performance: Macro-op fusion (more pipeline stages?)\vspace{10pt}
 129   \end{itemize}
 130 }
 131
 132
 133 \frame{\frametitle{Why no Zeroing (place zeros in non-predicated elements)?}
 134
 135  \begin{itemize}
 136    \item Zeroing is an implementation optimisation favouring OoO\vspace{10pt}
 137    \item Simple implementations may skip non-predicated operations\vspace{10pt}
 138    \item Simple implementations explicitly have to destroy data\vspace{10pt}
 139    \item Complex implementations may use reg-renames to save power\vspace{10pt}
 140   \end{itemize}
 141   Considerations:\vspace{10pt}
 142   \begin{itemize}
 143    \item Complex not really impacted, Simple impacted a LOT\vspace{10pt}
 144    \item Please don't use Vectors for "security" (use Sec-Ext)\vspace{10pt}
 145   \end{itemize}
 146 }
 147
 148
 149 \begin{frame}[fragile]
 150 \frametitle{ADD pseudocode (or trap, or actual hardware loop)}
 151
 152 \begin{semiverbatim}
 153 function op_add(rd, rs1, rs2, predr) # add not VADD!
 154   int i, id=0, irs1=0, irs2=0;
 155   for (i=0; i < MIN(VL, vectorlen[rd]); i++)
 156     if (ireg[predr] & 1<<i) # predication uses intregs
 157        ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
 158     if (reg_is_vectorised[rd]) \{ id += 1; \}
 159     if (reg_is_vectorised[rs1]) \{ irs1 += 1; \}
 160     if (reg_is_vectorised[rs2]) \{ irs2 += 1; \}
 161 \end{semiverbatim}
 162
 163   \begin{itemize}
 164    \item SIMD slightly more complex (case above is elwidth = default)
 165    \item Scalar-scalar and scalar-vector and vector-vector now all in one
 166    \item OoO may choose to push ADDs into instr. queue (v. busy!)
 167   \end{itemize}
 168 \end{frame}
 169
 170 \begin{frame}[fragile]
 171 \frametitle{Predication-Branch (or trap, or actual hardware loop)}
 172
 173 \begin{semiverbatim}
 174 s1 = vectorlen[src1] > 1;
 175 s2 = vectorlen[src2] > 1;
 176 for (int i = 0; i < VL; ++i)
 177    preg[rs3] |= 1 << cmp(s1 ? reg[src1+i] : reg[src1],
 178                          s2 ? reg[src2+i] : reg[src2]);
 179 \end{semiverbatim}
 180
 181   \begin{itemize}
 182    \item SIMD slightly more complex (case above is elwidth = default)
 183    \item If s1 and s2 both scalars, Standard branch occurs
 184    \item Predication stored in integer regfile as a bitfield
 185    \item Scalar-vector and vector-vector supported
 186   \end{itemize}
 187 \end{frame}
 188
 189 \begin{frame}[fragile]
 190 \frametitle{LD/LD.S/LD.X (or trap, or actual hardware loop)}
 191
 192 \begin{semiverbatim}
 193 if (unit-strided) stride = elsize;
 194 else stride = areg[as2]; // constant-strided
 195 for (int i = 0; i < VL; ++i)
 196   if (preg_enabled[rd] && ([!]preg[rd] & 1<<i))
 197     for (int j = 0; j < seglen+1; j++)
 198       if (vectorised[rs2]) offs = vreg[rs2][i]
 199       else offs = i*(seglen+1)*stride;
 200       vreg[rd+j][i] = mem[sreg[base] + offs + j*stride]
 201 \end{semiverbatim}
 202
 203   \begin{itemize}
 204    \item Again: SIMD slightly more complex
 205    \item rs2 vectorised taken to implicitly indicate LD.X
 206   \end{itemize}
 207 \end{frame}
 208
 209
 210 \frame{\frametitle{slide}
 211
 212  \begin{itemize}
 213    \item \vspace{10pt}
 214   \end{itemize}
 215   Considerations:\vspace{10pt}
 216   \begin{itemize}
 217    \item \vspace{10pt}
 218   \end{itemize}
 219 }
 220
 221
 222 \frame{\frametitle{Opcodes, compared to RVV}
 223
 224  \begin{itemize}
 225    \item All integer and FP opcodes all removed (no CLIP!)\vspace{10pt}
 226    \item VMPOP, VFIRST etc. all removed (use xBitManip)\vspace{10pt}
 227    \item VSLIDE, VEXTRACT, VINSERT removed (using regfile)\vspace{10pt}
 228    \item VSETVL, VGETVL, VSELECT stay\vspace{10pt}
 229    \item Issue: VCLIP is not in RV* (add with custom ext?)\vspace{10pt}
 230    \item Vector (or scalar-vector) use C.MV (MV is a pseudo-op)\vspace{10pt}
 231    \item VMERGE: twin predicated C.MVs (one inverted. macro-op'd)\vspace{10pt}
 232   \end{itemize}
 233 }
 234
 235
 236 \frame{\frametitle{Under consideration}
 237
 238  \begin{itemize}
 239    \item Can VSELECT be removed (or overloaded onto xBitManip)?\vspace{10pt}
 240    \item Can CLIP be done as a CSR (mode, like elwidth)\vspace{10pt}
 241    \item SIMD saturation (etc.) also set as a mode?\vspace{10pt}
 242   \end{itemize}
 243 }
 244
 245
 246 \frame{\frametitle{slide}
 247
 248  \begin{itemize}
 249    \item \vspace{10pt}
 250   \end{itemize}
 251   Considerations:\vspace{10pt}
 252   \begin{itemize}
 253    \item \vspace{10pt}
 254   \end{itemize}
 255 }
 256
 257
 258 \frame{\frametitle{slide}
 259
 260  \begin{itemize}
 261    \item \vspace{10pt}
 262   \end{itemize}
 263   Considerations:\vspace{10pt}
 264   \begin{itemize}
 265    \item \vspace{10pt}
 266   \end{itemize}
 267 }
 268
 269
 270 \frame{\frametitle{Including a plot}
 271  \begin{center}
 272 %  \includegraphics[height=2in]{dental.ps}\\
 273   {\bf \red Dental trajectories for 27 children:}
 274  \end{center}
 275 }
 276
 277 \frame{\frametitle{Creating .pdf slides in WinEdt}
 278
 279  \begin{itemize}
 280    \item LaTeX [Shift-Control-L]\vspace{10pt}
 281    \item dvi2pdf [click the button]\vspace{24pt}
 282   \end{itemize}
 283   To print 4 slides per page in acrobat click\vspace{10pt}
 284    \begin{itemize}
 285    \item File/print/properties\vspace{10pt}
 286    \item Change ``pages per sheet'' to 4\vspace{10pt}
 287   \end{itemize}
 288 }
 289
 290 \frame{
 291   \begin{center}
 292     {\Huge \red The end}
 293   \end{center}
 294 }
 295
 296
 297 \end{document}