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[libreriscv.git] / simple_v_extension / simple_v_chennai_2018.tex
1
2 \documentclass[slidestop]{beamer}
3 \usepackage{beamerthemesplit}
4 \usepackage{graphics}
5 \usepackage{pstricks}
6
7
8 \title{Simple-V RISC-V Extension for Vectorisation and SIMD}
9 \author{Luke Kenneth Casson Leighton}
10
11
12 \begin{document}
13
14 \frame{
15 \begin{center}
16 \huge{Simple-V RISC-V Extension for Vectors and SIMD}\\
17 \vspace{48pt}
18 \Large{Flexible Vectorisation}\\
19 \Large{Chennai 9th Workshop}\\
20 \vspace{24pt}
21 \large{\today}
22 \end{center}
23 }
24
25 \frame{\frametitle{Why another Vector Extension?}
26
27 \begin{itemize}
28 \item RVV very heavy-duty (excellent for supercomputing)\vspace{10pt}
29 \item Simple-V abstracts parallelism (based on best of RVV)\vspace{10pt}
30 \item Graded levels: hardware or software-emulation\vspace{10pt}
31 \item Even Compressed instructions become vectorised\vspace{10pt}
32 \end{itemize}
33 What Simple-V is not:\vspace{12pt}
34 \begin{itemize}
35 \item A full supercomputer-level Vector Proposal\vspace{12pt}
36 \item A replacement for RVV (designed to be augmented)\vspace{12pt}
37 \end{itemize}
38 }
39
40 \frame{\frametitle{Quick refresher on SIMD}
41
42 \begin{itemize}
43 \item SIMD very easy to implement\vspace{10pt}
44 \item Parallelism is in the ALU\vspace{10pt}
45 \item Negligeable impact for rest of core\vspace{10pt}
46 \end{itemize}
47 Where SIMD Goes Wrong:\vspace{12pt}
48 \begin{itemize}
49 \item See "Why SIMD considered harmful"\vspace{12pt}
50 \item (Corner-cases alone are extremely complex)\vspace{12pt}
51 \item O($N^{6}$) ISA proliferation\vspace{12pt}
52 \end{itemize}
53 }
54
55 \frame{\frametitle{Quick refresher on RVV}
56
57 \begin{itemize}
58 \item Extremely powerful (extensible to 256 registers)\vspace{10pt}
59 \item Supports polymorphism, several datatypes (inc. FP16)\vspace{10pt}
60 \item Requires a separate Register File\vspace{10pt}
61 \item Can be implemented as a separate pipeline\vspace{10pt}
62 \end{itemize}
63 However...\vspace{12pt}
64 \begin{itemize}
65 \item 98 percent opcode duplication with rest of RV (CLIP)\vspace{12pt}
66 \item Extending RVV requires customisation\vspace{12pt}
67 \end{itemize}
68 }
69
70
71 \frame{\frametitle{How is Parallelism abstracted?}
72
73 \begin{itemize}
74 \item Almost all opcodes removed in favour of implicit "typing"\vspace{10pt}
75 \item Primarily at the Instruction issue phase (except SIMD)\vspace{10pt}
76 \item Standard (and future, and custom) opcodes now parallel\vspace{10pt}
77 \end{itemize}
78 What Simple-V is not:\vspace{12pt}
79 \begin{itemize}
80 \item A full supercomputer-level Vector Proposal\vspace{12pt}
81 \item A replacement for RVV (designed to be augmented)\vspace{12pt}
82 \end{itemize}
83 }
84
85
86 \frame{\frametitle{How are SIMD Instructions Vectorised?}
87
88 \begin{itemize}
89 \item SIMD ALU(s) primarily unchanged\vspace{10pt}
90 \item Predication is added to each SIMD element\vspace{10pt}
91 \item End of Vector implicitly enables predication\vspace{10pt}
92 \end{itemize}
93 Considerations:\vspace{12pt}
94 \begin{itemize}
95 \item Many SIMD ALUs possible (parallel execution)\vspace{12pt}
96 \item Very long SIMD ALUs could waste die area (short vectors)\vspace{12pt}
97 \item Implementor free to choose (API remains the same)\vspace{12pt}
98 \end{itemize}
99 }
100
101 \frame{\frametitle{Including a plot}
102 \begin{center}
103 % \includegraphics[height=2in]{dental.ps}\\
104 {\bf \red Dental trajectories for 27 children:}
105 \end{center}
106 }
107
108 \frame{\frametitle{Creating .pdf slides in WinEdt}
109
110 \begin{itemize}
111 \item LaTeX [Shift-Control-L]\vspace{12pt}
112 \item dvi2pdf [click the button]\vspace{24pt}
113 \end{itemize}
114 To print 4 slides per page in acrobat click\vspace{12pt}
115 \begin{itemize}
116 \item File/print/properties\vspace{12pt}
117 \item Change ``pages per sheet'' to 4\vspace{12pt}
118 \end{itemize}
119 }
120
121 \frame{
122 \begin{center}
123 {\Huge \red The end}
124 \end{center}
125 }
126
127
128 \end{document}