1 \documentclass[slidestop
]{beamer
}
2 \usepackage{beamerthemesplit
}
6 \title{Simple-V RISC-V Extension for Vectorisation and SIMD
}
7 \author{Luke Kenneth Casson Leighton
}
14 \huge{Simple-V RISC-V Extension for Vectors and SIMD
}\\
16 \Large{Flexible Vectorisation
}\\
17 \Large{(aka not so Simple-V?)
}\\
19 \Large{[proposed for
] Chennai
9th RISC-V Workshop
}\\
26 \frame{\frametitle{Credits and Acknowledgements
}
29 \item The Designers of RISC-V
\vspace{15pt
}
30 \item The RVV Working Group and contributors
\vspace{15pt
}
31 \item Allen Baum, Jacob Bachmeyer, Xan Phung, Chuanhua Chang,\\
32 Guy Lemurieux, Jonathan Neuschafer, Roger Brussee,
33 and others
\vspace{15pt
}
34 \item ISA-Dev Group Members
\vspace{10pt
}
39 \frame{\frametitle{Quick refresher on SIMD
}
42 \item SIMD very easy to implement (and very seductive)
\vspace{10pt
}
43 \item Parallelism is in the ALU
\vspace{10pt
}
44 \item Zero-to-Negligeable impact for rest of core
\vspace{10pt
}
46 Where SIMD Goes Wrong:
\vspace{10pt
}
48 \item See "SIMD instructions considered harmful"
49 https://www.sigarch.org/simd-instructions-considered-harmful
50 \item Corner-cases alone are extremely complex.\\
51 Hardware is easy, but software is hell.
52 \item O($N^
{6}$) ISA opcode proliferation!\\
53 opcode, elwidth, veclen, src1-src2-dest hi/lo
57 \frame{\frametitle{Quick refresher on RVV
}
60 \item Extremely powerful (extensible to
256 registers)
\vspace{10pt
}
61 \item Supports polymorphism, several datatypes (inc. FP16)
\vspace{10pt
}
62 \item Requires a separate Register File (
32 w/ext to
256)
\vspace{10pt
}
63 \item Implemented as a separate pipeline (no impact on scalar)
\vspace{10pt
}
65 However...
\vspace{10pt
}
67 \item 98 percent opcode duplication with rest of RV (CLIP)
68 \item Extending RVV requires customisation not just of h/w:\\
69 gcc and s/w also need customisation (and maintenance)
74 \frame{\frametitle{The Simon Sinek lowdown (Why, How, What)
}
78 Implementors need flexibility in vectorisation to optimise for
79 area or performance depending on the scope:
80 embedded DSP, Mobile GPU's, Server CPU's and more.
\vspace{4pt
}\\
81 Compilers also need flexibility in vectorisation to optimise for cost
82 of pipeline setup, amount of state to context switch
83 and software portability
\vspace{4pt
}
85 By implicitly marking INT/FP regs as "Vectorised",\\
86 SV expresses how existing instructions should act
87 on
[contiguous
] blocks of registers, in parallel.
\vspace{4pt
}
89 Simple-V is an "API" that implicitly extends
90 existing (scalar) instructions with explicit parallelisation.
95 \frame{\frametitle{What's the value of SV? Why adopt it even in non-V?
}
98 \item memcpy becomes much smaller (higher bang-per-buck)
\vspace{10pt
}
99 \item context-switch (LOAD/STORE multiple):
1-
2 instructions
\vspace{10pt
}
100 \item Compressed instrs further reduces I-cache (etc.)
\vspace{10pt
}
101 \item greatly-reduced I-cache load (and less reads)
\vspace{10pt
}
105 \item It's not just about Vectors: it's about instruction effectiveness
106 \item Anything implementor is not interested in HW-optimising,\\
107 let it fall through to exceptions (implement as a trap).
112 \frame{\frametitle{How does Simple-V relate to RVV?
}
115 \item RVV very heavy-duty (excellent for supercomputing)
\vspace{10pt
}
116 \item Simple-V abstracts parallelism (based on best of RVV)
\vspace{10pt
}
117 \item Graded levels: hardware, hybrid or traps (fit impl. need)
\vspace{10pt
}
118 \item Even Compressed instructions become vectorised
\vspace{10pt
}
120 What Simple-V is not:
\vspace{10pt
}
122 \item A full supercomputer-level Vector Proposal
123 \item A replacement for RVV (SV is designed to be over-ridden\\
124 by - or augmented to become, or just be replaced by - RVV)
129 \frame{\frametitle{How is Parallelism abstracted in Simple-V?
}
132 \item Register "typing" turns any op into an implicit Vector op
\vspace{10pt
}
133 \item Primarily at the Instruction issue phase (except SIMD)\\
134 Note: it's ok to pass predication through to ALU (like SIMD)
135 \item Standard (and future, and custom) opcodes now parallel
\vspace{10pt
}
139 \item All LOAD/STORE (inc. Compressed, Int/FP versions)
140 \item All ALU ops (soft / hybrid / full HW, on per-op basis)
141 \item All branches become predication targets (C.FNE added)
142 \item C.MV of particular interest (s/v, v/v, v/s)
147 \frame{\frametitle{Implementation Options
}
150 \item Absolute minimum: Exceptions (if CSRs indicate "V", trap)
151 \item Hardware loop, single-instruction issue\\
152 (Do / Don't send through predication to ALU)
153 \item Hardware loop, parallel (multi-instruction) issue\\
154 (Do / Don't send through predication to ALU)
155 \item Hardware loop, full parallel ALU (not recommended)
159 \item 4 (or more?) options above may be deployed on per-op basis
160 \item SIMD always sends predication bits through to ALU
161 \item Minimum MVL MUST be sufficient to cover regfile LD/ST
162 \item Instr. FIFO may repeatedly split off N scalar ops at a time
165 % Instr. FIFO may need its own slide. Basically, the vectorised op
166 % gets pushed into the FIFO, where it is then "processed". Processing
167 % will remove the first set of ops from its vector numbering (taking
168 % predication into account) and shoving them **BACK** into the FIFO,
169 % but MODIFYING the remaining "vectorised" op, subtracting the now
170 % scalar ops from it.
172 \frame{\frametitle{How are SIMD Instructions Vectorised?
}
175 \item SIMD ALU(s) primarily unchanged
\vspace{10pt
}
176 \item Predication is added to each SIMD element (NO ZEROING!)
\vspace{10pt
}
177 \item End of Vector enables predication (NO ZEROING!)
\vspace{10pt
}
179 Considerations:
\vspace{10pt
}
181 \item Many SIMD ALUs possible (parallel execution)
\vspace{10pt
}
182 \item Very long SIMD ALUs could waste die area (short vectors)
\vspace{10pt
}
183 \item Implementor free to choose (API remains the same)
\vspace{10pt
}
186 % With multiple SIMD ALUs at for example 32-bit wide they can be used
187 % to either issue 64-bit or 128-bit or 256-bit wide SIMD operations
188 % or they can be used to cover several operations on totally different
189 % vectors / registers.
191 \frame{\frametitle{What's the deal / juice / score?
}
194 \item Standard Register File(s) overloaded with CSR "vector span"\\
195 (see pseudocode slides for examples)
196 \item Element width and type concepts remain same as RVV\\
197 (CSRs are used to "interpret" elements in registers)
198 \item CSRs are key-value tables (overlaps allowed)
\vspace{10pt
}
200 Key differences from RVV:
\vspace{10pt
}
202 \item Predication in INT regs as a BIT field (max VL=XLEN)
203 \item Minimum VL must be Num Regs -
1 (all regs single LD/ST)
204 \item SV may condense sparse Vecs: RVV lets ALU do predication
205 \item NO ZEROING: non-predicated elements are skipped
210 \begin{frame
}[fragile
]
211 \frametitle{ADD pseudocode (or trap, or actual hardware loop)
}
214 function op_add(rd, rs1, rs2, predr) # add not VADD!
215 Â int i, id=
0, irs1=
0, irs2=
0;
216 Â for (i =
0; i < VL; i++)
217 Â if (ireg
[predr
] &
1<<i) # predication uses intregs
218 Â Â ireg
[rd+id
] <= ireg
[rs1+irs1
] + ireg
[rs2+irs2
];
219 if (reg_is_vectorised
[rd
])Â \
{ id +=
1; \
}
220 if (reg_is_vectorised
[rs1
])Â \
{ irs1 +=
1; \
}
221 if (reg_is_vectorised
[rs2
])Â \
{ irs2 +=
1; \
}
225 \item SIMD slightly more complex (case above is elwidth = default)
226 \item Scalar-scalar and scalar-vector and vector-vector now all in one
227 \item OoO may choose to push ADDs into instr. queue (v. busy!)
231 % yes it really *is* ADD not VADD. that's the entire point of
232 % this proposal, that *standard* operations are overloaded to
233 % become vectorised-on-demand
236 \begin{frame
}[fragile
]
237 \frametitle{Predication-Branch (or trap, or actual hardware loop)
}
240 s1 = reg_is_vectorised(src1);
241 s2 = reg_is_vectorised(src2);
242 if (!s2 && !s1) goto branch;
243 for (int i =
0; i < VL; ++i)
244 if cmp(s1 ? reg
[src1+i
] : reg
[src1
],
245 s2 ? reg
[src2+i
] : reg
[src2
])
250 \item SIMD slightly more complex (case above is elwidth = default)
251 \item If s1 and s2 both scalars, Standard branch occurs
252 \item Predication stored in integer regfile as a bitfield
253 \item Scalar-vector and vector-vector supported
257 \begin{frame
}[fragile
]
258 \frametitle{VLD/VLD.S/VLD.X (or trap, or actual hardware loop)
}
261 if (unit-strided) stride = elsize;
262 else stride = areg
[as2
]; // constant-strided
263 for (int i =
0; i < VL; ++i)
264 if (preg_enabled
[rd
] && (
[!
]preg
[rd
] &
1<<i))
265 for (int j =
0; j < seglen+
1; j++)
266 if (reg_is_vectorised
[rs2
]) offs = vreg
[rs2
][i
]
267 else offs = i*(seglen+
1)*stride;
268 vreg
[rd+j
][i
] = mem
[sreg
[base
] + offs + j*stride
]
272 \item Again: elwidth != default slightly more complex
273 \item rs2 vectorised taken to implicitly indicate VLD.X
278 \frame{\frametitle{Why are overlaps allowed in Regfiles?
}
281 \item Same register(s) can have multiple "interpretations"
\vspace{6pt
}
282 \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops
\vspace{6pt
}
283 \item (
32-bit GREV plus
4x8-bit SIMD plus
32-bit GREV)
\vspace{6pt
}
284 \item RGB
565 (video): BEXTW plus
4x8-bit SIMD plus BDEPW
\vspace{6pt
}
285 \item Same register(s) can be offset (no need for VSLIDE)
\vspace{6pt
}
289 \item xBitManip reduces O($N^
{6}$) SIMD down to O($N^
{3}$)
290 \item Hi-Performance: Macro-op fusion (more pipeline stages?)
295 \frame{\frametitle{Why no Zeroing (place zeros in non-predicated elements)?
}
298 \item Zeroing is an implementation optimisation favouring OoO
\vspace{8pt
}
299 \item Simple implementations may skip non-predicated operations
\vspace{8pt
}
300 \item Simple implementations explicitly have to destroy data
\vspace{8pt
}
301 \item Complex implementations may use reg-renames to save power\\
302 Zeroing on predication chains makes optimisation harder
304 Considerations:
\vspace{10pt
}
306 \item Complex not really impacted, Simple impacted a LOT
307 \item Overlapping "Vectors" may issue overlapping ops
308 \item Please don't use Vectors for "security" (use Sec-Ext)
311 % with overlapping "vectors" - bearing in mind that "vectors" are
312 % just a remap onto the standard register file, if the top bits of
313 % predication are zero, and there happens to be a second vector
314 % that uses some of the same register file that happens to be
315 % predicated out, the second vector op may be issued *at the same time*
316 % if there are available parallel ALUs to do so.
319 \frame{\frametitle{Predication key-value CSR store
}
322 \item key is int regfile number or FP regfile number (
1 bit)
\vspace{6pt
}
323 \item register to be predicated if referred to (
5 bits, key)
\vspace{6pt
}
324 \item register to store actual predication in (
5 bits, value)
\vspace{6pt
}
325 \item predication is inverted (
1 bit)
\vspace{6pt
}
326 \item non-predicated elements are to be zero'd (
1 bit)
\vspace{6pt
}
330 \item Table should be expanded out for high-speed implementations
331 \item Multiple "keys" (and values) theoretically permitted
332 \item RVV rules about deleting higher-indexed CSRs followed
337 \frame{\frametitle{Register key-value CSR store
}
340 \item key is int regfile number or FP regfile number (
1 bit)
\vspace{6pt
}
341 \item treated as vector if referred to in op (
5 bits, key)
\vspace{6pt
}
342 \item starting register to actually be used (
5 bits, value)
\vspace{6pt
}
343 \item element bitwidth: default/
8/
16/
32/
64/rsvd (
3 bits)
\vspace{6pt
}
344 \item element type: still under consideration
\vspace{6pt
}
348 \item Same notes apply (previous slide) as for predication CSR table
349 \item Level of indirection has implications for pipeline latency
354 \frame{\frametitle{C.MV extremely flexible!
}
357 \item scalar-to-vector (w/no pred): VSPLAT
358 \item scalar-to-vector (w/dest-pred): Sparse VSPLAT
359 \item scalar-to-vector (w/single dest-pred): VINSERT
360 \item vector-to-scalar (w/src-pred): VEXTRACT
361 \item vector-to-vector (w/no pred): Vector Copy
362 \item vector-to-vector (w/src xor dest pred): Sparse Vector Copy
363 \item vector-to-vector (w/src and dest pred): Vector Gather/Scatter
368 \item Really powerful!
369 \item Any other options?
374 \frame{\frametitle{Opcodes, compared to RVV
}
377 \item All integer and FP opcodes all removed (no CLIP!)
\vspace{8pt
}
378 \item VMPOP, VFIRST etc. all removed (use xBitManip)
\vspace{8pt
}
379 \item VSLIDE removed (use regfile overlaps)
\vspace{8pt
}
380 \item C.MV covers VEXTRACT VINSERT and VSPLAT (and more)
\vspace{8pt
}
381 \item VSETVL, VGETVL, VSELECT stay
\vspace{8pt
}
382 \item Issue: VCLIP is not in RV* (add with custom ext?)
\vspace{8pt
}
383 \item Vector (or scalar-vector) use C.MV (MV is a pseudo-op)
\vspace{8pt
}
384 \item VMERGE: twin predicated C.MVs (one inverted. macro-op'd)
\vspace{8pt
}
389 \frame{\frametitle{Under consideration
}
392 \item Is C.FNE actually needed? Should it be added if it is?
393 \item Element type implies polymorphism. Should it be in SV?
394 \item Should use of registers be allowed to "wrap" (x30 x31 x1 x2)?
395 \item Is detection of all-scalar ops ok (without slowing pipeline)?
396 \item Can VSELECT be removed? (it's really complex)
397 \item Can CLIP be done as a CSR (mode, like elwidth)
398 \item SIMD saturation (etc.) also set as a mode?
399 \item C.MV src predication no different from dest predication\\
400 What to do? Make one have different meaning?
401 \item 8/
16-bit ops is it worthwhile adding a "start offset"? \\
402 (a bit like misaligned addressing... for registers)\\
403 or just use predication to skip start?
408 \frame{\frametitle{Is this OK (low latency)? Detect scalar-ops (only)
}
410 \includegraphics[height=
2.5in
]{scalardetect.png
}\\
411 {\bf \red Detect when all registers are scalar for a given op
}
416 \frame{\frametitle{TODO (break into separate slides)
}
419 \item Then explain why this proposal is a good way to \\
420 abstract parallelism\\
421 (hopefully also explaining how \\
422 a good compiler can make clever use of this increase parallelism\\
423 Then explain how this can be implemented (at instruction\\
424 issue time???) with\\
425 implementation options, and what these "cost".\\
426 Finally give examples that show simple usage that compares\\
435 \frame{\frametitle{Summary
}
438 \item Designed for flexibility (graded levels of complexity)
\vspace{6pt
}
439 \item Huge range of implementor freedom
\vspace{6pt
}
440 \item Fits RISC-V ethos: achieve more with less
\vspace{6pt
}
441 \item Reduces SIMD ISA proliferation by
3-
4 orders of magnitude \\
442 (without SIMD downsides or sacrificing speed trade-off)
\vspace{6pt
}
443 \item Covers
98\% of RVV, allows RVV to fit "on top"
\vspace{6pt
}
444 \item Not designed for supercomputing (that's RVV), designed for
445 in between: DSPs, RV32E, Embedded
3D GPUs etc.
\vspace{6pt
}
446 \item Not specifically designed for Vectorisation: designed to\\
447 reduce code size (increase efficiency, just
448 like Compressed)
\vspace{6pt
}
453 \frame{\frametitle{slide
}
458 Considerations:
\vspace{10pt
}
467 {\Huge \red The end
\vspace{20pt
}\\