simple_v_extension/simple_v_chennai_2018.tex

   1 \documentclass[slidestop]{beamer}
   2 \usepackage{beamerthemesplit}
   3 \usepackage{graphics}
   4 \usepackage{pstricks}
   5
   6 \title{Simple-V RISC-V Extension for Vectorisation and SIMD}
   7 \author{Luke Kenneth Casson Leighton}
   8
   9
  10 \begin{document}
  11
  12 \frame{
  13    \begin{center}
  14     \huge{Simple-V RISC-V Extension for Vectors and SIMD}\\
  15     \vspace{32pt}
  16     \Large{Flexible Vectorisation}\\
  17     \Large{(aka not so Simple-V?)}\\
  18     \vspace{24pt}
  19     \Large{Chennai 9th RISC-V Workshop}\\
  20     \vspace{24pt}
  21     \large{\today}
  22   \end{center}
  23 }
  24
  25 \frame{\frametitle{Why another Vector Extension?}
  26
  27  \begin{itemize}
  28    \item RVV very heavy-duty (excellent for supercomputing)\vspace{10pt}
  29    \item Simple-V abstracts parallelism (based on best of RVV)\vspace{10pt}
  30    \item Graded levels: hardware, hybrid or traps\vspace{10pt}
  31    \item Even Compressed instructions become vectorised\vspace{10pt}
  32   \end{itemize}
  33   What Simple-V is not:\vspace{10pt}
  34    \begin{itemize}
  35    \item A full supercomputer-level Vector Proposal\vspace{10pt}
  36    \item A replacement for RVV (designed to be augmented)\vspace{10pt}
  37   \end{itemize}
  38 }
  39
  40 \frame{\frametitle{Quick refresher on SIMD}
  41
  42  \begin{itemize}
  43    \item SIMD very easy to implement (and very seductive)\vspace{10pt}
  44    \item Parallelism is in the ALU\vspace{10pt}
  45    \item Zero-to-Negligeable impact for rest of core\vspace{10pt}
  46   \end{itemize}
  47   Where SIMD Goes Wrong:\vspace{10pt}
  48    \begin{itemize}
  49    \item See "Why SIMD considered harmful"\vspace{10pt}
  50    \item (Corner-cases alone are extremely complex)\vspace{10pt}
  51    \item O($N^{6}$) ISA opcode proliferation!\vspace{10pt}
  52   \end{itemize}
  53 }
  54
  55 \frame{\frametitle{Quick refresher on RVV}
  56
  57  \begin{itemize}
  58    \item Extremely powerful (extensible to 256 registers)\vspace{10pt}
  59    \item Supports polymorphism, several datatypes (inc. FP16)\vspace{10pt}
  60    \item Requires a separate Register File\vspace{10pt}
  61    \item Can be implemented as a separate pipeline\vspace{10pt}
  62   \end{itemize}
  63   However...\vspace{10pt}
  64    \begin{itemize}
  65    \item 98 percent opcode duplication with rest of RV (CLIP)\vspace{10pt}
  66    \item Extending RVV requires customisation\vspace{10pt}
  67   \end{itemize}
  68 }
  69
  70
  71 \frame{\frametitle{How is Parallelism abstracted?}
  72
  73  \begin{itemize}
  74    \item Almost all opcodes removed in favour of implicit "typing"\vspace{10pt}
  75    \item Primarily at the Instruction issue phase (except SIMD)\vspace{10pt}
  76    \item Standard (and future, and custom) opcodes now parallel\vspace{10pt}
  77   \end{itemize}
  78   Notes:\vspace{10pt}
  79    \begin{itemize}
  80    \item LOAD/STORE (inc. C.LD and C.ST, LDX: everything)\vspace{10pt}
  81    \item All ALU ops (soft / hybrid / full HW, on per-op basis)\vspace{10pt}
  82    \item All branches become predication targets (C.FNE added)\vspace{10pt}
  83   \end{itemize}
  84 }
  85
  86
  87 \frame{\frametitle{Implementation Options}
  88
  89  \begin{itemize}
  90    \item Absolute minimum: Exceptions (CSRs needed)\vspace{10pt}
  91    \item Hardware loop, single-instruction issue\vspace{10pt}
  92    \item Hardware loop, parallel (multi-instruction) issue\vspace{10pt}
  93    \item Hardware loop, full parallel ALU (not recommended)\vspace{10pt}
  94   \end{itemize}
  95   Considerations:\vspace{10pt}
  96   \begin{itemize}
  97    \item OoO may split off 4+ single-instructions at a time\vspace{10pt}
  98    \item Minimum VL MUST be sufficient to cover regfile LD/ST\vspace{10pt}
  99   \end{itemize}
 100 }
 101
 102
 103 \frame{\frametitle{How are SIMD Instructions Vectorised?}
 104
 105  \begin{itemize}
 106    \item SIMD ALU(s) primarily unchanged\vspace{10pt}
 107    \item Predication is added to each SIMD element (NO ZEROING!)\vspace{10pt}
 108    \item End of Vector enables predication (NO ZEROING!)\vspace{10pt}
 109   \end{itemize}
 110   Considerations:\vspace{10pt}
 111    \begin{itemize}
 112    \item Many SIMD ALUs possible (parallel execution)\vspace{10pt}
 113    \item Very long SIMD ALUs could waste die area (short vectors)\vspace{10pt}
 114    \item Implementor free to choose (API remains the same)\vspace{10pt}
 115   \end{itemize}
 116 }
 117
 118
 119 \frame{\frametitle{What's the deal / juice / score?}
 120
 121  \begin{itemize}
 122    \item Standard Register File(s) overloaded with "vector span"\vspace{10pt}
 123    \item Element width and type concepts remain same as RVV\vspace{10pt}
 124    \item CSRs are key-value tables (overlaps allowed)\vspace{10pt}
 125   \end{itemize}
 126   Key differences from RVV:\vspace{10pt}
 127    \begin{itemize}
 128    \item Predication in INT regs as a BIT field (max VL=XLEN)\vspace{10pt}
 129    \item Minimum VL must be Num Regs - 1 (all regs single LD/ST)\vspace{10pt}
 130    \item NO ZEROING: non-predicated elements are skipped\vspace{10pt}
 131   \end{itemize}
 132 }
 133
 134 \frame{\frametitle{Why are overlaps allowed in Regfiles?}
 135
 136  \begin{itemize}
 137    \item Same register(s) can have multiple "interpretations"\vspace{10pt}
 138    \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops\vspace{10pt}
 139    \item (32-bit GREV plus 4-wide 32-bit SIMD plus 32-bit GREVI)\vspace{10pt}
 140    \item 32-bit op followed by 16-bit op w/ 2x VL, 1/2 predicated\vspace{10pt}
 141   \end{itemize}
 142   Note:\vspace{10pt}
 143    \begin{itemize}
 144    \item xBitManip reduces O($N^{6}$) SIMD down to O($N^{3}$) \vspace{10pt}
 145    \item Hi-Performance: Macro-op fusion (more pipeline stages?)\vspace{10pt}
 146   \end{itemize}
 147 }
 148
 149
 150 \frame{\frametitle{Why no Zeroing (place zeros in non-predicated elements)?}
 151
 152  \begin{itemize}
 153    \item Zeroing is an implementation optimisation favouring OoO\vspace{10pt}
 154    \item Simple implementations may skip non-predicated operations\vspace{10pt}
 155    \item Simple implementations explicitly have to destroy data\vspace{10pt}
 156    \item Complex implementations may use reg-renames to save power\vspace{10pt}
 157   \end{itemize}
 158   Considerations:\vspace{10pt}
 159   \begin{itemize}
 160    \item Complex not really impacted, Simple impacted a LOT\vspace{10pt}
 161    \item Please don't use Vectors for "security" (use Sec-Ext)\vspace{10pt}
 162   \end{itemize}
 163 }
 164
 165
 166 \begin{frame}[fragile]
 167 \frametitle{ADD pseudocode (or trap, or actual hardware loop)}
 168
 169 \begin{semiverbatim}
 170 function op_add(rd, rs1, rs2, predr) # add not VADD!
 171   int i, id=0, irs1=0, irs2=0;
 172   for (i=0; i < MIN(VL, vectorlen[rd]); i++)
 173     if (ireg[predr] & 1<<i) # predication uses intregs
 174        ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
 175     if (reg_is_vectorised[rd]) \{ id += 1; \}
 176     if (reg_is_vectorised[rs1]) \{ irs1 += 1; \}
 177     if (reg_is_vectorised[rs2]) \{ irs2 += 1; \}
 178 \end{semiverbatim}
 179
 180   \begin{itemize}
 181    \item SIMD slightly more complex (case above is elwidth = default)
 182    \item Scalar-scalar and scalar-vector and vector-vector now all in one
 183    \item OoO may choose to push ADDs into instr. queue (v. busy!)
 184   \end{itemize}
 185 \end{frame}
 186
 187 \begin{frame}[fragile]
 188 \frametitle{Predication-Branch (or trap, or actual hardware loop)}
 189
 190 \begin{semiverbatim}
 191 s1 = vectorlen[src1] > 1;
 192 s2 = vectorlen[src2] > 1;
 193 for (int i = 0; i < VL; ++i)
 194    preg[rs3] |= 1 << cmp(s1 ? reg[src1+i] : reg[src1],
 195                          s2 ? reg[src2+i] : reg[src2]);
 196 \end{semiverbatim}
 197
 198   \begin{itemize}
 199    \item SIMD slightly more complex (case above is elwidth = default)
 200    \item If s1 and s2 both scalars, Standard branch occurs
 201    \item Predication stored in integer regfile as a bitfield
 202    \item Scalar-vector and vector-vector supported
 203   \end{itemize}
 204 \end{frame}
 205
 206 \begin{frame}[fragile]
 207 \frametitle{LD/LD.S/LD.X (or trap, or actual hardware loop)}
 208
 209 \begin{semiverbatim}
 210 if (unit-strided) stride = elsize;
 211 else stride = areg[as2]; // constant-strided
 212 for (int i = 0; i < VL; ++i)
 213   if (preg_enabled[rd] && ([!]preg[rd] & 1<<i))
 214     for (int j = 0; j < seglen+1; j++)
 215       if (vectorised[rs2]) offs = vreg[rs2][i]
 216       else offs = i*(seglen+1)*stride;
 217       vreg[rd+j][i] = mem[sreg[base] + offs + j*stride]
 218 \end{semiverbatim}
 219
 220   \begin{itemize}
 221    \item Again: SIMD slightly more complex
 222    \item rs2 vectorised taken to implicitly indicate LD.X
 223   \end{itemize}
 224 \end{frame}
 225
 226
 227 \frame{\frametitle{Opcodes, compared to RVV}
 228
 229  \begin{itemize}
 230    \item All integer and FP opcodes all removed (no CLIP!)\vspace{10pt}
 231    \item VMPOP, VFIRST etc. all removed (use xBitManip)\vspace{10pt}
 232    \item VSLIDE, VEXTRACT, VINSERT removed (using regfile)\vspace{10pt}
 233    \item VSETVL, VGETVL, VSELECT stay\vspace{10pt}
 234    \item Issue: VCLIP is not in RV* (add with custom ext?)\vspace{10pt}
 235    \item Vector (or scalar-vector) use C.MV (MV is a pseudo-op)\vspace{10pt}
 236    \item VMERGE: twin predicated C.MVs (one inverted. macro-op'd)\vspace{10pt}
 237   \end{itemize}
 238 }
 239
 240
 241 \frame{\frametitle{Under consideration}
 242
 243  \begin{itemize}
 244    \item Can VSELECT be removed (or overloaded onto xBitManip)?\vspace{10pt}
 245    \item Can CLIP be done as a CSR (mode, like elwidth)\vspace{10pt}
 246    \item SIMD saturation (etc.) also set as a mode?\vspace{10pt}
 247   \end{itemize}
 248 }
 249
 250
 251 \frame{\frametitle{slide}
 252
 253  \begin{itemize}
 254    \item \vspace{10pt}
 255   \end{itemize}
 256   Considerations:\vspace{10pt}
 257   \begin{itemize}
 258    \item \vspace{10pt}
 259   \end{itemize}
 260 }
 261
 262
 263 \frame{\frametitle{slide}
 264
 265  \begin{itemize}
 266    \item \vspace{10pt}
 267   \end{itemize}
 268   Considerations:\vspace{10pt}
 269   \begin{itemize}
 270    \item \vspace{10pt}
 271   \end{itemize}
 272 }
 273
 274
 275 \frame{\frametitle{Including a plot}
 276  \begin{center}
 277 %  \includegraphics[height=2in]{dental.ps}\\
 278   {\bf \red Dental trajectories for 27 children:}
 279  \end{center}
 280 }
 281
 282 \frame{\frametitle{Creating .pdf slides in WinEdt}
 283
 284  \begin{itemize}
 285    \item LaTeX [Shift-Control-L]\vspace{10pt}
 286    \item dvi2pdf [click the button]\vspace{24pt}
 287   \end{itemize}
 288   To print 4 slides per page in acrobat click\vspace{10pt}
 289    \begin{itemize}
 290    \item File/print/properties\vspace{10pt}
 291    \item Change ``pages per sheet'' to 4\vspace{10pt}
 292   \end{itemize}
 293 }
 294
 295 \frame{
 296   \begin{center}
 297     {\Huge \red The end}
 298   \end{center}
 299 }
 300
 301
 302 \end{document}