1 \documentclass[slidestop
]{beamer
}
2 \usepackage{beamerthemesplit
}
6 \title{Simple-V RISC-V Extension for Vectorisation and SIMD
}
7 \author{Luke Kenneth Casson Leighton
}
14 \huge{Simple-V RISC-V Extension for Vectors and SIMD
}\\
16 \Large{Flexible Vectorisation
}\\
17 \Large{(aka not so Simple-V?)
}\\
18 \Large{(aka How to Parallelise the RISC-V ISA)
}\\
20 \Large{[proposed for
] Chennai
9th RISC-V Workshop
}\\
27 \frame{\frametitle{Credits and Acknowledgements
}
30 \item The Designers of RISC-V
\vspace{15pt
}
31 \item The RVV Working Group and contributors
\vspace{15pt
}
32 \item Allen Baum, Jacob Bachmeyer, Xan Phung, Chuanhua Chang,\\
33 Guy Lemurieux, Jonathan Neuschafer, Roger Brussee,
34 and others
\vspace{15pt
}
35 \item ISA-Dev Group Members
\vspace{10pt
}
40 \frame{\frametitle{Quick refresher on SIMD
}
43 \item SIMD very easy to implement (and very seductive)
\vspace{8pt
}
44 \item Parallelism is in the ALU
\vspace{8pt
}
45 \item Zero-to-Negligeable impact for rest of core
\vspace{8pt
}
47 Where SIMD Goes Wrong:
\vspace{10pt
}
49 \item See "SIMD instructions considered harmful"
50 https://sigarch.org/simd-instructions-considered-harmful
51 \item Setup and corner-cases alone are extremely complex.\\
52 Hardware is easy, but software is hell.
53 \item O($N^
{6}$) ISA opcode proliferation!\\
54 opcode, elwidth, veclen, src1-src2-dest hi/lo
58 \frame{\frametitle{Quick refresher on RVV
}
61 \item Extremely powerful (extensible to
256 registers)
\vspace{10pt
}
62 \item Supports polymorphism, several datatypes (inc. FP16)
\vspace{10pt
}
63 \item Requires a separate Register File (
32 w/ext to
256)
\vspace{10pt
}
64 \item Implemented as a separate pipeline (no impact on scalar)
\vspace{10pt
}
66 However...
\vspace{10pt
}
68 \item 98 percent opcode duplication with rest of RV (CLIP)
69 \item Extending RVV requires customisation not just of h/w:\\
70 gcc, binutils also need customisation (and maintenance)
75 \frame{\frametitle{The Simon Sinek lowdown (Why, How, What)
}
79 Implementors need flexibility in vectorisation to optimise for
80 area or performance depending on the scope:
81 embedded DSP, Mobile GPU's, Server CPU's and more.
\vspace{4pt
}\\
82 Compilers also need flexibility in vectorisation to optimise for cost
83 of pipeline setup, amount of state to context switch
84 and software portability
\vspace{4pt
}
86 By marking INT/FP regs as "Vectorised" and
87 adding a level of indirection,
88 SV expresses how existing instructions should act
89 on
[contiguous
] blocks of registers, in parallel.
\vspace{4pt
}
91 Simple-V is an "API" that implicitly extends
92 existing (scalar) instructions with explicit parallelisation\\
93 (i.e. SV is actually about parallelism NOT vectors per se)
98 \frame{\frametitle{What's the value of SV? Why adopt it even in non-V?
}
101 \item memcpy becomes much smaller (higher bang-per-buck)
102 \item context-switch (LOAD/STORE multiple):
1-
2 instructions
103 \item Compressed instrs further reduces I-cache (etc.)
104 \item Greatly-reduced I-cache load (and less reads)
105 \item Amazingly, SIMD becomes (more) tolerable\\
106 (corner-cases for setup and teardown are gone)
107 \item Modularity/Abstraction in both the h/w and the toolchain.
108 \item "Reach" of registers accessible by Compressed is enhanced
112 \item It's not just about Vectors: it's about instruction effectiveness
113 \item Anything implementor is not interested in HW-optimising,\\
114 let it fall through to exceptions (implement as a trap).
119 \frame{\frametitle{How does Simple-V relate to RVV? What's different?
}
122 \item RVV very heavy-duty (excellent for supercomputing)
\vspace{10pt
}
123 \item Simple-V abstracts parallelism (based on best of RVV)
\vspace{10pt
}
124 \item Graded levels: hardware, hybrid or traps (fit impl. need)
\vspace{10pt
}
125 \item Even Compressed become vectorised (RVV can't)
\vspace{10pt
}
127 What Simple-V is not:
\vspace{10pt
}
129 \item A full supercomputer-level Vector Proposal
130 \item A replacement for RVV (SV is designed to be over-ridden\\
131 by - or augmented to become - RVV)
136 \frame{\frametitle{How is Parallelism abstracted in Simple-V?
}
139 \item Register "typing" turns any op into an implicit Vector op:\\
140 registers are reinterpreted through a level of indirection
141 \item Primarily at the Instruction issue phase (except SIMD)\\
142 Note: it's ok to pass predication through to ALU (like SIMD)
143 \item Standard (and future, and custom) opcodes now parallel
\vspace{10pt
}
145 Note: EVERYTHING is parallelised:
147 \item All LOAD/STORE (inc. Compressed, Int/FP versions)
148 \item All ALU ops (Int, FP, SIMD, DSP, everything)
149 \item All branches become predication targets (C.FNE added?)
150 \item C.MV of particular interest (s/v, v/v, v/s)
151 \item FCVT, FMV, FSGNJ etc. very similar to C.MV
156 \frame{\frametitle{Implementation Options
}
159 \item Absolute minimum: Exceptions: if CSRs indicate "V", trap.\\
160 (Requires as absolute minimum that CSRs be in H/W)
161 \item Hardware loop, single-instruction issue\\
162 (Do / Don't send through predication to ALU)
163 \item Hardware loop, parallel (multi-instruction) issue\\
164 (Do / Don't send through predication to ALU)
165 \item Hardware loop, full parallel ALU (not recommended)
169 \item 4 (or more?) options above may be deployed on per-op basis
170 \item SIMD always sends predication bits through to ALU
171 \item Minimum MVL MUST be sufficient to cover regfile LD/ST
172 \item Instr. FIFO may repeatedly split off N scalar ops at a time
175 % Instr. FIFO may need its own slide. Basically, the vectorised op
176 % gets pushed into the FIFO, where it is then "processed". Processing
177 % will remove the first set of ops from its vector numbering (taking
178 % predication into account) and shoving them **BACK** into the FIFO,
179 % but MODIFYING the remaining "vectorised" op, subtracting the now
180 % scalar ops from it.
182 \frame{\frametitle{Predicated
8-parallel ADD:
1-wide ALU
}
184 \includegraphics[height=
2.5in
]{padd9_alu1.png
}\\
185 {\bf \red Predicated adds are shuffled down:
6 cycles in total
}
190 \frame{\frametitle{Predicated
8-parallel ADD:
4-wide ALU
}
192 \includegraphics[height=
2.5in
]{padd9_alu4.png
}\\
193 {\bf \red Predicated adds are shuffled down:
4 in
1st cycle,
2 in
2nd
}
198 \frame{\frametitle{Predicated
8-parallel ADD:
3 phase FIFO expansion
}
200 \includegraphics[height=
2.5in
]{padd9_fifo.png
}\\
201 {\bf \red First cycle takes first four
1s; second takes the rest
}
206 \frame{\frametitle{How are SIMD Instructions Vectorised?
}
209 \item SIMD ALU(s) primarily unchanged
\vspace{6pt
}
210 \item Predication is added to each SIMD element
\vspace{6pt
}
211 \item Predication bits sent in groups to the ALU
\vspace{6pt
}
212 \item End of Vector enables (additional) predication\\
213 (completely nullifies need for end-case code)
215 Considerations:
\vspace{4pt
}
217 \item Many SIMD ALUs possible (parallel execution)
218 \item Implementor free to choose (API remains the same)
219 \item Unused ALU units wasted, but s/w DRASTICALLY simpler
220 \item Very long SIMD ALUs could waste significant die area
223 % With multiple SIMD ALUs at for example 32-bit wide they can be used
224 % to either issue 64-bit or 128-bit or 256-bit wide SIMD operations
225 % or they can be used to cover several operations on totally different
226 % vectors / registers.
228 \frame{\frametitle{Predicated
9-parallel SIMD ADD
}
230 \includegraphics[height=
2.5in
]{padd9_simd.png
}\\
231 {\bf \red 4-wide
8-bit SIMD,
4 bits of predicate passed to ALU
}
236 \frame{\frametitle{What's the deal / juice / score?
}
239 \item Standard Register File(s) overloaded with CSR "reg is vector"\\
240 (see pseudocode slides for examples)
241 \item "
2nd FP\&INT register bank" possibility (reserved for future)
242 \item Element width (and type?) concepts remain same as RVV\\
243 (CSRs give new size (and meaning?) to elements in registers)
244 \item CSRs are key-value tables (overlaps allowed: v. important)
246 Key differences from RVV:
248 \item Predication in INT regs as a BIT field (max VL=XLEN)
249 \item Minimum VL must be Num Regs -
1 (all regs single LD/ST)
250 \item SV may condense sparse Vecs: RVV lets ALU do predication
251 \item Choice to Zero or skip non-predicated elements
256 \begin{frame
}[fragile
]
257 \frametitle{ADD pseudocode (or trap, or actual hardware loop)
}
260 function op
\_add(rd, rs1, rs2, predr) # add not VADD!
261 int i, id=
0, irs1=
0, irs2=
0;
262 for (i =
0; i < VL; i++)
263 if (ireg
[predr
] &
1<<i) # predication uses intregs
264 ireg
[rd+id
] <= ireg
[rs1+irs1
] + ireg
[rs2+irs2
];
265 if (reg
\_is\_vectorised[rd
]) \
{ id +=
1; \
}
266 if (reg
\_is\_vectorised[rs1
]) \
{ irs1 +=
1; \
}
267 if (reg
\_is\_vectorised[rs2
]) \
{ irs2 +=
1; \
}
271 \item Above is oversimplified: Reg. indirection left out (for clarity).
272 \item SIMD slightly more complex (case above is elwidth = default)
273 \item Scalar-scalar and scalar-vector and vector-vector now all in one
274 \item OoO may choose to push ADDs into instr. queue (v. busy!)
278 % yes it really *is* ADD not VADD. that's the entire point of
279 % this proposal, that *standard* operations are overloaded to
280 % become vectorised-on-demand
283 \begin{frame
}[fragile
]
284 \frametitle{Predication-Branch (or trap, or actual hardware loop)
}
287 s1 = reg
\_is\_vectorised(src1);
288 s2 = reg
\_is\_vectorised(src2);
289 if (!s2 && !s1) goto branch;
290 for (int i =
0; i < VL; ++i)
291 if (cmp(s1 ? reg
[src1+i
]:reg
[src1
],
292 s2 ? reg
[src2+i
]:reg
[src2
])
297 \item SIMD slightly more complex (case above is elwidth = default)
298 \item If s1 and s2 both scalars, Standard branch occurs
299 \item Predication stored in integer regfile as a bitfield
300 \item Scalar-vector and vector-vector supported
301 \item Overload Branch immediate to be predication target rs3
305 \begin{frame
}[fragile
]
306 \frametitle{VLD/VLD.S/VLD.X (or trap, or actual hardware loop)
}
309 if (unit-strided) stride = elsize;
310 else stride = areg
[as2
]; // constant-strided
311 for (int i =
0; i < VL; ++i)
312 if (preg
\_enabled[rd
] && (
[!
]preg
[rd
] &
1<<i))
313 for (int j =
0; j < seglen+
1; j++)
314 if (reg
\_is\_vectorised[rs2
]) offs = vreg
[rs2+i
]
315 else offs = i*(seglen+
1)*stride;
316 vreg
[rd+j
][i
] = mem
[sreg
[base
] + offs + j*stride
]
320 \item Again: elwidth != default slightly more complex
321 \item rs2 vectorised taken to implicitly indicate VLD.X
326 \frame{\frametitle{Predication key-value CSR store
}
329 \item key is int regfile number or FP regfile number (
1 bit)
\vspace{6pt
}
330 \item register to be predicated if referred to (
5 bits, key)
\vspace{6pt
}
331 \item register to store actual predication in (
5 bits, value)
\vspace{6pt
}
332 \item predication is inverted Y/N (
1 bit)
\vspace{6pt
}
333 \item non-predicated elements are to be zero'd Y/N (
1 bit)
\vspace{6pt
}
337 \item Table should be expanded out for high-speed implementations
338 \item Multiple "keys" (and values) theoretically permitted
339 \item RVV rules about deleting higher-indexed CSRs followed
344 \begin{frame
}[fragile
]
345 \frametitle{Predication key-value CSR table decoding pseudocode
}
348 struct pred fp
\_pred[32];
349 struct pred int
\_pred[32];
351 for (i =
0; i <
16; i++) //
16 CSRs?
352 tb = int
\_pred if CSRpred
[i
].type ==
0 else fp
\_pred
353 idx = CSRpred
[i
].regidx
354 tb
[idx
].zero = CSRpred
[i
].zero
355 tb
[idx
].inv = CSRpred
[i
].inv
356 tb
[idx
].predidx = CSRpred
[i
].predidx
357 tb
[idx
].enabled = true
361 \item All
64 (int and FP) Entries zero'd before setting
362 \item Might be a bit complex to set up (TBD)
368 \begin{frame
}[fragile
]
369 \frametitle{Get Predication value pseudocode
}
372 def get
\_pred\_val(bool is
\_fp\_op, int reg):
373 tb = int
\_pred if is
\_fp\_op else fp
\_pred
374 if (!tb
[reg
].enabled):
375 return ~
0x0 // all ops enabled
376 predidx = tb
[reg
].predidx // redirection occurs HERE
377 predicate = intreg
[predidx
] // actual predicate HERE
379 predicate = ~predicate // invert ALL bits
384 \item References different (internal) mapping table for INT or FP
385 \item Actual predicate bitmask ALWAYS from the INT regfile
391 \frame{\frametitle{To Zero or not to place zeros in non-predicated elements?
}
394 \item Zeroing is an implementation optimisation favouring OoO
395 \item Simple implementations may skip non-predicated operations
396 \item Simple implementations explicitly have to destroy data
397 \item Complex implementations may use reg-renames to save power\\
398 Zeroing on predication chains makes optimisation harder
399 \item Compromise: REQUIRE both (specified in predication CSRs).
403 \item Complex not really impacted, simple impacted a LOT\\
404 with Zeroing... however it's useful (memzero)
405 \item Non-zero'd overlapping "Vectors" may issue overlapping ops\\
406 (
2nd op's predicated elements slot in
1st's non-predicated ops)
407 \item Please don't use Vectors for "security" (use Sec-Ext)
410 % with overlapping "vectors" - bearing in mind that "vectors" are
411 % just a remap onto the standard register file, if the top bits of
412 % predication are zero, and there happens to be a second vector
413 % that uses some of the same register file that happens to be
414 % predicated out, the second vector op may be issued *at the same time*
415 % if there are available parallel ALUs to do so.
418 \frame{\frametitle{Register key-value CSR store
}
421 \item key is int regfile number or FP regfile number (
1 bit)
422 \item treated as vector if referred to in op (
5 bits, key)
423 \item starting register to actually be used (
5 bits, value)
424 \item element bitwidth: default, dflt/
2,
8,
16 (
2 bits)
425 \item is vector: Y/N (
1 bit)
426 \item is packed SIMD: Y/N (
1 bit)
427 \item register bank:
0/reserved for future ext. (
1 bit)
431 \item References different (internal) mapping table for INT or FP
432 \item Level of indirection has implications for pipeline latency
433 \item (future) bank bit, no need to extend opcodes: set bank=
1,
434 just use normal
5-bit regs, indirection takes care of the rest.
439 \frame{\frametitle{Register element width and packed SIMD
}
443 \item default: RV32/
64/
128 opcodes define elwidth =
32/
64/
128
444 \item default/
2: RV32/
64/
128 opcodes, elwidth =
16/
32/
64 with
445 top half of register ignored (src), zero'd/s-ext (dest)
446 \item 8 or
16: elwidth =
8 (or
16), similar to default/
2
448 Packed SIMD = Y (default is moot, packing is
1:
1)
450 \item default/
2:
2 elements per register @ opcode-defined bitwidth
451 \item 8 or
16: standard
8 (or
16) packed SIMD
455 \item Different src/dest widths (and packs) PERMITTED
456 \item RV* already allows (and defines) how RV32 ops work in RV64\\
457 so just logically follow that lead/example.
462 \begin{frame
}[fragile
]
463 \frametitle{Register key-value CSR table decoding pseudocode
}
466 struct vectorised fp
\_vec[32], int
\_vec[32]; //
64 in future
468 for (i =
0; i <
16; i++) //
16 CSRs?
469 tb = int
\_vec if CSRvectortb
[i
].type ==
0 else fp
\_vec
470 idx = CSRvectortb
[i
].regidx
471 tb
[idx
].elwidth = CSRpred
[i
].elwidth
472 tb
[idx
].regidx = CSRpred
[i
].regidx // indirection
473 tb
[idx
].isvector = CSRpred
[i
].isvector
474 tb
[idx
].packed = CSRpred
[i
].packed // SIMD or not
475 tb
[idx
].bank = CSRpred
[i
].bank //
0 (
1=reserved)
479 \item All
64 (int and FP) Entries zero'd before setting
480 \item Might be a bit complex to set up (TBD)
486 \begin{frame
}[fragile
]
487 \frametitle{ADD pseudocode with redirection, this time
}
490 function op
\_add(rd, rs1, rs2) # add not VADD!
491 int i, id=
0, irs1=
0, irs2=
0;
492 rd = int
\_vec[rd
].isvector ? int
\_vec[rd
].regidx : rd;
493 rs1 = int
\_vec[rs1
].isvector ? int
\_vec[rs1
].regidx : rs1;
494 rs2 = int
\_vec[rs2
].isvector ? int
\_vec[rs2
].regidx : rs2;
495 predval = get
\_pred\_val(FALSE, rd);
496 for (i =
0; i < VL; i++)
497 if (predval \&
1<<i) # predication uses intregs
498 ireg
[rd+id
] <= ireg
[rs1+irs1
] + ireg
[rs2+irs2
];
499 if (int
\_vec[rd
].isvector) \
{ id +=
1; \
}
500 if (int
\_vec[rs1
].isvector) \
{ irs1 +=
1; \
}
501 if (int
\_vec[rs2
].isvector) \
{ irs2 +=
1; \
}
505 \item SIMD (elwidth != default) not covered above
510 \frame{\frametitle{Why are overlaps allowed in Regfiles?
}
513 \item Same register(s) can have multiple "interpretations"
514 \item Set "real" register (scalar) without needing to set/unset CSRs.
515 \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops
516 \item (
32-bit GREV plus
4x8-bit SIMD plus
32-bit GREV:\\
517 GREV @ VL=N,wid=
32; SIMD @ VL=Nx4,wid=
8)
518 \item RGB
565 (video): BEXTW plus
4x8-bit SIMD plus BDEPW\\
519 (BEXT/BDEP @ VL=N,wid=
32; SIMD @ VL=Nx4,wid=
8)
520 \item Same register(s) can be offset (no need for VSLIDE)
\vspace{6pt
}
524 \item xBitManip reduces O($N^
{6}$) SIMD down to O($N^
{3}$)
525 \item Hi-Performance: Macro-op fusion (more pipeline stages?)
530 \frame{\frametitle{C.MV extremely flexible!
}
533 \item scalar-to-vector (w/ no pred): VSPLAT
534 \item scalar-to-vector (w/ dest-pred): Sparse VSPLAT
535 \item scalar-to-vector (w/
1-bit dest-pred): VINSERT
536 \item vector-to-scalar (w/
[1-bit?
] src-pred): VEXTRACT
537 \item vector-to-vector (w/ no pred): Vector Copy
538 \item vector-to-vector (w/ src pred): Vector Gather
539 \item vector-to-vector (w/ dest pred): Vector Scatter
540 \item vector-to-vector (w/ src \& dest pred): Vector Gather/Scatter
545 \item Surprisingly powerful! Zero-predication even more so
546 \item Same arrangement for FVCT, FMV, FSGNJ etc.
551 \begin{frame
}[fragile
]
552 \frametitle{MV pseudocode with predication
}
555 function op
\_mv(rd, rs) # MV not VMV!
556 rd = int
\_vec[rd
].isvector ? int
\_vec[rd
].regidx : rd;
557 rs = int
\_vec[rs
].isvector ? int
\_vec[rs
].regidx : rs;
558 ps = get
\_pred\_val(FALSE, rs); # predication on src
559 pd = get
\_pred\_val(FALSE, rd); # ... AND on dest
560 for (int i =
0, int j =
0; i < VL && j < VL;):
561 if (int
\_vec[rs
].isvec) while (!(ps \&
1<<i)) i++;
562 if (int
\_vec[rd
].isvec) while (!(pd \&
1<<j)) j++;
563 ireg
[rd+j
] <= ireg
[rs+i
];
564 if (int
\_vec[rs
].isvec) i++;
565 if (int
\_vec[rd
].isvec) j++;
569 \item elwidth != default not covered above (might be a bit hairy)
570 \item Ending early with
1-bit predication not included (VINSERT)
575 \begin{frame
}[fragile
]
576 \frametitle{VSELECT: stays or goes? Stays if MV.X exists...
}
579 def op_mv_x(rd, rs): # (hypothetical) RV MX.X
580 rs = regfile
[rs
] # level of indirection (MV.X)
581 regfile
[rd
] = regfile
[rs
] # straight regcopy
584 Vectorised version aka "VSELECT":
587 def op_mv_x(rd, rs): # SV version of MX.X
589 rs1 = regfile
[rs+i
] # indirection
590 regfile
[rd+i
] = regfile
[rs
] # straight regcopy
594 \item However MV.X does not exist in RV, so neither can VSELECT
595 \item \red SV is not about adding new functionality, only parallelism
602 \frame{\frametitle{Opcodes, compared to RVV
}
605 \item All integer and FP opcodes all removed (no CLIP, FNE)
606 \item VMPOP, VFIRST etc. all removed (use xBitManip)
607 \item VSLIDE removed (use regfile overlaps)
608 \item C.MV covers VEXTRACT VINSERT and VSPLAT (and more)
609 \item Vector (or scalar-vector) copy: use C.MV (MV is a pseudo-op)
610 \item VMERGE: twin predicated C.MVs (one inverted. macro-op'd)
611 \item VSETVL, VGETVL stay (the only ops that do!)
615 \item VSELECT stays? no MV.X, so no (add with custom ext?)
616 \item VSNE exists, but no FNE (use predication inversion?)
617 \item VCLIP is not in RV* (add with custom ext?)
622 \begin{frame
}[fragile
]
623 \frametitle{Example c code: DAXPY
}
626 void daxpy(size_t n, double a,
627 const double x
[], double y
[])
629 for (size_t i =
0; i < n; i++) \
{
630 y
[i
] = a*x
[i
] + y
[i
];
636 \item See "SIMD Considered Harmful" for SIMD/RVV analysis\\
637 https://sigarch.org/simd-instructions-considered-harmful/
644 \begin{frame
}[fragile
]
645 \frametitle{RVV DAXPY assembly (RV32V)
}
648 # a0 is n, a1 is ptr to x
[0], a2 is ptr to y
[0], fa0 is a
650 vsetdcfg t0 # enable
2 64b Fl.Pt. registers
652 setvl t0, a0 # vl = t0 = min(mvl, n)
653 vld v0, a1 # load vector x
654 slli t1, t0,
3 # t1 = vl *
8 (in bytes)
655 vld v1, a2 # load vector y
656 add a1, a1, t1 # increment pointer to x by vl*
8
657 vfmadd v1, v0, fa0, v1 # v1 += v0 * fa0 (y = a * x + y)
658 sub a0, a0, t0 # n -= vl (t0)
660 add a2, a2, t1 # increment pointer to y by vl*
8
661 bnez a0, loop # repeat if n !=
0
666 \begin{frame
}[fragile
]
667 \frametitle{SV DAXPY assembly (RV64D)
}
670 # a0 is n, a1 is ptr to x
[0], a2 is ptr to y
[0], fa0 is a
671 CSRvect1 = \
{type: F, key: a3, val: a3, elwidth: dflt\
}
672 CSRvect2 = \
{type: F, key: a7, val: a7, elwidth: dflt\
}
674 setvl t0, a0,
4 # vl = t0 = min(
4, n)
675 ld a3, a1 # load
4 registers a3-
6 from x
676 slli t1, t0,
3 # t1 = vl *
8 (in bytes)
677 ld a7, a2 # load
4 registers a7-
10 from y
678 add a1, a1, t1 # increment pointer to x by vl*
8
679 fmadd a7, a3, fa0, a7 # v1 += v0 * fa0 (y = a * x + y)
680 sub a0, a0, t0 # n -= vl (t0)
681 st a7, a2 # store
4 registers a7-
10 to y
682 add a2, a2, t1 # increment pointer to y by vl*
8
683 bnez a0, loop # repeat if n !=
0
688 \frame{\frametitle{Under consideration
}
691 \item Is C.FNE actually needed? Should it be added if it is?
692 \item Element type implies polymorphism. Should it be in SV?
693 \item Should use of registers be allowed to "wrap" (x30 x31 x1 x2)?
694 \item Is detection of all-scalar ops ok (without slowing pipeline)?
695 \item Can VSELECT be removed? (it's really complex)
696 \item Can CLIP be done as a CSR (mode, like elwidth)
697 \item SIMD saturation (etc.) also set as a mode?
698 \item Include src1/src2 predication on Comparison Ops?\\
699 (same arrangement as C.MV, with same flexibility/power)
700 \item 8/
16-bit ops is it worthwhile adding a "start offset"? \\
701 (a bit like misaligned addressing... for registers)\\
702 or just use predication to skip start?
707 \frame{\frametitle{What's the downside(s) of SV?
}
709 \item EVERY register operation is inherently parallelised\\
710 (scalar ops are just vectors of length
1)
\vspace{4pt
}
711 \item Tightly coupled with the core (instruction issue)\\
712 could be disabled through MISA switch
\vspace{4pt
}
713 \item An extra pipeline phase almost certainly essential\\
714 for fast low-latency implementations
\vspace{4pt
}
715 \item With zeroing off, skipping non-predicated elements is hard:\\
716 it is however an optimisation (and could be skipped).
\vspace{4pt
}
717 \item Setting up the Register/Predication tables (interpreting the\\
718 CSR key-value stores) might be a bit complex to optimise
719 (any change to a CSR key-value entry needs to redo the table)
724 \frame{\frametitle{Is this OK (low latency)? Detect scalar-ops (only)
}
726 \includegraphics[height=
2.5in
]{scalardetect.png
}\\
727 {\bf \red Detect when all registers are scalar for a given op
}
732 \frame{\frametitle{Summary
}
735 \item Actually about parallelism, not Vectors (or SIMD) per se\\
736 and NOT about adding new ALU/logic/functionality.
737 \item Only needs
2 actual instructions (plus the CSRs).\\
738 RVV - and "standard" SIMD - require ISA duplication
739 \item Designed for flexibility (graded levels of complexity)
740 \item Huge range of implementor freedom
741 \item Fits RISC-V ethos: achieve more with less
742 \item Reduces SIMD ISA proliferation by
3-
4 orders of magnitude \\
743 (without SIMD downsides or sacrificing speed trade-off)
744 \item Covers
98\% of RVV, allows RVV to fit "on top"
745 \item Byproduct of SV is a reduction in code size, power usage
746 etc. (increase efficiency, just like Compressed)
753 {\Huge The end
\vspace{20pt
}\\
754 Thank you
\vspace{20pt
}\\
755 Questions?
\vspace{20pt
}
760 \item Discussion: ISA-DEV mailing list
761 \item http://libre-riscv.org/simple
\_v\_extension/