simple_v_extension/specification/mv.x.rst

   1 MV.X and MV.swizzle
   2 ===================
   3
   4 swizzle needs a MV.  see below for a potential way to use the funct7 to do a swizzle in rs2.
   5
   6 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
   7 | Encoding      | 31:27       | 26:25 | 24:20    | 19:15    | 14:12  | 11:7     | 6:2    | 1:0    |
   8 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
   9 | RV32-I-type   + imm[11:0]                      + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
  10 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
  11 | RV32-I-type   + fn4[11:8] swizzle[7:0]         + rs1[4:0] + 0b000  | rd[4:0]  + OP-V   + 0b11   |
  12 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
  13
  14 * funct3 = MV
  15 * OP-V = 0b1010111
  16 * fn4 = 4 bit function.
  17 * fn4 = 0b0000 - INT MV-SWIZZLE ?
  18 * fn4 = 0b0001 - FP MV-SWIZZLE ?
  19
  20 swizzle (only active on SV or P48/P64 when SUBVL!=0):
  21
  22 +-----+-----+-----+-----+
  23 | 7:6 | 5:4 | 3:2 | 1:0 |
  24 +-----+-----+-----+-----+
  25 |   w |   z |   y |   x |
  26 +-----+-----+-----+-----+
  27
  28 ----
  29
  30 potential MV.X?  register-version of MV-swizzle?
  31
  32 +-------------+-------+-------+----------+----------+--------+----------+--------+--------+
  33 | Encoding    | 31:27 | 26:25 | 24:20    | 19:15    | 14:12  | 11:7     | 6:2    | 1:0    |
  34 +-------------+-------+-------+----------+----------+--------+----------+--------+--------+
  35 | RV32-R-type + funct7        + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
  36 +-------------+-------+-------+----------+----------+--------+----------+--------+--------+
  37 | RV32-R-type + 0b0000000     + rs2[4:0] + rs1[4:0] + 0b001  | rd[4:0]  + OP-V   + 0b11   |
  38 +-------------+-------+-------+----------+----------+--------+----------+--------+--------+
  39
  40 * funct3 = MV.X
  41 * OP-V = 0b1010111
  42 * funct7 = 0b0000000 - INT MV.X
  43 * funct7 = 0b0000001 - FP MV.X
  44 * funct7 = 0b0000010 - INT MV.swizzle to say that rs2 is a swizzle argument?
  45 * funct7 = 0b0000011 - FP MV.swizzle to say that rs2 is a swizzle argument?
  46
  47 question: do we need a swizzle MV.X as well?
  48
  49 macro-op fusion
  50 ===============
  51
  52 there is the potential for macro-op fusion of mv-swizzle with the following instruction and/or preceding instruction.
  53 <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-August/002486.html>
  54
  55 VBLOCK context?
  56 ===============
  57
  58 additional idea: a VBLOCK context that says that if a given register is used, it indicates that the
  59 register is to be "swizzled", and the VBLOCK swizzle context contains the swizzling to be carried out.
  60
  61 mm_shuffle_ps?
  62 ==============
  63
  64 __m128 _mm_shuffle_ps(__m128 lo,__m128 hi,
  65        _MM_SHUFFLE(hi3,hi2,lo1,lo0))
  66 Interleave inputs into low 2 floats and high 2 floats of output. Basically
  67    out[0]=lo[lo0];
  68    out[1]=lo[lo1];
  69    out[2]=hi[hi2];
  70    out[3]=hi[hi3];
  71
  72 For example, _mm_shuffle_ps(a,a,_MM_SHUFFLE(i,i,i,i)) copies the float
  73 a[i] into all 4 output floats.