simple_v_extension/specification/sv.setvl.mdwn

   1 # SV setvl
   2
   3 sv.setvl allows optional setting of both MVL and of indirectly marking one of the scalar registers as being VL.
   4
   5 Unlike the majority of other CSRs, which contain status bits that change behaviour, VL is closely interlinked with the instructions it affects and often requires arithmetic interaction.
   6
   7 Thus it makes more sense to actually *use* one of the scalar registers *as* VL.
   8
   9 A potential implementation optimisation technique involves keeping 5 bits which specify the scalar register in use as VL actually in the instruction decode phase.  On detection of a CSRR rd, VL, if the cached copy of VL is not pointing to x0, the CSRR instruction is *replaced* with a "MV rd, vlcachedreg" instruction. See [[discussion]] for further details.
  10
  11 Format for Vector Configuration Instructions under OP-V major opcode:
  12
  13 | 31|30   20|19    15|14   12|11 7|6     0| name       |
  14 |---|-------|--------|-------|----|-------|------------|
  15 | 0 | VLMAX | rs1    | 1 1 1 | rd |1010111| sv.setvl   |
  16 | 0 | VLMAX | 0 (x0) | 1 1 1 | rd |1010111| sv.setvl   |
  17 | 1 | --    | --     | 1 1 1 | -- |1010111| *reserved* |
  18
  19
  20 # pseudocode
  21
  22     regs = [0u64; 128];
  23     vlval = 0;
  24     vl = rd;
  25
  26     // instruction fields:
  27     rd = get_rd_field();
  28     rs1 = get_rs1_field();
  29     vlmax = get_immed_field();
  30
  31     // handle illegal instruction decoding
  32     if vlmax > XLEN {
  33         trap()
  34     }
  35
  36     // calculate VL
  37     if rs1 == 0 { // rs1 is x0
  38         vlval = vlmax
  39     } else {
  40         vlval = min(regs[rs1], vlmax)
  41     }
  42
  43     // write rd
  44     if rd != 0 {
  45         // rd is not x0
  46         regs[rd] = vlval;
  47     }
  48
  49 # questions <a name="questions"></>
  50
  51 Moved to [[discussion]]
  52