3 Formats for Vector Configuration Instructions under OP-V major opcode:
5 | 31|30 25|24 20|19 15|14 12|11 7|6 0| name |
6 |---|------------------------|----------|-------|---------|-------|---------|
7 | 0 | imm[10:6] |imm[4:0] | rs1 | 1 1 1 | rd |1010111| vsetvli |
8 | 1 | 000000 | rs2 | rs1 | 1 1 1 | rd |1010111| vsetvl |
9 | 1 | 6 | 5 | 5 | 3 | 5 | 7 | |
11 Requirement: fit MVL into this format.
13 | 31|30 25|24 20|19 15|14 12|11 7|6 0| name |
14 |---|-------------|----------|----------|-------|---------|-------|---------|
15 | 0 | imm[10:6] |imm[4:0] | rs1 | 1 1 1 | rd |1010111| vsetvli |
16 | 1 | imm[5:0] | rs2 | rs1 | 1 1 1 | rd |1010111| vsetvl |
17 | 1 | 6 | 5 | 5 | 3 | 5 | 7 | |
21 * when bit 31==0, both MVL and VL are set to imm(10:6) - plus one to
22 get it out of the "NOP" scenario.
23 * when bit 31==1, MVL is set to imm(5:0) plus one.
25 hang on... no, that's a 4-argument setvl! what about this?
28 | 31|30 25|24 20|19 15|14 12|11 7|6 0| name | variant# |
29 |---|-------------|----------|----------|-------|---------|-------|---------|------------|
30 | 0 | imm[5:0] | 0b00000 | rs1 | 1 1 1 | rd |1010111| vsetvli | 1 |
31 | 0 | imm[5:0] | 0b00000 | 0b00000 | 1 1 1 | rd |1010111| vsetvli | 2 |
32 | 0 | imm[5:0] | rs2!=x0 | rs1 | 1 1 1 | rd |1010111| vsetvli | 3 |
33 | 0 | imm[5:0] | rs2!=x0 | 0b00000 | 1 1 1 | rd |1010111| vsetvli | 4 |
34 | 1 | imm[5:0] | 0b00000 | rs1 | 1 1 1 | rd |1010111| vsetvl | 5 |
35 | 1 | imm[5:0] | 0b00000 | 0b00000 | 1 1 1 | rd |1010111| vsetvl | 6 |
36 | 1 | imm[5:0] | rs2!=x0 | rs1 | 1 1 1 | rd |1010111| vsetvl | 7 |
37 | 1 | imm[5:0] | rs2!=x0 | 0b00000 | 1 1 1 | rd |1010111| vsetvl | 8 |
38 | 1 | 6 | 5 | 5 | 3 | 5 | 7 | | |
40 i think those are the 8 permutations: what can those be used for? some of them for actual
41 instructions (brownfield encodings).
43 | name | variant# - | purpose |
44 |---------|------------|------------------------------------------------|
45 | vsetvli | 1 | vl = min(rf[rs1], VLMAX), if (!rd) rf[rd]=rd |
46 | vsetvli | 2 | vl = VLMAX immed , if (!rd) rf[rd]=rd |
56 * there's no behavioural difference between the vsetvl version and the
57 vsetvli version. that needs fixing (somehow, doing something)
58 * the above 4 fit into the "rs2 == x0" case, leaving "rs2 != x0" for
66 // instruction fields:
68 rs1 = get_rs1_field();
69 vlmax = get_immed_field();
71 // handle illegal instruction decoding
77 if rs1 == 0 { // rs1 is x0
80 vl = min(regs[rs1], vlmax)