simple_v_extension/specification/sv.setvl.mdwn

   1 # SV setvl exploration
   2
   3 Formats for Vector Configuration Instructions under OP-V major opcode:
   4
   5 | 31|30         25|24      20|19      15|14   12|11      7|6     0| name    |
   6 |---|------------------------|----------|-------|---------|-------|---------|
   7 | 0 |  imm[10:6]  |imm[4:0]  |    rs1   | 1 1 1 |    rd   |1010111| vsetvli |
   8 | 1 |   000000    |   rs2    |    rs1   | 1 1 1 |    rd   |1010111| vsetvl  |
   9 | 1 |      6      |     5    |     5    |   3   |    5    |   7   |         |
  10
  11 Requirement: fit MVL into this format.
  12
  13 | 31|30         25|24      20|19      15|14   12|11      7|6     0| name    |
  14 |---|-------------|----------|----------|-------|---------|-------|---------|
  15 | 0 |  imm[10:6]  |imm[4:0]  |    rs1   | 1 1 1 |    rd   |1010111| vsetvli |
  16 | 1 |   imm[5:0]  |   rs2    |    rs1   | 1 1 1 |    rd   |1010111| vsetvl  |
  17 | 1 |      6      |     5    |     5    |   3   |    5    |   7   |         |
  18
  19 where:
  20
  21 * when bit 31==0, both MVL and VL are set to imm(10:6) - plus one to
  22   get it out of the "NOP" scenario.
  23 * when bit 31==1, MVL is set to imm(5:0) plus one.
  24
  25 hang on... no, that's a 4-argument setvl!  what about this?
  26
  27
  28 | 31|30         25|24      20|19      15|14   12|11      7|6     0| name    | variant#   |
  29 |---|-------------|----------|----------|-------|---------|-------|---------|------------|
  30 | 0 | imm[5:0]    | 0b00000  |    rs1   | 1 1 1 |    rd   |1010111| vsetvli | 1          |
  31 | 0 | imm[5:0]    | 0b00000  |  0b00000 | 1 1 1 |    rd   |1010111| vsetvli | 2          |
  32 | 0 |   imm[5:0]  | rs2!=x0  |    rs1   | 1 1 1 |    rd   |1010111| vsetvli | 3          |
  33 | 0 |   imm[5:0]  | rs2!=x0  |  0b00000 | 1 1 1 |    rd   |1010111| vsetvli | 4          |
  34 | 1 | imm[5:0]    | 0b00000  |    rs1   | 1 1 1 |    rd   |1010111| vsetvl  | 5          |
  35 | 1 | imm[5:0]    | 0b00000  |  0b00000 | 1 1 1 |    rd   |1010111| vsetvl  | 6          |
  36 | 1 |   imm[5:0]  | rs2!=x0  |    rs1   | 1 1 1 |    rd   |1010111| vsetvl  | 7          |
  37 | 1 |   imm[5:0]  | rs2!=x0  |  0b00000 | 1 1 1 |    rd   |1010111| vsetvl  | 8          |
  38 | 1 |      6      |     5    |     5    |   3   |    5    |   7   |         |            |
  39
  40 i think those are the 8 permutations: what can those be used for?  some of them for actual
  41 instructions (brownfield encodings).
  42
  43 | name    | variant# - | purpose                                        |
  44 |---------|------------|------------------------------------------------|
  45 | vsetvli | 1          | vl = min(rf[rs1], VLMAX), if (!rd) rf[rd]=rd   |
  46 | vsetvli | 2          | vl = VLMAX immed        , if (!rd) rf[rd]=rd   |
  47 | vsetvli | 3          | TBD                                            |
  48 | vsetvli | 4          | TBD                                            |
  49 | vsetvl  | 5          | TBD                                            |
  50 | vsetvl  | 6          | TBD                                            |
  51 | vsetvl  | 7          | TBD                                            |
  52 | vsetvl  | 8          | TBD                                            |
  53
  54 notes:
  55
  56 * there's no behavioural difference between the vsetvl version and the
  57   vsetvli version.  that needs fixing (somehow, doing something)
  58 * the above 4 fit into the "rs2 == x0" case, leaving "rs2 != x0" for
  59   brownfield encodings.
  60
  61 # original encoding
  62
  63 Selected encoding for sv.setvl, see http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-June/001898.html
  64
  65 The encoding I (programmerjake) was planning on using is:
  66
  67 | 31|30   20|19    15|14   12|11 7|6     0| name       |
  68 |---|-------|--------|-------|----|-------|------------|
  69 | 0 | VLMAX | rs1    | 1 1 1 | rd |1010111| sv.setvl   |
  70 | 0 | VLMAX | 0 (x0) | 1 1 1 | rd |1010111| sv.setvl   |
  71 | 1 | --    | --     | 1 1 1 | -- |1010111| *reserved* |
  72
  73 It leaves space for future expansion to RV128 and/or multi-register predicates.
  74
  75 > it's the opcode and funct7 that are actually used to determine the
  76 > instruction for almost all RISC-V instructions, therefore, I think we
  77 > should use the lower bits of the immediate in I-type to encode MAXVL.
  78 > This also has the benefit of simple extension of VL/MAXVL since the
  79 > bits immediately above the MAXVL field aren't used. If a new
  80 > instruction wants to be able to use rs2, it simply uses the encoding
  81 > with bit 31 set, which already indicates that rs2 is wanted in the V
  82 > extension.
  83
  84 >> yep, good logic.
  85
  86 # pseudocode
  87
  88     regs = [0u64; 128];
  89     vl = 0;
  90
  91     // instruction fields:
  92     rd = get_rd_field();
  93     rs1 = get_rs1_field();
  94     vlmax = get_immed_field();
  95
  96     // handle illegal instruction decoding
  97     if vlmax > XLEN {
  98         trap()
  99     }
 100
 101     // calculate VL
 102     if rs1 == 0 { // rs1 is x0
 103         vl = vlmax
 104     } else {
 105         vl = min(regs[rs1], vlmax)
 106     }
 107
 108     // write rd
 109     if rd != 0 {
 110         // rd is not x0
 111         regs[rd] = vl
 112     }
 113
 114 # links
 115
 116 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-June/001881.html>