simple_v_extension/specification/sv.setvl.mdwn

   1 [[!tag standards]]
   2
   3 # SV setvl
   4
   5 sv.setvl allows optional setting of both MVL and of indirectly marking
   6 one of the scalar registers as being VL.
   7
   8 Unlike the majority of other CSRs, which contain status bits that change
   9 behaviour, VL is closely interlinked with the instructions it affects
  10 and often requires arithmetic interaction.  Thus it makes more sense to
  11 actually *use* one of the scalar registers *as* VL.
  12
  13 Format for Vector Configuration Instructions under OP-V major opcode:
  14
  15 | 31|30...20|19....15|14..12|11.7|6.....0| name       |
  16 |---|-------|--------|------|----|-------|------------|
  17 | 0 | VLMAX | rs1    | 111  | rd |1010111| sv.setvl   |
  18 | 0 | VLMAX | 0 (x0) | 111  | rd |1010111| sv.setvl   |
  19 | 1 | --    | --     | 111  | -- |1010111| *reserved* |
  20
  21
  22 # pseudocode
  23
  24     regs = [0u64; 128];
  25     vlval = 0;
  26     vl = rd;
  27
  28     // instruction fields:
  29     rd = get_rd_field();
  30     rs1 = get_rs1_field();
  31     vlmax = get_immed_field();
  32
  33     // handle illegal instruction decoding
  34     if vlmax > XLEN {
  35         trap()
  36     }
  37
  38     // calculate VL
  39     if rs1 == 0 { // rs1 is x0
  40         vlval = vlmax
  41     } else {
  42         vlval = min(regs[rs1], vlmax)
  43     }
  44
  45     // write rd
  46     if rd != 0 {
  47         // rd is not x0
  48         regs[rd] = vlval;
  49     }
  50
  51 # questions <a name="questions"></>
  52
  53 Moved to [[discussion]]
  54