5 sv.setvl allows optional setting of both MVL and of indirectly marking
6 one of the scalar registers as being VL.
8 Unlike the majority of other CSRs, which contain status bits that change
9 behaviour, VL is closely interlinked with the instructions it affects
10 and often requires arithmetic interaction. Thus it makes more sense to
11 actually *use* one of the scalar registers *as* VL.
13 Format for Vector Configuration Instructions under OP-V major opcode:
15 | 31|30...20|19....15|14..12|11.7|6.....0| name |
16 |---|-------|--------|------|----|-------|------------|
17 | 0 | VLMAX | rs1 | 111 | rd |1010111| sv.setvl |
18 | 0 | VLMAX | 0 (x0) | 111 | rd |1010111| sv.setvl |
19 | 1 | -- | -- | 111 | -- |1010111| *reserved* |
28 // instruction fields:
30 rs1 = get_rs1_field();
31 vlmax = get_immed_field();
33 // handle illegal instruction decoding
39 if rs1 == 0 { // rs1 is x0
42 vlval = min(regs[rs1], vlmax)
51 # questions <a name="questions"></>
53 Moved to [[discussion]]