simple_v_extension/specification/sv.setvl.mdwn

   1 # SV setvl exploration
   2
   3 Formats for Vector Configuration Instructions under OP-V major opcode:
   4
   5 | 31|30         25|24      20|19      15|14   12|11      7|6     0| name    |
   6 |---|------------------------|----------|-------|---------|-------|---------|
   7 | 0 |  imm[10:6]  |imm[4:0]  |    rs1   | 1 1 1 |    rd   |1010111| vsetvli |
   8 | 1 |   000000    |   rs2    |    rs1   | 1 1 1 |    rd   |1010111| vsetvl  |
   9 | 1 |      6      |     5    |     5    |   3   |    5    |   7   |         |
  10
  11 Requirement: fit MVL into this format.
  12
  13 | 31|30         25|24      20|19      15|14   12|11      7|6     0| name    |
  14 |---|-------------|----------|----------|-------|---------|-------|---------|
  15 | 0 |  imm[10:6]  |imm[4:0]  |    rs1   | 1 1 1 |    rd   |1010111| vsetvli |
  16 | 1 |   imm[5:0]  |   rs2    |    rs1   | 1 1 1 |    rd   |1010111| vsetvl  |
  17 | 1 |      6      |     5    |     5    |   3   |    5    |   7   |         |
  18
  19 where:
  20
  21 * when bit 31==0, both MVL and VL are set to imm(10:6) - plus one to
  22   get it out of the "NOP" scenario.
  23 * when bit 31==1, MVL is set to imm(5:0) plus one.
  24
  25 hang on... no, that's a 4-argument setvl!  what about this?
  26
  27
  28 | 31|30         25|24      20|19      15|14   12|11      7|6     0| name    | variant#   |
  29 |---|-------------|----------|----------|-------|---------|-------|---------|------------|
  30 | 0 | imm[5:0]    | 0b00000  |    rs1   | 1 1 1 |    rd   |1010111| vsetvli | 1          |
  31 | 0 | imm[5:0]    | 0b00000  |  0b00000 | 1 1 1 |    rd   |1010111| vsetvli | 2          |
  32 | 0 |   imm[5:0]  | rs2!=x0  |    rs1   | 1 1 1 |    rd   |1010111| vsetvli | 3          |
  33 | 0 |   imm[5:0]  | rs2!=x0  |  0b00000 | 1 1 1 |    rd   |1010111| vsetvli | 4          |
  34 | 1 | imm[5:0]    | 0b00000  |    rs1   | 1 1 1 |    rd   |1010111| vsetvl  | 5          |
  35 | 1 | imm[5:0]    | 0b00000  |  0b00000 | 1 1 1 |    rd   |1010111| vsetvl  | 6          |
  36 | 1 |   imm[5:0]  | rs2!=x0  |    rs1   | 1 1 1 |    rd   |1010111| vsetvl  | 7          |
  37 | 1 |   imm[5:0]  | rs2!=x0  |  0b00000 | 1 1 1 |    rd   |1010111| vsetvl  | 8          |
  38 | 1 |      6      |     5    |     5    |   3   |    5    |   7   |         |            |
  39
  40 i think those are the 8 permutations: what can those be used for?  some of them for actual
  41 instructions (brownfield encodings).
  42
  43 | name    | variant# - | purpose                                        |
  44 |---------|------------|------------------------------------------------|
  45 | vsetvli | 1          | vl = min(rf[rs1], VLMAX), if (!rd) rf[rd]=rd   |
  46 | vsetvli | 2          | vl = VLMAX immed        , if (!rd) rf[rd]=rd   |
  47 | vsetvli | 3          | TBD                                            |
  48 | vsetvli | 4          | TBD                                            |
  49 | vsetvl  | 5          | TBD                                            |
  50 | vsetvl  | 6          | TBD                                            |
  51 | vsetvl  | 7          | TBD                                            |
  52 | vsetvl  | 8          | TBD                                            |
  53
  54 notes:
  55
  56 * there's no behavioural difference between the vsetvl version and the
  57   vsetvli version.  that needs fixing (somehow, doing something)
  58 * the above 4 fit into the "rs2 == x0" case, leaving "rs2 != x0" for
  59   brownfield encodings.
  60
  61 The encoding I (programmerjake) was planning on using is:
  62
  63 | 31|30   20|19    15|14   12|11 7|6     0| name       |
  64 |---|-------|--------|-------|----|-------|------------|
  65 | 0 | VLMAX | rs1    | 1 1 1 | rd |1010111| sv.setvl   |
  66 | 0 | VLMAX | 0 (x0) | 1 1 1 | rd |1010111| sv.setvl   |
  67 | 1 | --    | --     | 1 1 1 | -- |1010111| *reserved* |
  68
  69 It leaves space for future expansion to RV128 and/or multi-register predicates.
  70
  71
  72 pseudocode:
  73
  74     regs = [0u64; 128];
  75     vl = 0;
  76
  77     // instruction fields:
  78     rd = get_rd_field();
  79     rs1 = get_rs1_field();
  80     vlmax = get_immed_field();
  81
  82     // handle illegal instruction decoding
  83     if vlmax > XLEN {
  84         trap()
  85     }
  86
  87     // calculate VL
  88     if rs1 == 0 { // rs1 is x0
  89         vl = vlmax
  90     } else {
  91         vl = min(regs[rs1], vlmax)
  92     }
  93
  94     // write rd
  95     if rd != 0 {
  96         // rd is not x0
  97         regs[rd] = vl
  98     }