simple_v_extension/sv_prefix_proposal/discussion.rst

   1 Questions
   2 =========
   3
   4 Confirmation needed as to whether subvector extraction can be covered
   5 by twin predication (it probably can, it is one of the many purposes it
   6 is for).
   7
   8 Answer:
   9
  10 Yes, it can, but VL needs to be changed for it to work, since predicates
  11 work at the size of a whole subvector instead of an element of that
  12 subvector. To avoid needing to constantly change VL, and since swizzles
  13 are a very common operation, I think we should have a separate instruction
  14 -- a subvector element swizzle instruction::
  15
  16     velswizzle x32, x64, SRCSUBVL=3, DESTSUBVL=4, ELTYPE=u8, elements=[0, 0, 2, 1]
  17
  18 Example pseudocode:
  19
  20 .. code:: C
  21
  22     // processor state:
  23     uint64_t regs[128];
  24     int VL = 5;
  25
  26     typedef uint8_t ELTYPE;
  27     const int SRCSUBVL = 3;
  28     const int DESTSUBVL = 4;
  29     const int elements[] = [0, 0, 2, 1];
  30     ELTYPE *rd = (ELTYPE *)&regs[32];
  31     ELTYPE *rs1 = (ELTYPE *)&regs[48];
  32     for(int i = 0; i < VL; i++)
  33     {
  34         rd[i * DESTSUBVL + 0] = rs1[i * SRCSUBVL + elements[0]];
  35         rd[i * DESTSUBVL + 1] = rs1[i * SRCSUBVL + elements[1]];
  36         rd[i * DESTSUBVL + 2] = rs1[i * SRCSUBVL + elements[2]];
  37         rd[i * DESTSUBVL + 3] = rs1[i * SRCSUBVL + elements[3]];
  38     }
  39
  40 To use the subvector element swizzle instruction to extract a subvector element,
  41 all that needs to be done is to have DESTSUBVL be 1::
  42
  43     // extract element index 2
  44     velswizzle rd, rs1, SRCSUBVL=4, DESTSUBVL=1, ELTYPE=u32, elements=[2]
  45
  46 Example pseudocode:
  47
  48 .. code:: C
  49
  50     // processor state:
  51     uint64_t regs[128];
  52     int VL = 5;
  53
  54     typedef uint32_t ELTYPE;
  55     const int SRCSUBVL = 4;
  56     const int DESTSUBVL = 1;
  57     const int elements[] = [2];
  58     ELTYPE *rd = (ELTYPE *)&regs[...];
  59     ELTYPE *rs1 = (ELTYPE *)&regs[...];
  60     for(int i = 0; i < VL; i++)
  61     {
  62         rd[i * DESTSUBVL + 0] = rs1[i * SRCSUBVL + elements[0]];
  63     }
  64
  65 Answer:
  66
  67     > ok, i like that idea - adding to TODO list
  68
  69 ----
  70
  71 What is SUBVL and how does it work
  72
  73 Answer:
  74
  75 SUBVL is the instruction field in P48 instructions that specifies
  76 the sub-vector length. The sub-vector length is the number of scalars
  77 that are grouped together and treated like an element by both VL and
  78 predication. This is used to support operations where the elements are
  79 short vectors (2-4 elements) in Vulkan and OpenGL. Those short vectors
  80 are mostly used as mathematical vectors to handle directions, positions,
  81 and colors, rather than as a pure optimization.
  82
  83 For example, when VL is 5::
  84
  85     add x32, x48, x64, SUBVL=3, ELTYPE=u16, PRED=!x9
  86
  87 performs the following operation:
  88
  89 .. code:: C
  90
  91     // processor state:
  92     uint64_t regs[128];
  93     int VL = 5;
  94
  95     // instruction fields:
  96     typedef uint16_t ELTYPE;
  97     const int SUBVL = 3;
  98     ELTYPE *rd = (ELTYPE *)&regs[32];
  99     ELTYPE *rs1 = (ELTYPE *)&regs[48];
 100     ELTYPE *rs2 = (ELTYPE *)&regs[64];
 101     for(int i = 0; i < VL; i++)
 102     {
 103         if(~regs[9] & 0x1)
 104         {
 105             rd[i * SUBVL + 0] = rs1[i * SUBVL + 0] + rs2[i * SUBVL + 0];
 106             rd[i * SUBVL + 1] = rs1[i * SUBVL + 1] + rs2[i * SUBVL + 1];
 107             rd[i * SUBVL + 2] = rs1[i * SUBVL + 2] + rs2[i * SUBVL + 2];
 108         }
 109     }
 110
 111 ----
 112
 113 SVorig goes to a lot of effort to make VL 1<= MAXVL and MAXVL 1..64
 114 where both CSRs may be stored internally in only 6 bits.
 115
 116 Thus, CSRRWI can reach 1..32 for VL and MAXVL.
 117
 118 In addition, setting a hardware loop to zero turning instructions into
 119 NOPs, um, just branch over them, to start the first loop at the end,
 120 on the test for loop variable being zero, a la c "while do" instead of
 121 "do while".
 122
 123 Or, does it not matter that VL only goes up to 31 on a CSRRWI, and that
 124 it only goes to a max of 63 rather than 64?
 125
 126 Answer:
 127
 128 I think supporting SETVL where VL would be set to 0 should be done. that
 129 way, the branch can be put after SETVL, allowing SETVL to execute
 130 earlier giving more time for VL to propagate (preventing stalling)
 131 to the instruction decoder.  I have no problem with having 0 stored to
 132 VL via CSRW resulting in VL=64 (or whatever maximum value is supported
 133 in hardware).
 134
 135 One related idea would to support VL > XLEN but to only allow unpredicated
 136 instructions when VL > XLEN. This would allow later implementing register
 137 pairs/triplets/etc. as predicates as an extension.
 138
 139 ----
 140
 141 Is MV.X good enough a substitute for swizzle?
 142
 143 Answer:
 144
 145 no, since the swizzle instruction specifies in the opcode which elements are
 146 used and where they go, so it can run much faster since the execution engine
 147 doesn't need to pessimize. Additionally, swizzles almost always have constant
 148 element selectors. MV.X is meant more as a last-resort instruction that is
 149 better than load/store, but worse than everything else.
 150
 151     > ok, then we'll need a way to do that.  given that it needs to apply
 152     > to, well... everything, basically, i'm tempted to recommend it be
 153     > done as a CSR and/or as (another) table in VBLOCK.
 154     > the reason is, it's just too much to expect to massively duplicate
 155     > literally every single opcode in existence, just to add swizzle
 156     > when there's no room in the opcode space to do so.
 157     > not sure what alternatives there might be.
 158
 159 ----
 160
 161 Is vectorised srcbase ok as a gather scatter and ok substitute for
 162 register stride? 5 dependency registers (reg stride being the 5th)
 163 is quite scary
 164
 165 ----
 166
 167 Why are integer conversion instructions needed, when the main SV spec
 168 covers them by allowing elwidth to be set on both src and dest regs?
 169
 170 ----
 171
 172 Why are the SETVL rules so complex? What is the reason, how are loops
 173 carried out?
 174
 175 Partial Answer:
 176
 177 The idea is that the compiler knows maxVL at compile time since it allocated the
 178 backing registers, so SETVL has the maxVL as an immediate value. There is no
 179 maxVL CSR needed for just SVPrefix.
 180
 181     > when looking at a loop assembly sequence
 182     > i think you'll find this approach will not work.
 183     > RVV loops on which SV loops are directly based needs understanding
 184     > of the use of MIN within the actual SETVL instruction.
 185     > Yes MVL is known at compile time
 186     > however unless MVL is communicates to the hardware, SETVL just
 187     > does not work: it has absolutely no way of knowing when to stop
 188     > processing.  The point being: it's not *MVL* that's the problem
 189     > if MVL is not a CSR, it's *VL* that becomes the problem.
 190     > The only other option which does work is to set a mandatory
 191     > hardcoded MVL baked into the actual hardware.
 192     > That results in loss of flexibility and defeats the purpose of SV.
 193
 194 ----
 195
 196 With SUBVL (sub vector len) being both a CSR and also part of the 48/64
 197 bit opcode, how does that work?
 198
 199 Answer:
 200
 201 I think we should just ignore the SUBVL CSR and use the value from the
 202 SUBVL field when executing 48/64-bit instructions. For just SVPrefix,
 203 I would say that the only user-visible CSR needed is VL. This is ignoring
 204 all the state for context-switching and exception handling.
 205
 206     > the consequence of that would be that P48/64 would need
 207     > its own CSR State to track the subelement index.
 208     > or that any exceptions would need to occur on a group
 209     > basis, which is less than ideal,
 210     > and interrupts would have to be stalled.
 211     > interacting with SUBVL and requiring P48/64 to save the
 212     > STATE CSR if needed is a workable compromise that
 213     > does not result in huge CSR proliferation
 214
 215 ----
 216
 217 What are the interaction rules when a 48/64 prefix opcode has a rd/rs
 218 that already has a Vector Context for either predication or a register?
 219
 220 It would perhaps make sense (and for svlen as well) to make 48/64 isolated
 221 and unaffected by VLIW context, with the exception of VL/MVL.
 222
 223 MVL and VL should be modifiable by 64 bit prefix as they are global
 224 in nature.
 225
 226 Possible solution, svlen and VLtyp allowed to share STATE CSR however
 227 programmer becomes responsible for push and pop of state during use of
 228 a sequence of P48 and P64 ops.
 229
 230 ----
 231
 232 Can bit 60 of P64 be put to use (in all but the FR4 case)?
 233