simple_v_extension/sv_prefix_proposal.rst

   1 SimpleV Prefix (SVprefix) Proposal v0.3
   2 =======================================
   3
   4 This proposal is designed to be able to operate without SVorig, but not to
   5 require the absence of SVorig See Specification_.
   6
   7 .. _Specification: http://libre-riscv.org/simple_v_extension/specification/
   8
   9 .. contents::
  10
  11 Conventions
  12 ===========
  13
  14 Conventions used in this document:
  15 - Bits are numbered starting from 0 at the LSB, so bit 3 is 1 in the integer 8.
  16 - Bit ranges are inclusive on both ends, so 5:3 means bits 5, 4, and 3.
  17
  18 Operations work on variable-length vectors of sub-vectors, where each sub-vector
  19 has a length *svlen*, and an element type *etype*. When the vectors are stored
  20 in registers, all elements are packed so that there is no padding in-between
  21 elements of the same vector. The number of bytes in a sub-vector, *svsz*, is the
  22 product of *svlen* and the element size in bytes.
  23
  24 Half-Precision Floating Point (FP16)
  25 ====================================
  26 If the F extension is supported, SVprefix adds support for FP16 in the
  27 base FP instructions by using 10 (H) in the floating-point format field *fmt*
  28 and using 001 (H) in the floating-point load/store *width* field.
  29
  30 Compressed Instructions
  31 =======================
  32 This proposal doesn't include any prefixed RVC instructions, instead, it will
  33 include 32-bit instructions that are compressed forms of SVprefix 48-bit
  34 instructions, in the same manner that RVC instructions are compressed forms of
  35 RVI instructions. The compressed instructions will be defined later by
  36 considering which 48-bit instructions are the most common.
  37
  38 48-bit Prefixed Instructions
  39 ============================
  40 All 48-bit prefixed instructions contain a 32-bit "base" instruction as the
  41 last 4 bytes. Since all 32-bit instructions have bits 1:0 set to 11, those bits
  42 are reused for additional encoding space in the 48-bit instructions.
  43
  44 64-bit Prefixed Instructions
  45 ============================
  46
  47 The 48 bit format is further extended with the full 128-bit range on all source
  48 and destination registers, and the option to set both VL and MVL is provided.
  49
  50 48-bit Instruction Encodings
  51 ============================
  52
  53 In the following table, *Reserved* entries must be zero.  RV32 equivalent encodings
  54 included for side-by-side comparison (and listed below, separately).
  55
  56 First, bits 17:0:
  57
  58 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  59 | Encoding      | 17     | 16         | 15         | 14  | 13         | 12          | 11:7 | 6          | 5:0    |
  60 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  61 | P48-LD-type   | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  62 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  63 | P48-ST-type   |vitp7[6]| rs1[5]     | rs2[5]     | vs2 | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  64 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  65 | P48-R-type    | rd[5]  | rs1[5]     | rs2[5]     | vs2 | vs1        | vitp6              | *Reserved* | 011111 |
  66 +---------------+--------+------------+------------+-----+------------+--------------------+------------+--------+
  67 | P48-I-type    | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  68 +---------------+--------+------------+------------+-----+------------+--------------------+------------+--------+
  69 | P48-U-type    | rd[5]  | *Reserved* | *Reserved* | vd  | *Reserved* | vitp6              | *Reserved* | 011111 |
  70 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  71 | P48-FR-type   | rd[5]  | rs1[5]     | rs2[5]     | vs2 | vs1        | *Reserved*  | vtp5 | *Reserved* | 011111 |
  72 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  73 | P48-FI-type   | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  74 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  75 | P48-FR4-type  | rd[5]  | rs1[5]     | rs2[5]     | vs2 | rs3[5]     | vs3 [#fr4]_ | vtp5 | *Reserved* | 011111 |
  76 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  77
  78 .. [#fr4] Only vs2 and vs3 are included in the P48-FR4-type encoding because
  79           there is not enough space for vs1 as well, and because it is more
  80           useful to have a scalar argument for each of the multiplication and
  81           addition portions of fmadd than to have two scalars on the
  82           multiplication portion.
  83
  84 Table showing correspondance between P48-*-type and RV32-*-type.  These are
  85 bits 47:18 (RV32 shifted up by 16 bits):
  86
  87 +---------------+---------------+
  88 | Encoding      | 47:18         |
  89 +---------------+---------------+
  90 | RV32 Encoding | 31:2          |
  91 +---------------+---------------+
  92 | P48-LD-type   | RV32-I-type   |
  93 +---------------+---------------+
  94 | P48-ST-type   | RV32-S-Type   |
  95 +---------------+---------------+
  96 | P48-R-type    | RV32-R-Type   |
  97 +---------------+---------------+
  98 | P48-I-type    | RV32-I-Type   |
  99 +---------------+---------------+
 100 | P48-U-type    | RV32-U-Type   |
 101 +---------------+---------------+
 102 | P48-FR-type   | RV32-FR-Type  |
 103 +---------------+---------------+
 104 | P48-FI-type   | RV32-I-Type   |
 105 +---------------+---------------+
 106 | P48-FR4-type  | RV32-FR-type  |
 107 +---------------+---------------+
 108
 109 Table showing Standard RV32 encodings:
 110
 111 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 112 | Encoding      | 31:27       | 26:25 | 24:20    | 19:15    | 14:12  | 11:7     | 6:2    | 1      | 0          |
 113 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 114 | RV32-R-type   +    funct7           + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 115 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 116 | RV32-S-type   + imm[11:5]           + rs2[4:0] + rs1[4:0] + funct3 | imm[4:0] + opcode + 1      + 1          |
 117 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 118 | RV32-I-type   + imm[11:0]                      + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 119 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 120 | RV32-U-type   + imm[31:12]                                         | rd[4:0]  + opcode + 1      + 1          |
 121 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 122 | RV32-FR4-type + rs3[4:0]    + fmt   + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 123 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 124 | RV32-FR-type  + funct5      + fmt   + rs2[4:0] + rs1[4:0] + rm     | rd[4:0]  + opcode + 1      + 1          |
 125 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 126
 127 64-bit Instruction Encodings
 128 ============================
 129
 130 Where in the 48 bit format the prefix is "0b0011111" in bits 0 to 6, this is
 131 now set to "0b0111111".
 132
 133 +---------------+---------------+--------------+-----------+
 134 | 63:48         | 47:18         | 17:7         | 6:0       |
 135 +---------------+---------------+--------------+-----------+
 136 | 64 bit prefix | RV32[31:3]    | P48[17:7]    | 0b0111111 |
 137 +---------------+---------------+--------------+-----------+
 138
 139 * The 64 bit prefix format is below
 140 * Bits 18 to 47 contain bits 3 to 31 of a standard RV32 format
 141 * Bits 7 to 17 contain bits 7 through 17 of the P48 format
 142 * Bits 0 to 6 contain the standard RV 64-bit prefix 0b0111111
 143
 144 64 bit prefix format:
 145
 146 +--------------+-------+--------+--------+--------+--------+
 147 | Encoding     | 63    | 62     | 61     | 60     | 59:48  |
 148 +--------------+-------+--------+--------+--------+--------+
 149 | P64-LD-type  | rd[6] | rs1[6] |        |        | VLtyp  |
 150 +--------------+-------+--------+--------+--------+--------+
 151 | P64-ST-type  |       | rs1[6] | rs2[6] |        | VLtyp  |
 152 +--------------+-------+--------+--------+--------+--------+
 153 | P64-R-type   | rd[6] | rs1[6] | rs2[6] |        | VLtyp  |
 154 +--------------+-------+--------+--------+--------+--------+
 155 | P64-I-type   | rd[6] | rs1[6] |        |        | VLtyp  |
 156 +--------------+-------+--------+--------+--------+--------+
 157 | P64-U-type   | rd[6] |        |        |        | VLtyp  |
 158 +--------------+-------+--------+--------+--------+--------+
 159 | P64-FR-type  |       | rs1[6] | rs2[6] |        | VLtyp  |
 160 +--------------+-------+--------+--------+--------+--------+
 161 | P64-FI-type  | rd[6] | rs1[6] | rs2[6] |        | VLtyp  |
 162 +--------------+-------+--------+--------+--------+--------+
 163 | P64-FR4-type | rd[6] | rs1[6] | rs2[6] | rs3[6] | VLtyp  |
 164 +--------------+-------+--------+--------+--------+--------+
 165
 166 The extra bit for src and dest registers provides the full range of
 167 up to 128 registers, when combined with the extra bit from the 48 bit
 168 prefix as well.  VLtyp encodes how (whether) to set VL and MAXVL.
 169
 170 VLtyp field encoding
 171 ====================
 172
 173 +-----------+-------------+--------------+----------+----------------------+
 174 | VLtyp[11] | VLtyp[10:6] | VLtyp[5:1]   | VLtyp[0] | comment              |
 175 +-----------+-------------+--------------+----------+----------------------+
 176 | 0         |  000000     | 00000        |  0       | no change to VL/MVL  |
 177 +-----------+-------------+--------------+----------+----------------------+
 178 | 0         |  VLdest     | VLEN         |  vlt     | VL imm/reg mode (vlt)|
 179 +-----------+-------------+--------------+----------+----------------------+
 180 | 1         |  VLdest     | MVL+VL-immed | 0          | MVL/VL immed mode    |
 181 +-----------+-------------+--------------+----------+----------------------+
 182 | 1         |  VLdest     |  MVL-immed   | 1         | MVL/VL immed mode    |
 183 +-----------+-------------+--------------+----------+----------------------+
 184
 185 Note: when VLtyp is all zeros, neither VL nor MVL are changed.
 186
 187 Just as in the VLIW format, when bit 11 of VLtyp is zero:
 188
 189 * if vlt is zero, bits 1 to 5 specify the VLEN as a 5 bit immediate
 190   (offset by 1: 0b00000 represents VL=1, 0b00001 represents VL=2 etc.)
 191 * if vlt is 1, bits 1 to 5 specify the scalar (RV standard) register
 192   from which VL is set.  x0 is not permitted
 193 * VL goes into the scalar register VLdest (if VLdest is not x0)
 194
 195 When bit 11 of VLtype is 1:
 196
 197 * both MAXVL and VL are set to (VLenimmed+1)
 198 * the same value goes into the scalar register VLdest (if VLdest is not x0)
 199
 200 This gives the option to set up VL in a "loop mode" (VLtype[11]=0) or
 201 in a "one-off" mode (VLtype[11]=1) which sets both MVL and VL to the
 202 same immediate value.  This may be most useful for one-off Vectorised
 203 operations such as LOAD-MULTI / STORE-MULTI, for saving and restoration
 204 of large batches of registers in context-switches or function calls.
 205
 206 vs#/vd Fields' Encoding
 207 =======================
 208
 209 +--------+----------+----------------------------------------------------------+
 210 | vs#/vd | Mnemonic | Meaning                                                  |
 211 +========+==========+==========================================================+
 212 | 0      | S        | the rs#/rd field specifies a scalar (single sub-vector); |
 213 |        |          | the rs#/rd field is zero-extended to get the actual      |
 214 |        |          | 7-bit register number                                    |
 215 +--------+----------+----------------------------------------------------------+
 216 | 1      | V        | the rs#/rd field specifies a vector; the rs#/rd field is |
 217 |        |          | decoded using the `Vector Register Number Encoding`_ to  |
 218 |        |          | get the actual 7-bit register number                     |
 219 +--------+----------+----------------------------------------------------------+
 220
 221 If a vs#/vd field is not present, it is as if it was present with a value that
 222 is the bitwise-or of all present vs#/vd fields.
 223
 224 * scalar register numbers do NOT increment when allocated in the
 225   hardware for-loop.  the same scalar register number is handed
 226   to every ALU.
 227
 228 * vector register numbers *DO* increase when allocated in the
 229   hardware for-loop.  sequentially-increasing register data
 230   is handed to sequential ALUs.
 231
 232 Vector Register Number Encoding
 233 ===============================
 234
 235 For the 48 bit format, when vs#/vd is 1, the actual 7-bit register number is derived from the
 236 corresponding 6-bit rs#/rd field:
 237
 238 +---------------------------------+
 239 | Actual 7-bit register number    |
 240 +===========+=============+=======+
 241 | Bit 6     | Bits 5:1    | Bit 0 |
 242 +-----------+-------------+-------+
 243 | rs#/rd[0] | rs#/rd[5:1] | 0     |
 244 +-----------+-------------+-------+
 245
 246 For the 64 bit format, the 7 bit register is constructed from the 7 bit fields: bits 0 to 4 from the 32 bit RV Standard format, bit 5 from the 48 bit prefix and bit 6 from the 64 bit prefix.  Thus in the 64 bit format the full range of up to 128 registers is directly available. This for both when either scalar or vector mode is set.
 247
 248 Load/Store Kind (lsk) Field Encoding
 249 ====================================
 250
 251 +--------+-----+--------------------------------------------------------------------------------+
 252 | vd/vs2 | vs1 | Meaning                                                                        |
 253 +========+=====+================================================================================+
 254 | 0      | 0   | srcbase is scalar, LD/ST is pure scalar.                                       |
 255 +--------+-----+--------------------------------------------------------------------------------+
 256 | 1      | 0   | srcbase is scalar, LD/ST is unit strided                                       |
 257 +--------+-----+--------------------------------------------------------------------------------+
 258 | 0      | 1   | srcbase is a vector (gather/scatter aka array of srcbases). VSPLAT and VSELECT |
 259 +--------+-----+--------------------------------------------------------------------------------+
 260 | 1      | 1   | srcbase is a vector, LD/ST is a full vector LD/ST.                             |
 261 +--------+-----+--------------------------------------------------------------------------------+
 262
 263 Notes:
 264
 265 * A register strided LD/ST would require *5* registers. srcbase, vd/vs2, predicate 1, predicate 2 and the stride register.
 266 * Complex strides may all be done with a general purpose vector of srcbases.
 267 * Twin predication may be used even when vd/vs1 is a scalar, to give VSPLAT and VSELECT, because the hardware loop ends on the first occurrence of a 1 in the predicate when a predicate is applied to a scalar.
 268 * Full vectorised gather/scatter is enabled when both registers are marked as vectorised, however unlike e.g Intel AVX512, twin predication can be applied.
 269
 270 Open question: RVV overloads the width field of LOAD-FP/STORE-FP using the bit 2 to indicate additional interpretation of the 11 bit immediate. Should this be considered?
 271
 272
 273 Sub-Vector Length (svlen) Field Encoding
 274 =======================================================
 275
 276 Bitwidth, from VL's perspective, is a multiple of the elwidth times svlen.  So within each loop of VL there are svlen sub-elements of elwidth in size, just like in a SIMD architecture. When svlen is set to 0b00 (indicating svlen=1) no such SIMD-like behaviour exists and the subvectoring is disabled.
 277
 278 Predicate bits do not apply to the individual sub-vector elements, they apply to the entire subvector group. This saves instructions on setup of the predicate.
 279
 280 +----------------+-------+
 281 | svlen Encoding | Value |
 282 +================+=======+
 283 | 00             | 1     |
 284 +----------------+-------+
 285 | 01             | 2     |
 286 +----------------+-------+
 287 | 10             | 3     |
 288 +----------------+-------+
 289 | 11             | 4     |
 290 +----------------+-------+
 291
 292 TODO : resolve interactions when SV VLIW Mode is active, as SVLEN is also a CSR.
 293
 294 Predication (pred) Field Encoding
 295 =================================
 296
 297 +------+------------+--------------------+----------------------------------------+
 298 | pred | Mnemonic   | Predicate Register | Meaning                                |
 299 +======+============+====================+========================================+
 300 | 000  | *None*     | *None*             | The instruction is unpredicated        |
 301 +------+------------+--------------------+----------------------------------------+
 302 | 001  | *Reserved* | *Reserved*         |                                        |
 303 +------+------------+--------------------+----------------------------------------+
 304 | 010  | !x9        | x9 (s1)            | execute vector op[0..i] on x9[i] == 0  |
 305 +------+------------+                    +----------------------------------------+
 306 | 011  | x9         |                    | execute vector op[0..i] on x9[i] == 1  |
 307 +------+------------+--------------------+----------------------------------------+
 308 | 100  | !x10       | x10 (a0)           | execute vector op[0..i] on x10[i] == 0 |
 309 +------+------------+                    +----------------------------------------+
 310 | 101  | x10        |                    | execute vector op[0..i] on x10[i] == 1 |
 311 +------+------------+--------------------+----------------------------------------+
 312 | 110  | !x11       | x11 (a1)           | execute vector op[0..i] on x11[i] == 0 |
 313 +------+------------+                    +----------------------------------------+
 314 | 111  | x11        |                    | execute vector op[0..i] on x11[i] == 1 |
 315 +------+------------+--------------------+----------------------------------------+
 316
 317 Twin-predication (tpred) Field Encoding
 318 =======================================
 319
 320 +-------+------------+--------------------+----------------------------------------------+
 321 | tpred | Mnemonic   | Predicate Register | Meaning                                      |
 322 +=======+============+====================+==============================================+
 323 | 000   | *None*     | *None*             | The instruction is unpredicated              |
 324 +-------+------------+--------------------+----------------------------------------------+
 325 | 001   | x9,off     | src=x9, dest=none  | src[0..i] uses x9[i], dest unpredicated      |
 326 +-------+------------+                    +----------------------------------------------+
 327 | 010   | off,x10    | src=none, dest=x10 | dest[0..i] uses x10[i], src unpredicated     |
 328 +-------+------------+                    +----------------------------------------------+
 329 | 011   | x9,10      | src=x9, dest=x10   | src[0..i] uses x9[i], dest[0..i] uses x10[i] |
 330 +-------+------------+--------------------+----------------------------------------------+
 331 | 100   | *None*     | *RESERVED*         | Instruction is unpredicated (TBD)            |
 332 +-------+------------+--------------------+----------------------------------------------+
 333 | 101   | !x9,off    | src=!x9, dest=none |                                              |
 334 +-------+------------+                    +----------------------------------------------+
 335 | 110   | off,!x10   | src=none, dest=!x10|                                              |
 336 +-------+------------+                    +----------------------------------------------+
 337 | 111   | !x9,!x10   | src=!x9, dest=!x10 |                                              |
 338 +-------+------------+--------------------+----------------------------------------------+
 339
 340 Integer Element Type (itype) Field Encoding
 341 ===========================================
 342
 343 +------------+-------+--------------+--------------+-----------------+-------------------+
 344 | Signedness | itype | Element Type | Mnemonic in  | Mnemonic in FP  | Meaning (INT may  |
 345 | [#sgn_def]_|       |              | Integer      | Instructions    | be un/signed, FP  |
 346 | [#sgn_def]_|       |              | Instructions | (such as fmv.x) | just re-sized     |
 347 +============+=======+==============+==============+=================+===================+
 348 | Unsigned   | 01    | u8           | BU           | BU              | Unsigned 8-bit    |
 349 |            +-------+--------------+--------------+-----------------+-------------------+
 350 |            | 10    | u16          | HU           | HU              | Unsigned 16-bit   |
 351 |            +-------+--------------+--------------+-----------------+-------------------+
 352 |            | 11    | u32          | WU           | WU              | Unsigned 32-bit   |
 353 |            +-------+--------------+--------------+-----------------+-------------------+
 354 |            | 00    | uXLEN        | WU/DU/QU     | WU/LU/TU        | Unsigned XLEN-bit |
 355 +------------+-------+--------------+--------------+-----------------+-------------------+
 356 | Signed     | 01    | i8           | BS           | BS              | Signed 8-bit      |
 357 |            +-------+--------------+--------------+-----------------+-------------------+
 358 |            | 10    | i16          | HS           | HS              | Signed 16-bit     |
 359 |            +-------+--------------+--------------+-----------------+-------------------+
 360 |            | 11    | i32          | W            | W               | Signed 32-bit     |
 361 |            +-------+--------------+--------------+-----------------+-------------------+
 362 |            | 00    | iXLEN        | W/D/Q        | W/L/T           | Signed XLEN-bit   |
 363 +------------+-------+--------------+--------------+-----------------+-------------------+
 364
 365 .. [#sgn_def] Signedness is defined in `Signedness Decision Procedure`_
 366
 367 Note: vector mode is effectively a type-cast of the register file
 368 as if it was a sequential array being typecast to typedef itype[]
 369 (c syntax).  The starting point of the "typecast" is the vector
 370 register rs#/rd.
 371
 372 Example: if itype=0b10 (u16), and rd is set to "vector", and
 373 VL is set to 4, the 64-bit register at rd is subdivided into
 374 *FOUR* 16-bit destination elements.  It is *NOT* four
 375 separate 64-bit destination registers (rd+0, rd+1, rd+2, rd+3)
 376 that are sign-extended from the source width size out to 64-bit,
 377 because that is itype=0b00 (uXLEN).
 378
 379 Signedness Decision Procedure
 380 =============================
 381
 382 1. If the opcode field is either OP or OP-IMM, then
 383     1. Signedness is Unsigned.
 384 2. If the opcode field is either OP-32 or OP-IMM-32, then
 385     1. Signedness is Signed.
 386 3. If Signedness is encoded in a field of the base instruction, [#sign_enc]_ then
 387     1. Signedness uses the encoded value.
 388 4. Otherwise,
 389     1. Signedness is Unsigned.
 390
 391 .. [#sign_enc] Like in fcvt.d.l[u], but unlike in fmv.x.w, since there is no
 392                fmv.x.wu
 393
 394 Vector Type and Predication 5-bit (vtp5) Field Encoding
 395 =======================================================
 396
 397 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 398 different value for every occurrence.
 399
 400 +-------+-----------+-----------+
 401 | vtp5  | pred      | svlen     |
 402 +=======+===========+===========+
 403 | 1XXXX | vtp5[4:2] | vtp5[1:0] |
 404 +-------+           |           |
 405 | 01XXX |           |           |
 406 +-------+           |           |
 407 | 000XX |           |           |
 408 +-------+-----------+-----------+
 409 | 001XX | *Reserved*            |
 410 +-------+-----------------------+
 411
 412 Vector Integer Type and Predication 6-bit (vitp6) Field Encoding
 413 ================================================================
 414
 415 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 416 different value for every occurrence.
 417
 418 +--------+------------+---------+------------+------------+
 419 | vitp6  | itype      | pred[2] | pred[0:1]  | svlen      |
 420 +========+============+=========+============+============+
 421 | XX1XXX | vitp6[5:4] | 0       | vitp6[3:2] | vitp6[1:0] |
 422 +--------+            |         |            |            |
 423 | XX00XX |            |         |            |            |
 424 +--------+------------+---------+------------+------------+
 425 | XX01XX | *Reserved*                                     |
 426 +--------+------------------------------------------------+
 427
 428 vitp7 field: only tpred=
 429
 430 +---------+------------+----------+-------------+------------+
 431 | vitp7   | itype      | tpred[2] | tpred[0:1]  | svlen      |
 432 +=========+============+==========+=============+============+
 433 | XXXXXXX | vitp7[5:4] | vitp7[6] | vitp7[3:2]  | vitp7[1:0] |
 434 +---------+------------+----------+-------------+------------+
 435
 436 48-bit Instruction Encoding Decision Procedure
 437 ==============================================
 438
 439 In the following decision procedure, *Reserved* means that there is not yet a
 440 defined 48-bit instruction encoding for the base instruction.
 441
 442 1. If the base instruction is a load instruction, then
 443     a. If the base instruction is an I-type instruction, then
 444         1. The encoding is P48-LD-type.
 445     b. Otherwise
 446         1. The encoding is *Reserved*.
 447 2. If the base instruction is a store instruction, then
 448     a. If the base instruction is an S-type instruction, then
 449         1. The encoding is P48-ST-type.
 450     b. Otherwise
 451         1. The encoding is *Reserved*.
 452 3. If the base instruction is a SYSTEM instruction, then
 453     a. The encoding is *Reserved*.
 454 4. If the base instruction is an integer instruction, then
 455     a. If the base instruction is an R-type instruction, then
 456         1. The encoding is P48-R-type.
 457     b. If the base instruction is an I-type instruction, then
 458         1. The encoding is P48-I-type.
 459     c. If the base instruction is an S-type instruction, then
 460         1. The encoding is *Reserved*.
 461     d. If the base instruction is an B-type instruction, then
 462         1. The encoding is *Reserved*.
 463     e. If the base instruction is an U-type instruction, then
 464         1. The encoding is P48-U-type.
 465     f. If the base instruction is an J-type instruction, then
 466         1. The encoding is *Reserved*.
 467     g. Otherwise
 468         1. The encoding is *Reserved*.
 469 5. If the base instruction is a floating-point instruction, then
 470     a. If the base instruction is an R-type instruction, then
 471         1. The encoding is P48-FR-type.
 472     b. If the base instruction is an I-type instruction, then
 473         1. The encoding is P48-FI-type.
 474     c. If the base instruction is an S-type instruction, then
 475         1. The encoding is *Reserved*.
 476     d. If the base instruction is an B-type instruction, then
 477         1. The encoding is *Reserved*.
 478     e. If the base instruction is an U-type instruction, then
 479         1. The encoding is *Reserved*.
 480     f. If the base instruction is an J-type instruction, then
 481         1. The encoding is *Reserved*.
 482     g. If the base instruction is an R4-type instruction, then
 483         1. The encoding is P48-FR4-type.
 484     h. Otherwise
 485         1. The encoding is *Reserved*.
 486 6. Otherwise
 487     a. The encoding is *Reserved*.
 488
 489 CSR Registers
 490 =============
 491
 492 +--------+-----------------+---------------------------------------------------+
 493 | Name   | Legal Values    | Meaning                                           |
 494 +========+=================+===================================================+
 495 | VL     | 0 <= VL <= XLEN | Vector Length. The number of sub-vectors operated |
 496 |        |                 | on by vector instructions.                        |
 497 +--------+-----------------+---------------------------------------------------+
 498 | Vstart | 0 <= VL < XLEN  | The sub-vector index to start execution at.       |
 499 |        |                 | Successful completion of all elements in a vector |
 500 |        |                 | instruction sets Vstart to 0. Set to the index of |
 501 |        |                 | the failing sub-vector when a vector instruction  |
 502 |        |                 | traps.  Used to resume execution of vector        |
 503 |        |                 | instructions after a trap. Is *NOT* "slow"        |
 504 +--------+-----------------+---------------------------------------------------+
 505
 506 SetVL
 507 =====
 508
 509 setvl rd, rs1, imm
 510
 511 This is done the same as Standard SV.
 512 There is alsO a MVL CSR.  CSRRW and CSRRWI operate in the same way as in SV. See Specification_.
 513
 514
 515 Additional Instructions
 516 =======================
 517
 518 Add instructions to convert between integer types.
 519
 520 Add instructions to `swizzle`_ elements in sub-vectors. Note that the sub-vector
 521 lengths of the source and destination won't necessarily match.
 522
 523 .. _swizzle: https://www.khronos.org/opengl/wiki/Data_Type_(GLSL)#Swizzling
 524
 525 Add instructions to transpose (2-4)x(2-4) element matrices.
 526
 527 Add instructions to insert or extract a sub-vector from a vector, with the index
 528 allowed to be both immediate and from a register (*immediate can be covered partly
 529 by twin-predication, register cannot: requires MV.X aka VSELECT*)
 530
 531 Add a register gather instruction (aka MV.X)
 532
 533 # Open questions <a name="questions"></a>
 534
 535 What is SUBVL and how does it work
 536
 537 --
 538
 539 SVorig goes to a lot of effort to make VL 1<= MAXVL and MAXVL 1..64 where both CSRs may be stored internally in only 6 bits.
 540
 541 Thus, CSRRWI can reach 1..32 for VL and MAXVL.
 542
 543 In addition, setting a hardware loop to zero turning instructions into NOPs, um, just branch over them, to start the first loop at the end, on the test for loop variable being zero, a la c "while do" instead of "do while".
 544
 545 Or, does it not matter that VL only goes up to 31 on a CSRRWI, and that it only goes to a max of 63 rather than 64?
 546
 547 --
 548
 549 Should these questions be moved to Discussion subpage
 550
 551 --
 552
 553 Is MV.X good enough a substitute for swizzle?
 554
 555 --
 556
 557 Is vectorised srcbase ok as a gather scatter and ok substitute for register stride? 5 dependency registers (reg stride being the 5th) is quite scary
 558
 559 --
 560
 561 Why are integer conversion instructions needed, when the main SV spec covers them by allowing elwidth to be set on both src and dest regs?
 562
 563 --
 564
 565 Why are the SETVL rules so complex? What is the reason, how are loops carried out?
 566
 567 --
 568
 569 With SUBVL (sub vector len) being both a CSR and also part of the 48/64 bit opcode, how does that work?
 570
 571 --
 572
 573 What are the interaction rules when a 48/64 prefix opcode has a rd/rs that already has a Vector Context for either predication or a register?
 574
 575 It would perhaps make sense (and for svlen as well) to make 48/64 isolated and unaffected by VLIW context, with the exception of VL/MVL.
 576
 577 MVL and VL should be modifiable by 64 bit prefix as they are global in nature.
 578