simple_v_extension/sv_prefix_proposal.rst

   1 SimpleV Prefix (SVprefix) Proposal v0.3
   2 =======================================
   3
   4 This proposal is designed to be able to operate without SVorig, but not to
   5 require the absence of SVorig See Specification_.
   6
   7 If required, the STATE, VL, MVL and SUBVL CSRs all operate according to the main specification: hypothetically an implementor could choose not to support setting of VL, MVL or SUBVL (only allowing them to be set to a value of 1). STATE would then not be required either.
   8
   9 .. _Specification: http://libre-riscv.org/simple_v_extension/specification/
  10
  11 .. contents::
  12
  13 Conventions
  14 ===========
  15
  16 Conventions used in this document:
  17 - Bits are numbered starting from 0 at the LSB, so bit 3 is 1 in the integer 8.
  18 - Bit ranges are inclusive on both ends, so 5:3 means bits 5, 4, and 3.
  19
  20 Operations work on variable-length vectors of sub-vectors, where each sub-vector
  21 has a length *svlen*, and an element type *etype*. When the vectors are stored
  22 in registers, all elements are packed so that there is no padding in-between
  23 elements of the same vector. The number of bytes in a sub-vector, *svsz*, is the
  24 product of *svlen* and the element size in bytes.
  25
  26 Half-Precision Floating Point (FP16)
  27 ====================================
  28 If the F extension is supported, SVprefix adds support for FP16 in the
  29 base FP instructions by using 10 (H) in the floating-point format field *fmt*
  30 and using 001 (H) in the floating-point load/store *width* field.
  31
  32 Compressed Instructions
  33 =======================
  34 This proposal doesn't include any prefixed RVC instructions, instead, it will
  35 include 32-bit instructions that are compressed forms of SVprefix 48-bit
  36 instructions, in the same manner that RVC instructions are compressed forms of
  37 RVI instructions. The compressed instructions will be defined later by
  38 considering which 48-bit instructions are the most common.
  39
  40 48-bit Prefixed Instructions
  41 ============================
  42 All 48-bit prefixed instructions contain a 32-bit "base" instruction as the
  43 last 4 bytes. Since all 32-bit instructions have bits 1:0 set to 11, those bits
  44 are reused for additional encoding space in the 48-bit instructions.
  45
  46 64-bit Prefixed Instructions
  47 ============================
  48
  49 The 48 bit format is further extended with the full 128-bit range on all source
  50 and destination registers, and the option to set both VL and MVL is provided.
  51
  52 48-bit Instruction Encodings
  53 ============================
  54
  55 In the following table, *Reserved* entries must be zero.  RV32 equivalent encodings
  56 included for side-by-side comparison (and listed below, separately).
  57
  58 First, bits 17:0:
  59
  60 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  61 | Encoding      | 17     | 16         | 15         | 14  | 13         | 12          | 11:7 | 6          | 5:0    |
  62 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  63 | P48-LD-type   | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  64 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  65 | P48-ST-type   |vitp7[6]| rs1[5]     | rs2[5]     | vs2 | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  66 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  67 | P48-R-type    | rd[5]  | rs1[5]     | rs2[5]     | vs2 | vs1        | vitp6              | *Reserved* | 011111 |
  68 +---------------+--------+------------+------------+-----+------------+--------------------+------------+--------+
  69 | P48-I-type    | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  70 +---------------+--------+------------+------------+-----+------------+--------------------+------------+--------+
  71 | P48-U-type    | rd[5]  | *Reserved* | *Reserved* | vd  | *Reserved* | vitp6              | *Reserved* | 011111 |
  72 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  73 | P48-FR-type   | rd[5]  | rs1[5]     | rs2[5]     | vs2 | vs1        | *Reserved*  | vtp5 | *Reserved* | 011111 |
  74 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  75 | P48-FI-type   | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  76 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  77 | P48-FR4-type  | rd[5]  | rs1[5]     | rs2[5]     | vs2 | rs3[5]     | vs3 [#fr4]_ | vtp5 | *Reserved* | 011111 |
  78 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  79
  80 .. [#fr4] Only vs2 and vs3 are included in the P48-FR4-type encoding because
  81           there is not enough space for vs1 as well, and because it is more
  82           useful to have a scalar argument for each of the multiplication and
  83           addition portions of fmadd than to have two scalars on the
  84           multiplication portion.
  85
  86 Table showing correspondance between P48-*-type and RV32-*-type.  These are
  87 bits 47:18 (RV32 shifted up by 16 bits):
  88
  89 +---------------+---------------+
  90 | Encoding      | 47:18         |
  91 +---------------+---------------+
  92 | RV32 Encoding | 31:2          |
  93 +---------------+---------------+
  94 | P48-LD-type   | RV32-I-type   |
  95 +---------------+---------------+
  96 | P48-ST-type   | RV32-S-Type   |
  97 +---------------+---------------+
  98 | P48-R-type    | RV32-R-Type   |
  99 +---------------+---------------+
 100 | P48-I-type    | RV32-I-Type   |
 101 +---------------+---------------+
 102 | P48-U-type    | RV32-U-Type   |
 103 +---------------+---------------+
 104 | P48-FR-type   | RV32-FR-Type  |
 105 +---------------+---------------+
 106 | P48-FI-type   | RV32-I-Type   |
 107 +---------------+---------------+
 108 | P48-FR4-type  | RV32-FR-type  |
 109 +---------------+---------------+
 110
 111 Table showing Standard RV32 encodings:
 112
 113 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 114 | Encoding      | 31:27       | 26:25 | 24:20    | 19:15    | 14:12  | 11:7     | 6:2    | 1      | 0          |
 115 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 116 | RV32-R-type   +    funct7           + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 117 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 118 | RV32-S-type   + imm[11:5]           + rs2[4:0] + rs1[4:0] + funct3 | imm[4:0] + opcode + 1      + 1          |
 119 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 120 | RV32-I-type   + imm[11:0]                      + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 121 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 122 | RV32-U-type   + imm[31:12]                                         | rd[4:0]  + opcode + 1      + 1          |
 123 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 124 | RV32-FR4-type + rs3[4:0]    + fmt   + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 125 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 126 | RV32-FR-type  + funct5      + fmt   + rs2[4:0] + rs1[4:0] + rm     | rd[4:0]  + opcode + 1      + 1          |
 127 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 128
 129 64-bit Instruction Encodings
 130 ============================
 131
 132 Where in the 48 bit format the prefix is "0b0011111" in bits 0 to 6, this is
 133 now set to "0b0111111".
 134
 135 +---------------+---------------+--------------+-----------+
 136 | 63:48         | 47:18         | 17:7         | 6:0       |
 137 +---------------+---------------+--------------+-----------+
 138 | 64 bit prefix | RV32[31:3]    | P48[17:7]    | 0b0111111 |
 139 +---------------+---------------+--------------+-----------+
 140
 141 * The 64 bit prefix format is below
 142 * Bits 18 to 47 contain bits 3 to 31 of a standard RV32 format
 143 * Bits 7 to 17 contain bits 7 through 17 of the P48 format
 144 * Bits 0 to 6 contain the standard RV 64-bit prefix 0b0111111
 145
 146 64 bit prefix format:
 147
 148 +--------------+-------+--------+--------+--------+--------+
 149 | Encoding     | 63    | 62     | 61     | 60     | 59:48  |
 150 +--------------+-------+--------+--------+--------+--------+
 151 | P64-LD-type  | rd[6] | rs1[6] |        |        | VLtyp  |
 152 +--------------+-------+--------+--------+--------+--------+
 153 | P64-ST-type  |       | rs1[6] | rs2[6] |        | VLtyp  |
 154 +--------------+-------+--------+--------+--------+--------+
 155 | P64-R-type   | rd[6] | rs1[6] | rs2[6] |        | VLtyp  |
 156 +--------------+-------+--------+--------+--------+--------+
 157 | P64-I-type   | rd[6] | rs1[6] |        |        | VLtyp  |
 158 +--------------+-------+--------+--------+--------+--------+
 159 | P64-U-type   | rd[6] |        |        |        | VLtyp  |
 160 +--------------+-------+--------+--------+--------+--------+
 161 | P64-FR-type  |       | rs1[6] | rs2[6] |        | VLtyp  |
 162 +--------------+-------+--------+--------+--------+--------+
 163 | P64-FI-type  | rd[6] | rs1[6] | rs2[6] |        | VLtyp  |
 164 +--------------+-------+--------+--------+--------+--------+
 165 | P64-FR4-type | rd[6] | rs1[6] | rs2[6] | rs3[6] | VLtyp  |
 166 +--------------+-------+--------+--------+--------+--------+
 167
 168 The extra bit for src and dest registers provides the full range of
 169 up to 128 registers, when combined with the extra bit from the 48 bit
 170 prefix as well.  VLtyp encodes how (whether) to set VL and MAXVL.
 171
 172 VLtyp field encoding
 173 ====================
 174
 175 +-----------+-------------+--------------+----------+----------------------+
 176 | VLtyp[11] | VLtyp[10:6] | VLtyp[5:1]   | VLtyp[0] | comment              |
 177 +-----------+-------------+--------------+----------+----------------------+
 178 | 0         |  000000     | 00000        |  0       | no change to VL/MVL  |
 179 +-----------+-------------+--------------+----------+----------------------+
 180 | 0         |  VLdest     | VLEN         |  vlt     | VL imm/reg mode (vlt)|
 181 +-----------+-------------+--------------+----------+----------------------+
 182 | 1         |  VLdest     | MVL+VL-immed | 0        | MVL+VL immed mode    |
 183 +-----------+-------------+--------------+----------+----------------------+
 184 | 1         |  VLdest     |  MVL-immed   | 1        | MVL immed mode       |
 185 +-----------+-------------+--------------+----------+----------------------+
 186
 187 Note: when VLtyp is all zeros, neither VL nor MVL are changed.
 188
 189 Just as in the VLIW format, when bit 11 of VLtyp is zero:
 190
 191 * if vlt is zero, bits 1 to 5 specify the VLEN as a 5 bit immediate
 192   (offset by 1: 0b00000 represents VL=1, 0b00001 represents VL=2 etc.)
 193 * if vlt is 1, bits 1 to 5 specify the scalar (RV standard) register
 194   from which VL is set.  x0 is not permitted
 195 * VL goes into the scalar register VLdest (if VLdest is not x0)
 196
 197 When bit 11 of VLtype is 1:
 198
 199 * if VLtyp[0] is zero, both MAXVL and VL are set to (imm+1).  The same
 200   value goes into the scalar register VLdest (if VLdest is not x0)
 201 * if VLtyp[0] is 1, MAXVL is set to (imm+1).
 202   VL will be truncated to within the new range (if VL was greater
 203   than the new MAXVL).  The new VL goes into the scalar register VLdest
 204   (if VLdest is not x0).
 205
 206 This gives the option to set up VL in a "loop mode" (VLtype[11]=0) or
 207 in a "one-off" mode (VLtype[11]=1) which sets both MVL and VL to the
 208 same immediate value.  This may be most useful for one-off Vectorised
 209 operations such as LOAD-MULTI / STORE-MULTI, for saving and restoration
 210 of large batches of registers in context-switches or function calls.
 211
 212 vs#/vd Fields' Encoding
 213 =======================
 214
 215 +--------+----------+----------------------------------------------------------+
 216 | vs#/vd | Mnemonic | Meaning                                                  |
 217 +========+==========+==========================================================+
 218 | 0      | S        | the rs#/rd field specifies a scalar (single sub-vector); |
 219 |        |          | the rs#/rd field is zero-extended to get the actual      |
 220 |        |          | 7-bit register number                                    |
 221 +--------+----------+----------------------------------------------------------+
 222 | 1      | V        | the rs#/rd field specifies a vector; the rs#/rd field is |
 223 |        |          | decoded using the `Vector Register Number Encoding`_ to  |
 224 |        |          | get the actual 7-bit register number                     |
 225 +--------+----------+----------------------------------------------------------+
 226
 227 If a vs#/vd field is not present, it is as if it was present with a value that
 228 is the bitwise-or of all present vs#/vd fields.
 229
 230 * scalar register numbers do NOT increment when allocated in the
 231   hardware for-loop.  the same scalar register number is handed
 232   to every ALU.
 233
 234 * vector register numbers *DO* increase when allocated in the
 235   hardware for-loop.  sequentially-increasing register data
 236   is handed to sequential ALUs.
 237
 238 Vector Register Number Encoding
 239 ===============================
 240
 241 For the 48 bit format, when vs#/vd is 1, the actual 7-bit register number is derived from the
 242 corresponding 6-bit rs#/rd field:
 243
 244 +---------------------------------+
 245 | Actual 7-bit register number    |
 246 +===========+=============+=======+
 247 | Bit 6     | Bits 5:1    | Bit 0 |
 248 +-----------+-------------+-------+
 249 | rs#/rd[0] | rs#/rd[5:1] | 0     |
 250 +-----------+-------------+-------+
 251
 252 For the 64 bit format, the 7 bit register is constructed from the 7 bit fields: bits 0 to 4 from the 32 bit RV Standard format, bit 5 from the 48 bit prefix and bit 6 from the 64 bit prefix.  Thus in the 64 bit format the full range of up to 128 registers is directly available. This for both when either scalar or vector mode is set.
 253
 254 Load/Store Kind (lsk) Field Encoding
 255 ====================================
 256
 257 +--------+-----+--------------------------------------------------------------------------------+
 258 | vd/vs2 | vs1 | Meaning                                                                        |
 259 +========+=====+================================================================================+
 260 | 0      | 0   | srcbase is scalar, LD/ST is pure scalar.                                       |
 261 +--------+-----+--------------------------------------------------------------------------------+
 262 | 1      | 0   | srcbase is scalar, LD/ST is unit strided                                       |
 263 +--------+-----+--------------------------------------------------------------------------------+
 264 | 0      | 1   | srcbase is a vector (gather/scatter aka array of srcbases). VSPLAT and VSELECT |
 265 +--------+-----+--------------------------------------------------------------------------------+
 266 | 1      | 1   | srcbase is a vector, LD/ST is a full vector LD/ST.                             |
 267 +--------+-----+--------------------------------------------------------------------------------+
 268
 269 Notes:
 270
 271 * A register strided LD/ST would require *5* registers. srcbase, vd/vs2, predicate 1, predicate 2 and the stride register.
 272 * Complex strides may all be done with a general purpose vector of srcbases.
 273 * Twin predication may be used even when vd/vs1 is a scalar, to give VSPLAT and VSELECT, because the hardware loop ends on the first occurrence of a 1 in the predicate when a predicate is applied to a scalar.
 274 * Full vectorised gather/scatter is enabled when both registers are marked as vectorised, however unlike e.g Intel AVX512, twin predication can be applied.
 275
 276 Open question: RVV overloads the width field of LOAD-FP/STORE-FP using the bit 2 to indicate additional interpretation of the 11 bit immediate. Should this be considered?
 277
 278
 279 Sub-Vector Length (svlen) Field Encoding
 280 =======================================================
 281
 282 Bitwidth, from VL's perspective, is a multiple of the elwidth times svlen.  So within each loop of VL there are svlen sub-elements of elwidth in size, just like in a SIMD architecture. When svlen is set to 0b00 (indicating svlen=1) no such SIMD-like behaviour exists and the subvectoring is disabled.
 283
 284 Predicate bits do not apply to the individual sub-vector elements, they apply to the entire subvector group. This saves instructions on setup of the predicate.
 285
 286 +----------------+-------+
 287 | svlen Encoding | Value |
 288 +================+=======+
 289 | 00             | 1     |
 290 +----------------+-------+
 291 | 01             | 2     |
 292 +----------------+-------+
 293 | 10             | 3     |
 294 +----------------+-------+
 295 | 11             | 4     |
 296 +----------------+-------+
 297
 298 TODO : resolve interactions when SV VLIW Mode is active, as SVLEN is also a CSR.
 299
 300 Predication (pred) Field Encoding
 301 =================================
 302
 303 +------+------------+--------------------+----------------------------------------+
 304 | pred | Mnemonic   | Predicate Register | Meaning                                |
 305 +======+============+====================+========================================+
 306 | 000  | *None*     | *None*             | The instruction is unpredicated        |
 307 +------+------------+--------------------+----------------------------------------+
 308 | 001  | *Reserved* | *Reserved*         |                                        |
 309 +------+------------+--------------------+----------------------------------------+
 310 | 010  | !x9        | x9 (s1)            | execute vector op[0..i] on x9[i] == 0  |
 311 +------+------------+                    +----------------------------------------+
 312 | 011  | x9         |                    | execute vector op[0..i] on x9[i] == 1  |
 313 +------+------------+--------------------+----------------------------------------+
 314 | 100  | !x10       | x10 (a0)           | execute vector op[0..i] on x10[i] == 0 |
 315 +------+------------+                    +----------------------------------------+
 316 | 101  | x10        |                    | execute vector op[0..i] on x10[i] == 1 |
 317 +------+------------+--------------------+----------------------------------------+
 318 | 110  | !x11       | x11 (a1)           | execute vector op[0..i] on x11[i] == 0 |
 319 +------+------------+                    +----------------------------------------+
 320 | 111  | x11        |                    | execute vector op[0..i] on x11[i] == 1 |
 321 +------+------------+--------------------+----------------------------------------+
 322
 323 Twin-predication (tpred) Field Encoding
 324 =======================================
 325
 326 +-------+------------+--------------------+----------------------------------------------+
 327 | tpred | Mnemonic   | Predicate Register | Meaning                                      |
 328 +=======+============+====================+==============================================+
 329 | 000   | *None*     | *None*             | The instruction is unpredicated              |
 330 +-------+------------+--------------------+----------------------------------------------+
 331 | 001   | x9,off     | src=x9, dest=none  | src[0..i] uses x9[i], dest unpredicated      |
 332 +-------+------------+                    +----------------------------------------------+
 333 | 010   | off,x10    | src=none, dest=x10 | dest[0..i] uses x10[i], src unpredicated     |
 334 +-------+------------+                    +----------------------------------------------+
 335 | 011   | x9,10      | src=x9, dest=x10   | src[0..i] uses x9[i], dest[0..i] uses x10[i] |
 336 +-------+------------+--------------------+----------------------------------------------+
 337 | 100   | *None*     | *RESERVED*         | Instruction is unpredicated (TBD)            |
 338 +-------+------------+--------------------+----------------------------------------------+
 339 | 101   | !x9,off    | src=!x9, dest=none |                                              |
 340 +-------+------------+                    +----------------------------------------------+
 341 | 110   | off,!x10   | src=none, dest=!x10|                                              |
 342 +-------+------------+                    +----------------------------------------------+
 343 | 111   | !x9,!x10   | src=!x9, dest=!x10 |                                              |
 344 +-------+------------+--------------------+----------------------------------------------+
 345
 346 Integer Element Type (itype) Field Encoding
 347 ===========================================
 348
 349 +------------+-------+--------------+--------------+-----------------+-------------------+
 350 | Signedness | itype | Element Type | Mnemonic in  | Mnemonic in FP  | Meaning (INT may  |
 351 | [#sgn_def]_|       |              | Integer      | Instructions    | be un/signed, FP  |
 352 | [#sgn_def]_|       |              | Instructions | (such as fmv.x) | just re-sized     |
 353 +============+=======+==============+==============+=================+===================+
 354 | Unsigned   | 01    | u8           | BU           | BU              | Unsigned 8-bit    |
 355 |            +-------+--------------+--------------+-----------------+-------------------+
 356 |            | 10    | u16          | HU           | HU              | Unsigned 16-bit   |
 357 |            +-------+--------------+--------------+-----------------+-------------------+
 358 |            | 11    | u32          | WU           | WU              | Unsigned 32-bit   |
 359 |            +-------+--------------+--------------+-----------------+-------------------+
 360 |            | 00    | uXLEN        | WU/DU/QU     | WU/LU/TU        | Unsigned XLEN-bit |
 361 +------------+-------+--------------+--------------+-----------------+-------------------+
 362 | Signed     | 01    | i8           | BS           | BS              | Signed 8-bit      |
 363 |            +-------+--------------+--------------+-----------------+-------------------+
 364 |            | 10    | i16          | HS           | HS              | Signed 16-bit     |
 365 |            +-------+--------------+--------------+-----------------+-------------------+
 366 |            | 11    | i32          | W            | W               | Signed 32-bit     |
 367 |            +-------+--------------+--------------+-----------------+-------------------+
 368 |            | 00    | iXLEN        | W/D/Q        | W/L/T           | Signed XLEN-bit   |
 369 +------------+-------+--------------+--------------+-----------------+-------------------+
 370
 371 .. [#sgn_def] Signedness is defined in `Signedness Decision Procedure`_
 372
 373 Note: vector mode is effectively a type-cast of the register file
 374 as if it was a sequential array being typecast to typedef itype[]
 375 (c syntax).  The starting point of the "typecast" is the vector
 376 register rs#/rd.
 377
 378 Example: if itype=0b10 (u16), and rd is set to "vector", and
 379 VL is set to 4, the 64-bit register at rd is subdivided into
 380 *FOUR* 16-bit destination elements.  It is *NOT* four
 381 separate 64-bit destination registers (rd+0, rd+1, rd+2, rd+3)
 382 that are sign-extended from the source width size out to 64-bit,
 383 because that is itype=0b00 (uXLEN).
 384
 385 Note also: changing elwidth creates packed elements that, depending on VL, may create vectors that do not fit perfectly onto XLEM sized rehistry file boundaries. This does  NOT result in the destruction of the MSBs of the last register written to at the end of a VL loop. More details on how to handle this are described in the main Specification_.
 386
 387 Signedness Decision Procedure
 388 =============================
 389
 390 1. If the opcode field is either OP or OP-IMM, then
 391     1. Signedness is Unsigned.
 392 2. If the opcode field is either OP-32 or OP-IMM-32, then
 393     1. Signedness is Signed.
 394 3. If Signedness is encoded in a field of the base instruction, [#sign_enc]_ then
 395     1. Signedness uses the encoded value.
 396 4. Otherwise,
 397     1. Signedness is Unsigned.
 398
 399 .. [#sign_enc] Like in fcvt.d.l[u], but unlike in fmv.x.w, since there is no
 400                fmv.x.wu
 401
 402 Vector Type and Predication 5-bit (vtp5) Field Encoding
 403 =======================================================
 404
 405 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 406 different value for every occurrence.
 407
 408 +-------+-----------+-----------+
 409 | vtp5  | pred      | svlen     |
 410 +=======+===========+===========+
 411 | 1XXXX | vtp5[4:2] | vtp5[1:0] |
 412 +-------+           |           |
 413 | 01XXX |           |           |
 414 +-------+           |           |
 415 | 000XX |           |           |
 416 +-------+-----------+-----------+
 417 | 001XX | *Reserved*            |
 418 +-------+-----------------------+
 419
 420 Vector Integer Type and Predication 6-bit (vitp6) Field Encoding
 421 ================================================================
 422
 423 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 424 different value for every occurrence.
 425
 426 +--------+------------+---------+------------+------------+
 427 | vitp6  | itype      | pred[2] | pred[0:1]  | svlen      |
 428 +========+============+=========+============+============+
 429 | XX1XXX | vitp6[5:4] | 0       | vitp6[3:2] | vitp6[1:0] |
 430 +--------+            |         |            |            |
 431 | XX00XX |            |         |            |            |
 432 +--------+------------+---------+------------+------------+
 433 | XX01XX | *Reserved*                                     |
 434 +--------+------------------------------------------------+
 435
 436 vitp7 field: only tpred=
 437
 438 +---------+------------+----------+-------------+------------+
 439 | vitp7   | itype      | tpred[2] | tpred[0:1]  | svlen      |
 440 +=========+============+==========+=============+============+
 441 | XXXXXXX | vitp7[5:4] | vitp7[6] | vitp7[3:2]  | vitp7[1:0] |
 442 +---------+------------+----------+-------------+------------+
 443
 444 48-bit Instruction Encoding Decision Procedure
 445 ==============================================
 446
 447 In the following decision procedure, *Reserved* means that there is not yet a
 448 defined 48-bit instruction encoding for the base instruction.
 449
 450 1. If the base instruction is a load instruction, then
 451     a. If the base instruction is an I-type instruction, then
 452         1. The encoding is P48-LD-type.
 453     b. Otherwise
 454         1. The encoding is *Reserved*.
 455 2. If the base instruction is a store instruction, then
 456     a. If the base instruction is an S-type instruction, then
 457         1. The encoding is P48-ST-type.
 458     b. Otherwise
 459         1. The encoding is *Reserved*.
 460 3. If the base instruction is a SYSTEM instruction, then
 461     a. The encoding is *Reserved*.
 462 4. If the base instruction is an integer instruction, then
 463     a. If the base instruction is an R-type instruction, then
 464         1. The encoding is P48-R-type.
 465     b. If the base instruction is an I-type instruction, then
 466         1. The encoding is P48-I-type.
 467     c. If the base instruction is an S-type instruction, then
 468         1. The encoding is *Reserved*.
 469     d. If the base instruction is an B-type instruction, then
 470         1. The encoding is *Reserved*.
 471     e. If the base instruction is an U-type instruction, then
 472         1. The encoding is P48-U-type.
 473     f. If the base instruction is an J-type instruction, then
 474         1. The encoding is *Reserved*.
 475     g. Otherwise
 476         1. The encoding is *Reserved*.
 477 5. If the base instruction is a floating-point instruction, then
 478     a. If the base instruction is an R-type instruction, then
 479         1. The encoding is P48-FR-type.
 480     b. If the base instruction is an I-type instruction, then
 481         1. The encoding is P48-FI-type.
 482     c. If the base instruction is an S-type instruction, then
 483         1. The encoding is *Reserved*.
 484     d. If the base instruction is an B-type instruction, then
 485         1. The encoding is *Reserved*.
 486     e. If the base instruction is an U-type instruction, then
 487         1. The encoding is *Reserved*.
 488     f. If the base instruction is an J-type instruction, then
 489         1. The encoding is *Reserved*.
 490     g. If the base instruction is an R4-type instruction, then
 491         1. The encoding is P48-FR4-type.
 492     h. Otherwise
 493         1. The encoding is *Reserved*.
 494 6. Otherwise
 495     a. The encoding is *Reserved*.
 496
 497 CSR Registers
 498 =============
 499
 500 +--------+-----------------+---------------------------------------------------+
 501 | Name   | Legal Values    | Meaning                                           |
 502 +========+=================+===================================================+
 503 | VL     | 0 <= VL <= XLEN | Vector Length. The number of sub-vectors operated |
 504 |        |                 | on by vector instructions.                        |
 505 +--------+-----------------+---------------------------------------------------+
 506 | Vstart | 0 <= VL < XLEN  | The sub-vector index to start execution at.       |
 507 |        |                 | Successful completion of all elements in a vector |
 508 |        |                 | instruction sets Vstart to 0. Set to the index of |
 509 |        |                 | the failing sub-vector when a vector instruction  |
 510 |        |                 | traps.  Used to resume execution of vector        |
 511 |        |                 | instructions after a trap. Is *NOT* "slow"        |
 512 +--------+-----------------+---------------------------------------------------+
 513
 514 SetVL
 515 =====
 516
 517 setvl rd, rs1, imm
 518
 519 This is done the same as Standard SV.
 520 There is alsO a MVL CSR.  CSRRW and CSRRWI operate in the same way as in SV. See Specification_.
 521
 522
 523 Additional Instructions
 524 =======================
 525
 526 Add instructions to convert between integer types.
 527
 528 Add instructions to `swizzle`_ elements in sub-vectors. Note that the sub-vector
 529 lengths of the source and destination won't necessarily match.
 530
 531 .. _swizzle: https://www.khronos.org/opengl/wiki/Data_Type_(GLSL)#Swizzling
 532
 533 Add instructions to transpose (2-4)x(2-4) element matrices.
 534
 535 Add instructions to insert or extract a sub-vector from a vector, with the index
 536 allowed to be both immediate and from a register (*immediate can be covered partly
 537 by twin-predication, register cannot: requires MV.X aka VSELECT*)
 538
 539 Add a register gather instruction (aka MV.X)
 540
 541 # Open questions <a name="questions"></a>
 542
 543 What is SUBVL and how does it work
 544
 545 --
 546
 547 SVorig goes to a lot of effort to make VL 1<= MAXVL and MAXVL 1..64 where both CSRs may be stored internally in only 6 bits.
 548
 549 Thus, CSRRWI can reach 1..32 for VL and MAXVL.
 550
 551 In addition, setting a hardware loop to zero turning instructions into NOPs, um, just branch over them, to start the first loop at the end, on the test for loop variable being zero, a la c "while do" instead of "do while".
 552
 553 Or, does it not matter that VL only goes up to 31 on a CSRRWI, and that it only goes to a max of 63 rather than 64?
 554
 555 --
 556
 557 Should these questions be moved to Discussion subpage
 558
 559 --
 560
 561 Is MV.X good enough a substitute for swizzle?
 562
 563 --
 564
 565 Is vectorised srcbase ok as a gather scatter and ok substitute for register stride? 5 dependency registers (reg stride being the 5th) is quite scary
 566
 567 --
 568
 569 Why are integer conversion instructions needed, when the main SV spec covers them by allowing elwidth to be set on both src and dest regs?
 570
 571 --
 572
 573 Why are the SETVL rules so complex? What is the reason, how are loops carried out?
 574
 575 --
 576
 577 With SUBVL (sub vector len) being both a CSR and also part of the 48/64 bit opcode, how does that work?
 578
 579 --
 580
 581 What are the interaction rules when a 48/64 prefix opcode has a rd/rs that already has a Vector Context for either predication or a register?
 582
 583 It would perhaps make sense (and for svlen as well) to make 48/64 isolated and unaffected by VLIW context, with the exception of VL/MVL.
 584
 585 MVL and VL should be modifiable by 64 bit prefix as they are global in nature.
 586