simple_v_extension/sv_prefix_proposal.rst

   1 SimpleV Prefix (SVprefix) Proposal v0.3
   2 =======================================
   3
   4 * Copyright (c) Jacob Lifshay, 2019
   5 * Copyright (c) Luke Kenneth Casson Leighton, 2019
   6
   7 This proposal is designed to be able to operate without SVorig, but not to
   8 require the absence of SVorig. See Specification_.
   9
  10 Principle: SVprefix embeds (unmodified) RVC and 32-bit scalar opcodes
  11 into 32, 48 and 64 bit RV formats, to provide Vectorisation context
  12 on a per-instruction basis.
  13
  14 .. _Specification: http://libre-riscv.org/simple_v_extension/specification/
  15
  16 .. contents::
  17
  18 Conventions
  19 ===========
  20
  21 Conventions used in this document:
  22
  23 * Bits are numbered starting from 0 at the LSB, so bit 3 is 1 in the integer 8.
  24 * Bit ranges are inclusive on both ends, so 5:3 means bits 5, 4, and 3.
  25 * Operations work on variable-length vectors of sub-vectors up to *VL*
  26   in length, where each sub-vector has a length *svlen*, and *svlen*
  27   elements of type *etype*.
  28 * The actual total number of elements is therefore *svlen* times *VL*.
  29 * When the vectors are stored in registers, all elements are packed so
  30   that there is no padding in-between elements of the same vector.
  31 * The register file itself is thus best viewed as a byte-level SRAM that
  32   is typecast to an array of *etypes*
  33 * The number of bytes in a sub-vector, *svsz*, is the product of *svlen*
  34   and the element size in bytes.
  35
  36 Options
  37 =======
  38
  39 The following partial / full implementation options are possible:
  40
  41 * SVPrefix augments the main Specification_
  42 * SVPregix operates independently, without the main spec VL (and MVL)
  43   CSRs (in any priv level)
  44 * SVPrefix operates independently, without the main spec SUBVL CSRs
  45   (in any priv level)
  46 * SVPrefix has no support for VL (or MVL) overrides in the 64 bit
  47   instruction format (VLtyp=0 as the only legal permitted value)
  48 * SVPrefix has no support for svlen overrides in either the 48 or 64
  49   bit instruction format either (svlen=0 as the only legal permitted value).
  50
  51 All permutations of the above options are permitted, and the UNIX
  52 platform must raise illegal instruction exceptions on implementations
  53 that do not support each option.  For example, an implementation that
  54 has no support for VLtyp that sees an opcode with a nonzero VLtyp must
  55 raise an illegal instruction exception.
  56
  57 Note that SVPrefix (VLtyp and svlen) and the main spec share (modify) the
  58 STATE CSR. P48 and P64 opcodes must **NOT** set VLtyp or svlen inside
  59 loops that also use VL or SUBVL. Doing so will result in undefined
  60 behaviour, as STATE will be affected by doing so.
  61
  62 However, using VLtyp or svlen in standalone operations, or pushing (and
  63 restoring) the contents of the STATE CSR to the stack, or just storing
  64 its contents in a temporary register whilst executing a sequence of P48
  65 or P64 opcodes, is perfectly fine.
  66
  67 If the main Specification_ CSRs are to be supported, the STATE, VL, MVL
  68 and SUBVL CSRs all operate according to the main specification. Under
  69 the options above, hypothetically an implementor could choose not to
  70 support setting of VL, MVL or SUBVL (only allowing them to be set to
  71 a value of 1). Under such circumstances, where *neither* VL/MVL *nor*
  72 SUBVL are supported, STATE would then not be required either.
  73
  74 If however support for SUBVL is to be provided, storing of the sub-vector
  75 offsets and SUBVL itself (and context switching of the same) in the
  76 STATE CSRs are mandatory.
  77
  78 Likewise if support for VL is to be provided, storing of VL, MVL and the
  79 dest and src offsets (and context switching of the same) in the STATE
  80 CSRs are mandatory.
  81
  82
  83 Half-Precision Floating Point (FP16)
  84 ====================================
  85
  86 If the F extension is supported, SVprefix adds support for FP16 in the
  87 base FP instructions by using 10 (H) in the floating-point format field
  88 *fmt* and using 001 (H) in the floating-point load/store *width* field.
  89
  90 Compressed Instructions
  91 =======================
  92
  93 Compressed instructions are under evaluation by taking the same
  94 prefix as used in P48, embedding that and standard RVC opcodes (minus
  95 their RVC prefix) into a 32-bit space.  This by taking the three remaining
  96 Major "custom" opcodes (0-2), one for each of the three RVC Quadrants.
  97 see [[discussion]].
  98
  99 48-bit Prefixed Instructions
 100 ============================
 101
 102 All 48-bit prefixed instructions contain a 32-bit "base" instruction as
 103 the last 4 bytes. Since all 32-bit instructions have bits 1:0 set to
 104 11, those bits are reused for additional encoding space in the 48-bit
 105 instructions.
 106
 107 64-bit Prefixed Instructions
 108 ============================
 109
 110 The 48 bit format is further extended with the full 128-bit range on all
 111 source and destination registers, and the option to set both VL and MVL
 112 is provided.
 113
 114 48-bit Instruction Encodings
 115 ============================
 116
 117 In the following table, *Rsvd* (reserved) entries must be zero.  RV32 equivalent
 118 encodings included for side-by-side comparison (and listed below,
 119 separately).
 120
 121 First, bits 17:0:
 122
 123 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 124 | Encoding      | 17     | 16     | 15       | 14  | 13     | 12          | 11:7 | 6      | 5:0    |
 125 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 126 | P48-LD-type   | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 127 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 128 | P48-ST-type   |vitp7[6]| rs1[5] | rs2[5]   | vs2 | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 129 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 130 | P48-R-type    | rd[5]  | rs1[5] | rs2[5]   | vs2 | vs1    | vitp6              | *Rsvd* | 011111 |
 131 +---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
 132 | P48-I-type    | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 133 +---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
 134 | P48-U-type    | rd[5]  | *Rsvd* | *Rsvd*   | vd  | *Rsvd* | vitp6              | *Rsvd* | 011111 |
 135 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 136 | P48-FR-type   | rd[5]  | rs1[5] | rs2[5]   | vs2 | vs1    | *Rsvd*      | vtp5 | *Rsvd* | 011111 |
 137 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 138 | P48-FI-type   | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 139 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 140 | P48-FR4-type  | rd[5]  | rs1[5] | rs2[5]   | vs2 | rs3[5] | vs3 [#fr4]_ | vtp5 | *Rsvd* | 011111 |
 141 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 142
 143 .. [#fr4] Only vs2 and vs3 are included in the P48-FR4-type encoding
 144           because there is not enough space for vs1 as well, and because
 145           it is more useful to have a scalar argument for each of the
 146           multiplication and addition portions of fmadd than to have
 147           two scalars on the multiplication portion.
 148
 149 Table showing correspondance between P48-*-type and RV32-*-type.
 150 These are bits 47:18 (RV32 shifted up by 16 bits):
 151
 152 +---------------+---------------+
 153 | Encoding      | 47:18         |
 154 +---------------+---------------+
 155 | RV32 Encoding | 31:2          |
 156 +---------------+---------------+
 157 | P48-LD-type   | RV32-I-type   |
 158 +---------------+---------------+
 159 | P48-ST-type   | RV32-S-Type   |
 160 +---------------+---------------+
 161 | P48-R-type    | RV32-R-Type   |
 162 +---------------+---------------+
 163 | P48-I-type    | RV32-I-Type   |
 164 +---------------+---------------+
 165 | P48-U-type    | RV32-U-Type   |
 166 +---------------+---------------+
 167 | P48-FR-type   | RV32-FR-Type  |
 168 +---------------+---------------+
 169 | P48-FI-type   | RV32-I-Type   |
 170 +---------------+---------------+
 171 | P48-FR4-type  | RV32-FR4-type |
 172 +---------------+---------------+
 173
 174 Table showing Standard RV32 encodings:
 175
 176 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 177 | Encoding      | 31:27       | 26:25 | 24:20    | 19:15    | 14:12  | 11:7     | 6:2    | 1:0    |
 178 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 179 | RV32-R-type   +    funct7           + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 180 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 181 | RV32-S-type   + imm[11:5]           + rs2[4:0] + rs1[4:0] + funct3 | imm[4:0] + opcode + 0b11   |
 182 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 183 | RV32-I-type   + imm[11:0]                      + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 184 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 185 | RV32-U-type   + imm[31:12]                                         | rd[4:0]  + opcode + 0b11   |
 186 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 187 | RV32-FR4-type + rs3[4:0]    + fmt   + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 188 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 189 | RV32-FR-type  + funct5      + fmt   + rs2[4:0] + rs1[4:0] + rm     | rd[4:0]  + opcode + 0b11   |
 190 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 191
 192 64-bit Instruction Encodings
 193 ============================
 194
 195 Where in the 48 bit format the prefix is "0b0011111" in bits 0 to 6,
 196 this is now set to "0b0111111".
 197
 198 +---------------+---------------+--------------+-----------+
 199 | 63:48         | 47:18         | 17:7         | 6:0       |
 200 +---------------+---------------+--------------+-----------+
 201 | 64 bit prefix | RV32[31:3]    | P48[17:7]    | 0b0111111 |
 202 +---------------+---------------+--------------+-----------+
 203
 204 * The 64 bit prefix format is below
 205 * Bits 18 to 47 contain bits 3 to 31 of a standard RV32 format
 206 * Bits 7 to 17 contain bits 7 through 17 of the P48 format
 207 * Bits 0 to 6 contain the standard RV 64-bit prefix 0b0111111
 208
 209 64 bit prefix format:
 210
 211 +--------------+-------+--------+--------+--------+--------+
 212 | Encoding     | 63    | 62     | 61     | 60     | 59:48  |
 213 +--------------+-------+--------+--------+--------+--------+
 214 | P64-LD-type  | rd[6] | rs1[6] |        | *Rsvd* | VLtyp  |
 215 +--------------+-------+--------+--------+--------+--------+
 216 | P64-ST-type  |       | rs1[6] | rs2[6] | *Rsvd* | VLtyp  |
 217 +--------------+-------+--------+--------+--------+--------+
 218 | P64-R-type   | rd[6] | rs1[6] | rs2[6] | *Rsvd* | VLtyp  |
 219 +--------------+-------+--------+--------+--------+--------+
 220 | P64-I-type   | rd[6] | rs1[6] |        | *Rsvd* | VLtyp  |
 221 +--------------+-------+--------+--------+--------+--------+
 222 | P64-U-type   | rd[6] |        |        | *Rsvd* | VLtyp  |
 223 +--------------+-------+--------+--------+--------+--------+
 224 | P64-FR-type  |       | rs1[6] | rs2[6] | *Rsvd* | VLtyp  |
 225 +--------------+-------+--------+--------+--------+--------+
 226 | P64-FI-type  | rd[6] | rs1[6] | rs2[6] | *Rsvd* | VLtyp  |
 227 +--------------+-------+--------+--------+--------+--------+
 228 | P64-FR4-type | rd[6] | rs1[6] | rs2[6] | rs3[6] | VLtyp  |
 229 +--------------+-------+--------+--------+--------+--------+
 230
 231 The extra bit for src and dest registers provides the full range of
 232 up to 128 registers, when combined with the extra bit from the 48 bit
 233 prefix as well.  VLtyp encodes how (whether) to set VL and MAXVL.
 234
 235 VLtyp field encoding
 236 ====================
 237
 238 NOTE: VL and MVL below are modified (potentially damaging) and so is
 239 the STATE CSR. It is the responsibility of the programmer to ensure that
 240 modifications to STATE do not compromise loops or VBLOCK Group operations,
 241 by saving and restoring the STATE CSR (if needed).
 242
 243 +-----------+-------------+--------------+----------+----------------------+
 244 | VLtyp[11] | VLtyp[10:6] | VLtyp[5:1]   | VLtyp[0] | comment              |
 245 +-----------+-------------+--------------+----------+----------------------+
 246 | 0         |  00000      | 00000        |  0       | no change to VL/MVL  |
 247 +-----------+-------------+--------------+----------+----------------------+
 248 | 0         |  VLdest     | VLEN         |  vlt     | VL imm/reg mode (vlt)|
 249 +-----------+-------------+--------------+----------+----------------------+
 250 | 1         |  VLdest     | MVL+VL-immed | 0        | MVL+VL immed mode    |
 251 +-----------+-------------+--------------+----------+----------------------+
 252 | 1         |  VLdest     |  MVL-immed   | 1        | MVL immed mode       |
 253 +-----------+-------------+--------------+----------+----------------------+
 254
 255 Note: when VLtyp is all zeros, neither VL nor MVL are changed.
 256
 257 Just as in the VBLOCK format, when bit 11 of VLtyp is zero:
 258
 259 * if vlt is zero, bits 1 to 5 specify the VLEN as a 5 bit immediate
 260   (offset by 1: 0b00000 represents VL=1, 0b00001 represents VL=2 etc.)
 261 * if vlt is 1, bits 1 to 5 specify the scalar (RV standard) register
 262   from which VL is set.  x0 is not permitted
 263 * VL goes into the scalar register VLdest (if VLdest is not x0)
 264
 265 When bit 11 of VLtype is 1:
 266
 267 * if VLtyp[0] is zero, both MAXVL and VL are set to (imm+1).  The same
 268   value goes into the scalar register VLdest (if VLdest is not x0)
 269 * if VLtyp[0] is 1, MAXVL is set to (imm+1).
 270   VL will be truncated to within the new range (if VL was greater
 271   than the new MAXVL).  The new VL goes into the scalar register VLdest
 272   (if VLdest is not x0).
 273
 274 This gives the option to set up VL in a "loop mode" (VLtype[11]=0) or
 275 in a "one-off" mode (VLtype[11]=1) which sets both MVL and VL to the
 276 same immediate value.  This may be most useful for one-off Vectorised
 277 operations such as LOAD-MULTI / STORE-MULTI, for saving and restoration
 278 of large batches of registers in context-switches or function calls.
 279
 280 Note that VLtyp's VL and MVL are the same as the main Specification_
 281 VL or MVL, and that loops will also alter srcoffs and destoffs. It is
 282 the programmer's responsibility to ensure that STATE is not compromised
 283 (e.g saved to a temp reg or to the stack).
 284
 285 Furthermore, the execution order and exception handling must be exactly
 286 the same as in the main spec.
 287
 288 vs#/vd Fields' Encoding
 289 =======================
 290
 291 +--------+----------+----------------------------------------------------------+
 292 | vs#/vd | Mnemonic | Meaning                                                  |
 293 +========+==========+==========================================================+
 294 | 0      | S        | the rs#/rd field specifies a scalar (single sub-vector); |
 295 |        |          | the rs#/rd field is zero-extended to get the actual      |
 296 |        |          | 7-bit register number                                    |
 297 +--------+----------+----------------------------------------------------------+
 298 | 1      | V        | the rs#/rd field specifies a vector; the rs#/rd field is |
 299 |        |          | decoded using the `Vector Register Number Encoding`_ to  |
 300 |        |          | get the actual 7-bit register number                     |
 301 +--------+----------+----------------------------------------------------------+
 302
 303 If a vs#/vd field is not present, it is as if it was present with a value that
 304 is the bitwise-or of all present vs#/vd fields.
 305
 306 * scalar register numbers do NOT increment when allocated in the
 307   hardware for-loop.  the same scalar register number is handed
 308   to every ALU.
 309
 310 * vector register numbers *DO* increase when allocated in the
 311   hardware for-loop.  sequentially-increasing register data
 312   is handed to sequential ALUs.
 313
 314 Vector Register Number Encoding
 315 ===============================
 316
 317 For the 48 bit format, when vs#/vd is 1, the actual 7-bit register number
 318 is derived from the corresponding 6-bit rs#/rd field:
 319
 320 +---------------------------------+
 321 | Actual 7-bit register number    |
 322 +===========+=============+=======+
 323 | Bit 6     | Bits 5:1    | Bit 0 |
 324 +-----------+-------------+-------+
 325 | rs#/rd[0] | rs#/rd[5:1] | 0     |
 326 +-----------+-------------+-------+
 327
 328 For the 64 bit format, the 7 bit register is constructed from the 7 bit
 329 fields: bits 0 to 4 from the 32 bit RV Standard format, bit 5 from the 48
 330 bit prefix and bit 6 from the 64 bit prefix.  Thus in the 64 bit format
 331 the full range of up to 128 registers is directly available. This for
 332 both when either scalar or vector mode is set.
 333
 334 Load/Store Kind (lsk) Field Encoding
 335 ====================================
 336
 337 +--------+-----+--------------------------------------------------------------------------------+
 338 | vd/vs2 | vs1 | Meaning                                                                        |
 339 +========+=====+================================================================================+
 340 | 0      | 0   | srcbase is scalar, LD/ST is pure scalar.                                       |
 341 +--------+-----+--------------------------------------------------------------------------------+
 342 | 1      | 0   | srcbase is scalar, LD/ST is unit strided                                       |
 343 +--------+-----+--------------------------------------------------------------------------------+
 344 | 0      | 1   | srcbase is a vector (gather/scatter aka array of srcbases). VSPLAT and VSELECT |
 345 +--------+-----+--------------------------------------------------------------------------------+
 346 | 1      | 1   | srcbase is a vector, LD/ST is a full vector LD/ST.                             |
 347 +--------+-----+--------------------------------------------------------------------------------+
 348
 349 Notes:
 350
 351 * A register strided LD/ST would require *5* registers. srcbase, vd/vs2,
 352   predicate 1, predicate 2 and the stride register.
 353 * Complex strides may all be done with a general purpose vector of srcbases.
 354 * Twin predication may be used even when vd/vs1 is a scalar, to give
 355   VSPLAT and VSELECT, because the hardware loop ends on the first occurrence
 356   of a 1 in the predicate when a predicate is applied to a scalar.
 357 * Full vectorised gather/scatter is enabled when both registers are
 358   marked as vectorised, however unlike e.g Intel AVX512, twin predication
 359   can be applied.
 360
 361 Open question: RVV overloads the width field of LOAD-FP/STORE-FP
 362 using the bit 2 to indicate additional interpretation of the 11 bit
 363 immediate. Should this be considered?
 364
 365
 366 Sub-Vector Length (svlen) Field Encoding
 367 ========================================
 368
 369 NOTE: svlen is the same as the main spec SUBVL, and modifies the STATE
 370 CSR. The same caveats apply to svlen as do to SUBVL.
 371
 372 Bitwidth, from VL's perspective, is a multiple of the elwidth times svlen.
 373 So within each loop of VL there are svlen sub-elements of elwidth in size,
 374 just like in a SIMD architecture. When svlen is set to 0b00 (indicating
 375 svlen=1) no such SIMD-like behaviour exists and the subvectoring is
 376 disabled.
 377
 378 Predicate bits do not apply to the individual sub-vector elements, they
 379 apply to the entire subvector group. This saves instructions on setup
 380 of the predicate.
 381
 382 +----------------+-------+
 383 | svlen Encoding | Value |
 384 +================+=======+
 385 | 00             | SUBVL |
 386 +----------------+-------+
 387 | 01             | 2     |
 388 +----------------+-------+
 389 | 10             | 3     |
 390 +----------------+-------+
 391 | 11             | 4     |
 392 +----------------+-------+
 393
 394 In independent standalone implementations that do not implement the
 395 main specification, the value of SUBVL in the above table (svtyp=0b00)
 396 is set to 1, such that svlen is also 1.
 397
 398 Behaviour of operations that set svlen are identical to those of the
 399 main spec. See section on VLtyp, above.
 400
 401 Predication (pred) Field Encoding
 402 =================================
 403
 404 +------+------------+--------------------+----------------------------------------+
 405 | pred | Mnemonic   | Predicate Register | Meaning                                |
 406 +======+============+====================+========================================+
 407 | 000  | *None*     | *None*             | The instruction is unpredicated        |
 408 +------+------------+--------------------+----------------------------------------+
 409 | 001  | *Reserved* | *Reserved*         |                                        |
 410 +------+------------+--------------------+----------------------------------------+
 411 | 010  | !x9        | x9 (s1)            | execute vector op[0..i] on x9[i] == 0  |
 412 +------+------------+                    +----------------------------------------+
 413 | 011  | x9         |                    | execute vector op[0..i] on x9[i] == 1  |
 414 +------+------------+--------------------+----------------------------------------+
 415 | 100  | !x10       | x10 (a0)           | execute vector op[0..i] on x10[i] == 0 |
 416 +------+------------+                    +----------------------------------------+
 417 | 101  | x10        |                    | execute vector op[0..i] on x10[i] == 1 |
 418 +------+------------+--------------------+----------------------------------------+
 419 | 110  | !x11       | x11 (a1)           | execute vector op[0..i] on x11[i] == 0 |
 420 +------+------------+                    +----------------------------------------+
 421 | 111  | x11        |                    | execute vector op[0..i] on x11[i] == 1 |
 422 +------+------------+--------------------+----------------------------------------+
 423
 424 Twin-predication (tpred) Field Encoding
 425 =======================================
 426
 427 +-------+------------+--------------------+----------------------------------------------+
 428 | tpred | Mnemonic   | Predicate Register | Meaning                                      |
 429 +=======+============+====================+==============================================+
 430 | 000   | *None*     | *None*             | The instruction is unpredicated              |
 431 +-------+------------+--------------------+----------------------------------------------+
 432 | 001   | x9,off     | src=x9, dest=none  | src[0..i] uses x9[i], dest unpredicated      |
 433 +-------+------------+                    +----------------------------------------------+
 434 | 010   | off,x10    | src=none, dest=x10 | dest[0..i] uses x10[i], src unpredicated     |
 435 +-------+------------+                    +----------------------------------------------+
 436 | 011   | x9,10      | src=x9, dest=x10   | src[0..i] uses x9[i], dest[0..i] uses x10[i] |
 437 +-------+------------+--------------------+----------------------------------------------+
 438 | 100   | *None*     | *RESERVED*         | Instruction is unpredicated (TBD)            |
 439 +-------+------------+--------------------+----------------------------------------------+
 440 | 101   | !x9,off    | src=!x9, dest=none |                                              |
 441 +-------+------------+                    +----------------------------------------------+
 442 | 110   | off,!x10   | src=none, dest=!x10|                                              |
 443 +-------+------------+                    +----------------------------------------------+
 444 | 111   | !x9,!x10   | src=!x9, dest=!x10 |                                              |
 445 +-------+------------+--------------------+----------------------------------------------+
 446
 447 Integer Element Type (itype) Field Encoding
 448 ===========================================
 449
 450 +------------+-------+--------------+--------------+-----------------+-------------------+
 451 | Signedness | itype | Element Type | Mnemonic in  | Mnemonic in FP  | Meaning (INT may  |
 452 | [#sgn_def]_|       |              | Integer      | Instructions    | be un/signed, FP  |
 453 | [#sgn_def]_|       |              | Instructions | (such as fmv.x) | just re-sized     |
 454 +============+=======+==============+==============+=================+===================+
 455 | Unsigned   | 01    | u8           | BU           | BU              | Unsigned 8-bit    |
 456 |            +-------+--------------+--------------+-----------------+-------------------+
 457 |            | 10    | u16          | HU           | HU              | Unsigned 16-bit   |
 458 |            +-------+--------------+--------------+-----------------+-------------------+
 459 |            | 11    | u32          | WU           | WU              | Unsigned 32-bit   |
 460 |            +-------+--------------+--------------+-----------------+-------------------+
 461 |            | 00    | uXLEN        | WU/DU/QU     | WU/LU/TU        | Unsigned XLEN-bit |
 462 +------------+-------+--------------+--------------+-----------------+-------------------+
 463 | Signed     | 01    | i8           | BS           | BS              | Signed 8-bit      |
 464 |            +-------+--------------+--------------+-----------------+-------------------+
 465 |            | 10    | i16          | HS           | HS              | Signed 16-bit     |
 466 |            +-------+--------------+--------------+-----------------+-------------------+
 467 |            | 11    | i32          | W            | W               | Signed 32-bit     |
 468 |            +-------+--------------+--------------+-----------------+-------------------+
 469 |            | 00    | iXLEN        | W/D/Q        | W/L/T           | Signed XLEN-bit   |
 470 +------------+-------+--------------+--------------+-----------------+-------------------+
 471
 472 .. [#sgn_def] Signedness is defined in `Signedness Decision Procedure`_
 473
 474 Note: vector mode is effectively a type-cast of the register file
 475 as if it was a sequential array being typecast to typedef itype[]
 476 (c syntax).  The starting point of the "typecast" is the vector
 477 register rs#/rd.
 478
 479 Example: if itype=0b10 (u16), and rd is set to "vector", and
 480 VL is set to 4, the 64-bit register at rd is subdivided into
 481 *FOUR* 16-bit destination elements.  It is *NOT* four
 482 separate 64-bit destination registers (rd+0, rd+1, rd+2, rd+3)
 483 that are sign-extended from the source width size out to 64-bit,
 484 because that is itype=0b00 (uXLEN).
 485
 486 Note also: changing elwidth creates packed elements that, depending on
 487 VL, may create vectors that do not fit perfectly onto XLEN sized registry
 488 file bit-boundaries. This does NOT result in the destruction of the MSBs
 489 of the last register written to at the end of a VL loop. More details
 490 on how to handle this are described in the main Specification_.
 491
 492 Signedness Decision Procedure
 493 =============================
 494
 495 1. If the opcode field is either OP or OP-IMM, then
 496     1. Signedness is Unsigned.
 497 2. If the opcode field is either OP-32 or OP-IMM-32, then
 498     1. Signedness is Signed.
 499 3. If Signedness is encoded in a field of the base instruction, [#sign_enc]_ then
 500     1. Signedness uses the encoded value.
 501 4. Otherwise,
 502     1. Signedness is Unsigned.
 503
 504 .. [#sign_enc] Like in fcvt.d.l[u], but unlike in fmv.x.w,
 505                since there is no fmv.x.wu
 506
 507 Vector Type and Predication 5-bit (vtp5) Field Encoding
 508 =========================================================
 509
 510 In the following table, X denotes a wildcard that is 0 or 1 and can be
 511 a different value for every occurrence.
 512
 513 +-------+-----------+-----------+
 514 | vtp5  | pred      | svlen     |
 515 +=======+===========+===========+
 516 | 1XXXX | vtp5[4:2] | vtp5[1:0] |
 517 +-------+           |           |
 518 | 01XXX |           |           |
 519 +-------+           |           |
 520 | 000XX |           |           |
 521 +-------+-----------+-----------+
 522 | 001XX | *Reserved*            |
 523 +-------+-----------------------+
 524
 525 Vector Integer Type and Predication 6-bit (vitp6) Field Encoding
 526 =================================================================
 527
 528 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 529 different value for every occurrence.
 530
 531 +--------+------------+---------+------------+------------+
 532 | vitp6  | itype      | pred[2] | pred[0:1]  | svlen      |
 533 +========+============+=========+============+============+
 534 | XX1XXX | vitp6[5:4] | 0       | vitp6[3:2] | vitp6[1:0] |
 535 +--------+            |         |            |            |
 536 | XX00XX |            |         |            |            |
 537 +--------+------------+---------+------------+------------+
 538 | XX01XX | *Reserved*                                     |
 539 +--------+------------------------------------------------+
 540
 541 vitp7 field: only tpred
 542
 543 +---------+------------+----------+-------------+------------+
 544 | vitp7   | itype      | tpred[2] | tpred[0:1]  | svlen      |
 545 +=========+============+==========+=============+============+
 546 | XXXXXXX | vitp7[5:4] | vitp7[6] | vitp7[3:2]  | vitp7[1:0] |
 547 +---------+------------+----------+-------------+------------+
 548
 549 48-bit Instruction Encoding Decision Procedure
 550 ==============================================
 551
 552 In the following decision procedure, *Reserved* means that there is not
 553 yet a defined 48-bit instruction encoding for the base instruction.
 554
 555 1. If the base instruction is a load instruction, then
 556     a. If the base instruction is an I-type instruction, then
 557         1. The encoding is P48-LD-type.
 558     b. Otherwise
 559         1. The encoding is *Reserved*.
 560 2. If the base instruction is a store instruction, then
 561     a. If the base instruction is an S-type instruction, then
 562         1. The encoding is P48-ST-type.
 563     b. Otherwise
 564         1. The encoding is *Reserved*.
 565 3. If the base instruction is a SYSTEM instruction, then
 566     a. The encoding is *Reserved*.
 567 4. If the base instruction is an integer instruction, then
 568     a. If the base instruction is an R-type instruction, then
 569         1. The encoding is P48-R-type.
 570     b. If the base instruction is an I-type instruction, then
 571         1. The encoding is P48-I-type.
 572     c. If the base instruction is an S-type instruction, then
 573         1. The encoding is *Reserved*.
 574     d. If the base instruction is an B-type instruction, then
 575         1. The encoding is *Reserved*.
 576     e. If the base instruction is an U-type instruction, then
 577         1. The encoding is P48-U-type.
 578     f. If the base instruction is an J-type instruction, then
 579         1. The encoding is *Reserved*.
 580     g. Otherwise
 581         1. The encoding is *Reserved*.
 582 5. If the base instruction is a floating-point instruction, then
 583     a. If the base instruction is an R-type instruction, then
 584         1. The encoding is P48-FR-type.
 585     b. If the base instruction is an I-type instruction, then
 586         1. The encoding is P48-FI-type.
 587     c. If the base instruction is an S-type instruction, then
 588         1. The encoding is *Reserved*.
 589     d. If the base instruction is an B-type instruction, then
 590         1. The encoding is *Reserved*.
 591     e. If the base instruction is an U-type instruction, then
 592         1. The encoding is *Reserved*.
 593     f. If the base instruction is an J-type instruction, then
 594         1. The encoding is *Reserved*.
 595     g. If the base instruction is an R4-type instruction, then
 596         1. The encoding is P48-FR4-type.
 597     h. Otherwise
 598         1. The encoding is *Reserved*.
 599 6. Otherwise
 600     a. The encoding is *Reserved*.
 601
 602 CSR Registers
 603 =============
 604
 605 CSRs are the same as in the main Specification_, if associated
 606 functionality is implemented. They have the exact same meaning as in
 607 the main specification.
 608
 609 * VL
 610 * MVL
 611 * STATE
 612 * SUBVL
 613
 614 Associated SET and GET on the CSRs is exactly as in the main spec as well
 615 (including CSRRWI and CSRRW differences).
 616
 617 Note that if all of VL/MVL, SUBVL, VLtyp and svlen are all chosen by an
 618 implementor not to be implemented, the STATE CSR is not required.
 619
 620 However if partial functionality is implemented, the unimplemented bits
 621 in STATE must be zero, and, in the UNIX Platform, an illegal exception
 622 **MUST** be raised if unsupported bits are written to.
 623
 624 Additional Instructions
 625 =======================
 626
 627 * Add instructions to convert between integer types.
 628 * Add instructions to `swizzle`_ elements in sub-vectors. Note that
 629   the sub-vector lengths of the source and destination won't necessarily
 630   match.
 631 * Add instructions to transpose (2-4)x(2-4) element matrices.
 632 * Add instructions to insert or extract a sub-vector from a vector, with
 633   the index allowed to be both immediate and from a register (*immediate
 634   can be covered by twin-predication, register might be, by virtue of
 635   predicates being registers*)
 636 * Add a register gather instruction (aka MV.X: regfile[rd] =
 637   regfile[regfile[rs1]])
 638
 639 subelement swizzle example:
 640
 641     velswizzle x32, x64, SRCSUBVL=3, DESTSUBVL=4, ELTYPE=u8, elements=[0, 0, 2, 1]
 642
 643 .. _swizzle: https://www.khronos.org/opengl/wiki/Data_Type_(GLSL)#Swizzling
 644
 645 questions
 646 =========
 647
 648 Moved to the discussion page (link at top of this page)
 649
 650 TODO
 651 ====
 652
 653 Work out a way to do sub-element swizzling.
 654