3 # Variable-width Variable-packed SIMD / Simple-V / Parallelism Extension Proposal
5 **OBSOLETE. This document is out of date and involved early ideas and discussions. [Go to the up-to-date document](https://libre-soc.org/openpower/sv/)**
7 Key insight: Simple-V is intended as an abstraction layer to provide
8 a consistent "API" to parallelisation of existing *and future* operations.
9 *Actual* internal hardware-level parallelism is *not* required, such
10 that Simple-V may be viewed as providing a "compact" or "consolidated"
11 means of issuing multiple near-identical arithmetic instructions to an
12 instruction queue (FIFO), pending execution.
14 *Actual* parallelism, if added independently of Simple-V in the form
15 of Out-of-order restructuring (including parallel ALU lanes) or VLIW
16 implementations, or SIMD, or anything else, would then benefit from
17 the uniformity of a consistent API.
19 **No arithmetic operations are added or required to be added.** SV is purely a parallelism API and consequentially is suitable for use even with RV32E.
21 * Talk slides: <http://hands.com/~lkcl/simple_v_chennai_2018.pdf>
22 * Specification: now move to its own page: [[specification]]
28 This proposal exists so as to be able to satisfy several disparate
29 requirements: power-conscious, area-conscious, and performance-conscious
30 designs all pull an ISA and its implementation in different conflicting
31 directions, as do the specific intended uses for any given implementation.
33 The existing P (SIMD) proposal and the V (Vector) proposals,
34 whilst each extremely powerful in their own right and clearly desirable,
37 * Clearly independent in their origins (Cray and AndesStar v3 respectively)
38 so need work to adapt to the RISC-V ethos and paradigm
39 * Are sufficiently large so as to make adoption (and exploration for
40 analysis and review purposes) prohibitively expensive
41 * Both contain partial duplication of pre-existing RISC-V instructions
42 (an undesirable characteristic)
43 * Both have independent, incompatible and disparate methods for introducing
44 parallelism at the instruction level
45 * Both require that their respective parallelism paradigm be implemented
46 along-side and integral to their respective functionality *or not at all*.
47 * Both independently have methods for introducing parallelism that
48 could, if separated, benefit
49 *other areas of RISC-V not just DSP or Floating-point respectively*.
51 There are also key differences between Vectorisation and SIMD (full
52 details outlined in the Appendix), the key points being:
54 * SIMD has an extremely seductively compelling ease of implementation argument:
55 each operation is passed to the ALU, which is where the parallelism
56 lies. There is *negligeable* (if any) impact on the rest of the core
57 (with life instead being made hell for compiler writers and applications
58 writers due to extreme ISA proliferation).
59 * By contrast, Vectorisation has quite some complexity (for considerable
60 flexibility, reduction in opcode proliferation and much more).
61 * Vectorisation typically includes much more comprehensive memory load
62 and store schemes (unit stride, constant-stride and indexed), which
63 in turn have ramifications: virtual memory misses (TLB cache misses)
64 and even multiple page-faults... all caused by a *single instruction*,
65 yet with a clear benefit that the regularisation of LOAD/STOREs can
66 be optimised for minimal impact on caches and maximised throughput.
67 * By contrast, SIMD can use "standard" memory load/stores (32-bit aligned
68 to pages), and these load/stores have absolutely nothing to do with the
69 SIMD / ALU engine, no matter how wide the operand. Simplicity but with
70 more impact on instruction and data caches.
72 Overall it makes a huge amount of sense to have a means and method
73 of introducing instruction parallelism in a flexible way that provides
74 implementors with the option to choose exactly where they wish to offer
75 performance improvements and where they wish to optimise for power
76 and/or area (and if that can be offered even on a per-operation basis that
77 would provide even more flexibility).
79 Additionally it makes sense to *split out* the parallelism inherent within
80 each of P and V, and to see if each of P and V then, in *combination* with
81 a "best-of-both" parallelism extension, could be added on *on top* of
82 this proposal, to topologically provide the exact same functionality of
83 each of P and V. Each of P and V then can focus on providing the best
84 operations possible for their respective target areas, without being
85 hugely concerned about the actual parallelism.
87 Furthermore, an additional goal of this proposal is to reduce the number
88 of opcodes utilised by each of P and V as they currently stand, leveraging
89 existing RISC-V opcodes where possible, and also potentially allowing
90 P and V to make use of Compressed Instructions as a result.
92 # Analysis and discussion of Vector vs SIMD
94 There are six combined areas between the two proposals that help with
95 parallelism (increased performance, reduced power / area) without
96 over-burdening the ISA with a huge proliferation of
99 * Fixed vs variable parallelism (fixed or variable "M" in SIMD)
100 * Implicit vs fixed instruction bit-width (integral to instruction or not)
101 * Implicit vs explicit type-conversion (compounded on bit-width)
102 * Implicit vs explicit inner loops.
103 * Single-instruction LOAD/STORE.
104 * Masks / tagging (selecting/preventing certain indexed elements from execution)
106 The pros and cons of each are discussed and analysed below.
108 ## Fixed vs variable parallelism length
110 In David Patterson and Andrew Waterman's analysis of SIMD and Vector
111 ISAs, the analysis comes out clearly in favour of (effectively) variable
112 length SIMD. As SIMD is a fixed width, typically 4, 8 or in extreme cases
113 16 or 32 simultaneous operations, the setup, teardown and corner-cases of SIMD
114 are extremely burdensome except for applications whose requirements
115 *specifically* match the *precise and exact* depth of the SIMD engine.
117 Thus, SIMD, no matter what width is chosen, is never going to be acceptable
118 for general-purpose computation, and in the context of developing a
119 general-purpose ISA, is never going to satisfy 100 percent of implementors.
121 To explain this further: for increased workloads over time, as the
122 performance requirements increase for new target markets, implementors
123 choose to extend the SIMD width (so as to again avoid mixing parallelism
124 into the instruction issue phases: the primary "simplicity" benefit of
125 SIMD in the first place), with the result that the entire opcode space
126 effectively doubles with each new SIMD width that's added to the ISA.
128 That basically leaves "variable-length vector" as the clear *general-purpose*
129 winner, at least in terms of greatly simplifying the instruction set,
130 reducing the number of instructions required for any given task, and thus
131 reducing power consumption for the same.
133 ## Implicit vs fixed instruction bit-width
135 SIMD again has a severe disadvantage here, over Vector: huge proliferation
136 of specialist instructions that target 8-bit, 16-bit, 32-bit, 64-bit, and
137 have to then have operations *for each and between each*. It gets very
138 messy, very quickly: *six* separate dimensions giving an O(N^6) instruction
139 proliferation profile.
141 The V-Extension on the other hand proposes to set the bit-width of
142 future instructions on a per-register basis, such that subsequent instructions
143 involving that register are *implicitly* of that particular bit-width until
144 otherwise changed or reset.
146 This has some extremely useful properties, without being particularly
147 burdensome to implementations, given that instruction decode already has
148 to direct the operation to a correctly-sized width ALU engine, anyway.
150 Not least: in places where an ISA was previously constrained (due for
151 whatever reason, including limitations of the available operand space),
152 implicit bit-width allows the meaning of certain operations to be
153 type-overloaded *without* pollution or alteration of frozen and immutable
154 instructions, in a fully backwards-compatible fashion.
156 ## Implicit and explicit type-conversion
158 The Draft 2.3 V-extension proposal has (deprecated) polymorphism to help
159 deal with over-population of instructions, such that type-casting from
160 integer (and floating point) of various sizes is automatically inferred
161 due to "type tagging" that is set with a special instruction. A register
162 will be *specifically* marked as "16-bit Floating-Point" and, if added
163 to an operand that is specifically tagged as "32-bit Integer" an implicit
164 type-conversion will take place *without* requiring that type-conversion
165 to be explicitly done with its own separate instruction.
167 However, implicit type-conversion is not only quite burdensome to
168 implement (explosion of inferred type-to-type conversion) but also is
169 never really going to be complete. It gets even worse when bit-widths
170 also have to be taken into consideration. Each new type results in
171 an increased O(N^2) conversion space that, as anyone who has examined
172 python's source code (which has built-in polymorphic type-conversion),
173 knows that the task is more complex than it first seems.
175 Overall, type-conversion is generally best to leave to explicit
176 type-conversion instructions, or in definite specific use-cases left to
177 be part of an actual instruction (DSP or FP)
179 ## Zero-overhead loops vs explicit loops
181 The initial Draft P-SIMD Proposal by Chuanhua Chang of Andes Technology
182 contains an extremely interesting feature: zero-overhead loops. This
183 proposal would basically allow an inner loop of instructions to be
184 repeated indefinitely, a fixed number of times.
186 Its specific advantage over explicit loops is that the pipeline in a DSP
187 can potentially be kept completely full *even in an in-order single-issue
188 implementation*. Normally, it requires a superscalar architecture and
189 out-of-order execution capabilities to "pre-process" instructions in
190 order to keep ALU pipelines 100% occupied.
192 By bringing that capability in, this proposal could offer a way to increase
193 pipeline activity even in simpler implementations in the one key area
194 which really matters: the inner loop.
196 However when looking at much more comprehensive schemes
197 "A portable specification of zero-overhead loop control hardware
198 applied to embedded processors" (ZOLC), optimising only the single
199 inner loop seems inadequate, tending to suggest that ZOLC may be
200 better off being proposed as an entirely separate Extension.
202 ## Single-instruction LOAD/STORE
204 In traditional Vector Architectures there are instructions which
205 result in multiple register-memory transfer operations resulting
206 from a single instruction. They're complicated to implement in hardware,
207 yet the benefits are a huge consistent regularisation of memory accesses
208 that can be highly optimised with respect to both actual memory and any
209 L1, L2 or other caches. In Hwacha EECS-2015-263 it is explicitly made
210 clear the consequences of getting this architecturally wrong:
211 L2 cache-thrashing at the very least.
213 Complications arise when Virtual Memory is involved: TLB cache misses
214 need to be dealt with, as do page faults. Some of the tradeoffs are
215 discussed in <http://people.eecs.berkeley.edu/~krste/thesis.pdf>, Section
216 4.6, and an article by Jeff Bush when faced with some of these issues
217 is particularly enlightening
218 <https://jbush001.github.io/2015/11/03/lost-in-translation.html>
220 Interestingly, none of this complexity is faced in SIMD architectures...
221 but then they do not get the opportunity to optimise for highly-streamlined
222 memory accesses either.
224 With the "bang-per-buck" ratio being so high and the indirect improvement
225 in L1 Instruction Cache usage (reduced instruction count), as well as
226 the opportunity to optimise L1 and L2 cache usage, the case for including
227 Vector LOAD/STORE is compelling.
229 ## Mask and Tagging (Predication)
231 Tagging (aka Masks aka Predication) is a pseudo-method of implementing
232 simplistic branching in a parallel fashion, by allowing execution on
233 elements of a vector to be switched on or off depending on the results
234 of prior operations in the same array position.
236 The reason for considering this is simple: by *definition* it
237 is not possible to perform individual parallel branches in a SIMD
238 (Single-Instruction, **Multiple**-Data) context. Branches (modifying
239 of the Program Counter) will result in *all* parallel data having
240 a different instruction executed on it: that's just the definition of
241 SIMD, and it is simply unavoidable.
243 So these are the ways in which conditional execution may be implemented:
245 * explicit compare and branch: BNE x, y -> offs would jump offs
246 instructions if x was not equal to y
247 * explicit store of tag condition: CMP x, y -> tagbit
248 * implicit (condition-code) such as ADD results in a carry, carry bit
249 implicitly (or sometimes explicitly) goes into a "tag" (mask) register
251 The first of these is a "normal" branch method, which is flat-out impossible
252 to parallelise without look-ahead and effectively rewriting instructions.
253 This would defeat the purpose of RISC.
255 The latter two are where parallelism becomes easy to do without complexity:
256 every operation is modified to be "conditionally executed" (in an explicit
257 way directly in the instruction format *or* implicitly).
259 RVV (Vector-Extension) proposes to have *explicit* storing of the compare
260 in a tag/mask register, and to *explicitly* have every vector operation
261 *require* that its operation be "predicated" on the bits within an
262 explicitly-named tag/mask register.
264 SIMD (P-Extension) has not yet published precise documentation on what its
265 schema is to be: there is however verbal indication at the time of writing
268 > The "compare" instructions in the DSP/SIMD ISA proposed by Andes will
269 > be executed using the same compare ALU logic for the base ISA with some
270 > minor modifications to handle smaller data types. The function will not
273 This is an *implicit* form of predication as the base RV ISA does not have
274 condition-codes or predication. By adding a CSR it becomes possible
275 to also tag certain registers as "predicated if referenced as a destination".
278 // in future operations from now on, if r0 is the destination use r5 as
279 // the PREDICATION register
280 SET_IMPLICIT_CSRPREDICATE r0, r5
281 // store the compares in r5 as the PREDICATION register
283 // r0 is used here. ah ha! that means it's predicated using r5!
286 With enough registers (and in RISC-V there are enough registers) some fairly
287 complex predication can be set up and yet still execute without significant
288 stalling, even in a simple non-superscalar architecture.
290 (For details on how Branch Instructions would be retro-fitted to indirectly
291 predicated equivalents, see Appendix)
295 In the above sections the five different ways where parallel instruction
296 execution has closely and loosely inter-related implications for the ISA and
297 for implementors, were outlined. The pluses and minuses came out as
300 * Fixed vs variable parallelism: <b>variable</b>
301 * Implicit (indirect) vs fixed (integral) instruction bit-width: <b>indirect</b>
302 * Implicit vs explicit type-conversion: <b>explicit</b>
303 * Implicit vs explicit inner loops: <b>implicit but best done separately</b>
304 * Single-instruction Vector LOAD/STORE: <b>Complex but highly beneficial</b>
305 * Tag or no-tag: <b>Complex but highly beneficial</b>
309 * variable-length vectors came out on top because of the high setup, teardown
310 and corner-cases associated with the fixed width of SIMD.
311 * Implicit bit-width helps to extend the ISA to escape from
312 former limitations and restrictions (in a backwards-compatible fashion),
313 whilst also leaving implementors free to simmplify implementations
314 by using actual explicit internal parallelism.
315 * Implicit (zero-overhead) loops provide a means to keep pipelines
316 potentially 100% occupied in a single-issue in-order implementation
317 i.e. *without* requiring a super-scalar or out-of-order architecture,
318 but doing a proper, full job (ZOLC) is an entirely different matter.
320 Constructing a SIMD/Simple-Vector proposal based around four of these six
321 requirements would therefore seem to be a logical thing to do.
323 # Note on implementation of parallelism
325 One extremely important aspect of this proposal is to respect and support
326 implementors desire to focus on power, area or performance. In that regard,
327 it is proposed that implementors be free to choose whether to implement
328 the Vector (or variable-width SIMD) parallelism as sequential operations
329 with a single ALU, fully parallel (if practical) with multiple ALUs, or
330 a hybrid combination of both.
332 In Broadcom's Videocore-IV, they chose hybrid, and called it "Virtual
333 Parallelism". They achieve a 16-way SIMD at an **instruction** level
334 by providing a combination of a 4-way parallel ALU *and* an externally
335 transparent loop that feeds 4 sequential sets of data into each of the
338 Also in the same core, it is worth noting that particularly uncommon
339 but essential operations (Reciprocal-Square-Root for example) are
340 *not* part of the 4-way parallel ALU but instead have a *single* ALU.
341 Under the proposed Vector (varible-width SIMD) implementors would
342 be free to do precisely that: i.e. free to choose *on a per operation
343 basis* whether and how much "Virtual Parallelism" to deploy.
345 It is absolutely critical to note that it is proposed that such choices MUST
346 be **entirely transparent** to the end-user and the compiler. Whilst
347 a Vector (varible-width SIMD) may not precisely match the width of the
348 parallelism within the implementation, the end-user **should not care**
349 and in this way the performance benefits are gained but the ISA remains
350 straightforward. All that happens at the end of an instruction run is: some
351 parallel units (if there are any) would remain offline, completely
352 transparently to the ISA, the program, and the compiler.
354 To make that clear: should an implementor choose a particularly wide
355 SIMD-style ALU, each parallel unit *must* have predication so that
356 the parallel SIMD ALU may emulate variable-length parallel operations.
357 Thus the "SIMD considered harmful" trap of having huge complexity and extra
358 instructions to deal with corner-cases is thus avoided, and implementors
359 get to choose precisely where to focus and target the benefits of their
360 implementation efforts, without "extra baggage".
362 In addition, implementors will be free to choose whether to provide an
363 absolute bare minimum level of compliance with the "API" (software-traps
364 when vectorisation is detected), all the way up to full supercomputing
365 level all-hardware parallelism. Options are covered in the Appendix.
368 ### FMV, FNEG and FABS Instructions
370 These are identical in form to C.MV, except covering floating-point
371 register copying. The same double-predication rules also apply.
372 However when elwidth is not set to default the instruction is implicitly
373 and automatic converted to a (vectorised) floating-point type conversion
374 operation of the appropriate size covering the source and destination
377 (Note that FMV, FNEG and FABS are all actually pseudo-instructions)
379 ### FVCT Instructions
381 These are again identical in form to C.MV, except that they cover
382 floating-point to integer and integer to floating-point. When element
383 width in each vector is set to default, the instructions behave exactly
384 as they are defined for standard RV (scalar) operations, except vectorised
385 in exactly the same fashion as outlined in C.MV.
387 However when the source or destination element width is not set to default,
388 the opcode's explicit element widths are *over-ridden* to new definitions,
389 and the opcode's element width is taken as indicative of the SIMD width
390 (if applicable i.e. if packed SIMD is requested) instead.
392 For example FCVT.S.L would normally be used to convert a 64-bit
393 integer in register rs1 to a 64-bit floating-point number in rd.
394 If however the source rs1 is set to be a vector, where elwidth is set to
395 default/2 and "packed SIMD" is enabled, then the first 32 bits of
396 rs1 are converted to a floating-point number to be stored in rd's
397 first element and the higher 32-bits *also* converted to floating-point
398 and stored in the second. The 32 bit size comes from the fact that
399 FCVT.S.L's integer width is 64 bit, and with elwidth on rs1 set to
400 divide that by two it means that rs1 element width is to be taken as 32.
402 Similar rules apply to the destination register.
406 > What does an ADD of two different-sized vectors do in simple-V?
408 * if the two source operands are not the same, throw an exception.
409 * if the destination operand is also a vector, and the source is longer
410 than the destination, throw an exception.
412 > And what about instructions like JALR?
413 > What does jumping to a vector do?
415 * Throw an exception. Whether that actually results in spawning threads
416 as part of the trap-handling remains to be seen.
418 # Under consideration <a name="issues"></a>
420 From the Chennai 2018 slides the following issues were raised.
421 Efforts to analyse and answer these questions are below.
423 * Should future extra bank be included now?
424 * How many Register and Predication CSRs should there be?
425 (and how many in RV32E)
426 * How many in M-Mode (for doing context-switch)?
427 * Should use of registers be allowed to "wrap" (x30 x31 x1 x2)?
428 * Can CLIP be done as a CSR (mode, like elwidth)
429 * SIMD saturation (etc.) also set as a mode?
430 * Include src1/src2 predication on Comparison Ops?
431 (same arrangement as C.MV, with same flexibility/power)
432 * 8/16-bit ops is it worthwhile adding a "start offset"?
433 (a bit like misaligned addressing... for registers)
434 or just use predication to skip start?
436 ## Future (extra) bank be included (made mandatory)
438 The implications of expanding the *standard* register file from
439 32 entries per bank to 64 per bank is quite an extensive architectural
440 change. Also it has implications for context-switching.
442 Therefore, on balance, it is not recommended and certainly should
443 not be made a *mandatory* requirement for the use of SV. SV's design
444 ethos is to be minimally-disruptive for implementors to shoe-horn
445 into an existing design.
447 ## How large should the Register and Predication CSR key-value stores be?
449 This is something that definitely needs actual evaluation and for
450 code to be run and the results analysed. At the time of writing
451 (12jul2018) that is too early to tell. An approximate best-guess
452 however would be 16 entries.
454 RV32E however is a special case, given that it is highly unlikely
455 (but not outside the realm of possibility) that it would be used
456 for performance reasons but instead for reducing instruction count.
457 The number of CSR entries therefore has to be considered extremely
460 ## How many CSR entries in M-Mode or S-Mode (for context-switching)?
462 The minimum required CSR entries would be 1 for each register-bank:
463 one for integer and one for floating-point. However, as shown
464 in the "Context Switch Example" section, for optimal efficiency
465 (minimal instructions in a low-latency situation) the CSRs for
466 the context-switch should be set up *and left alone*.
468 This means that it is not really a good idea to touch the CSRs
469 used for context-switching in the M-Mode (or S-Mode) trap, so
470 if there is ever demonstrated a need for vectors then there would
471 need to be *at least* one more free. However just one does not make
472 much sense (as it one only covers scalar-vector ops) so it is more
473 likely that at least two extra would be needed.
475 This *in addition* - in the RV32E case - if an RV32E implementation
476 happens also to support U/S/M modes. This would be considered quite
477 rare but not outside of the realm of possibility.
479 Conclusion: all needs careful analysis and future work.
481 ## Should use of registers be allowed to "wrap" (x30 x31 x1 x2)?
483 On balance it's a neat idea however it does seem to be one where the
484 benefits are not really clear. It would however obviate the need for
485 an exception to be raised if the VL runs out of registers to put
486 things in (gets to x31, tries a non-existent x32 and fails), however
487 the "fly in the ointment" is that x0 is hard-coded to "zero". The
488 increment therefore would need to be double-stepped to skip over x0.
489 Some microarchitectures could run into difficulties (SIMD-like ones
490 in particular) so it needs a lot more thought.
492 ## Can CLIP be done as a CSR (mode, like elwidth)
494 RVV appears to be going this way. At the time of writing (12jun2018)
495 it's noted that in V2.3-Draft V0.4 RVV Chapter, RVV intends to do
496 clip by way of exactly this method: setting a "clip mode" in a CSR.
498 No details are given however the most sensible thing to have would be
499 to extend the 16-bit Register CSR table to 24-bit (or 32-bit) and have
500 extra bits specifying the type of clipping to be carried out, on
501 a per-register basis. Other bits may be used for other purposes
502 (see SIMD saturation below)
504 ## SIMD saturation (etc.) also set as a mode?
506 Similar to "CLIP" as an extension to the CSR key-value store, "saturate"
507 may also need extra details (what the saturation maximum is for example).
509 ## Include src1/src2 predication on Comparison Ops?
511 In the C.MV (and other ops - see "C.MV Instruction"), the decision
512 was taken, unlike in ADD (etc.) which are 3-operand ops, to use
513 *both* the src *and* dest predication masks to give an extremely
514 powerful and flexible instruction that covers a huge number of
515 "traditional" vector opcodes.
517 The natural question therefore to ask is: where else could this
518 flexibility be deployed? What about comparison operations?
520 Unfortunately, C.MV is basically "regs[dest] = regs[src]" whilst
521 predicated comparison operations are actually a *three* operand
524 regs[pred] |= 1<< (cmp(regs[src1], regs[src2]) ? 1 : 0)
526 Therefore at first glance it does not make sense to use src1 and src2
527 predication masks, as it breaks the rule of 3-operand instructions
528 to use the *destination* predication register.
530 In this case however, the destination *is* a predication register
531 as opposed to being a predication mask that is applied *to* the
532 (vectorised) operation, element-at-a-time on src1 and src2.
534 Thus the question is directly inter-related to whether the modification
535 of the predication mask should *itself* be predicated.
537 It is quite complex, in other words, and needs careful consideration.
539 ## 8/16-bit ops is it worthwhile adding a "start offset"?
541 The idea here is to make it possible, particularly in a "Packed SIMD"
542 case, to be able to avoid doing unaligned Load/Store operations
543 by specifying that operations, instead of being carried out
544 element-for-element, are offset by a fixed amount *even* in 8 and 16-bit
545 element Packed SIMD cases.
547 For example rather than take 2 32-bit registers divided into 4 8-bit
548 elements and have them ADDed element-for-element as follows:
550 r3[0] = add r4[0], r6[0]
551 r3[1] = add r4[1], r6[1]
552 r3[2] = add r4[2], r6[2]
553 r3[3] = add r4[3], r6[3]
555 an offset of 1 would result in four operations as follows, instead:
557 r3[0] = add r4[1], r6[0]
558 r3[1] = add r4[2], r6[1]
559 r3[2] = add r4[3], r6[2]
560 r3[3] = add r5[0], r6[3]
562 In non-packed-SIMD mode there is no benefit at all, as a vector may
563 be created using a different CSR that has the offset built-in. So this
564 leaves just the packed-SIMD case to consider.
566 Two ways in which this could be implemented / emulated (without special
569 * bit-manipulation that shuffles the data along by one byte (or one word)
570 either prior to or as part of the operation requiring the offset.
571 * just use an unaligned Load/Store sequence, even if there are performance
572 penalties for doing so.
574 The question then is whether the performance hit is worth the extra hardware
575 involving byte-shuffling/shifting the data by an arbitrary offset. On
576 balance given that there are two reasonable instruction-based options, the
577 hardware-offset option should be left out for the initial version of SV,
578 with the option to consider it in an "advanced" version of the specification.
580 # Impementing V on top of Simple-V
582 With Simple-V converting the original RVV draft concept-for-concept
583 from explicit opcodes to implicit overloading of existing RV Standard
584 Extensions, certain features were (deliberately) excluded that need
585 to be added back in for RVV to reach its full potential. This is
586 made slightly complicated by the fact that RVV itself has two
587 levels: Base and reserved future functionality.
589 * Representation Encoding is entirely left out of Simple-V in favour of
590 implicitly taking the exact (explicit) meaning from RV Standard Extensions.
591 * VCLIP and VCLIPI do not have corresponding RV Standard Extension
592 opcodes (and are the only such operations).
593 * Extended Element bitwidths (1 through to 24576 bits) were left out
594 of Simple-V as, again, there is no corresponding RV Standard Extension
595 that covers anything even below 32-bit operands.
596 * Polymorphism was entirely left out of Simple-V due to the inherent
597 complexity of automatic type-conversion.
598 * Vector Register files were specifically left out of Simple-V in favour
599 of fitting on top of the integer and floating-point files. An
600 "RVV re-retro-fit" needs to be able to mark (implicitly marked)
601 registers as being actually in a separate *vector* register file.
602 * Fortunately in RVV (Draft 0.4, V2.3-Draft), the "base" vector
603 register file size is 5 bits (32 registers), whilst the "Extended"
604 variant of RVV specifies 8 bits (256 registers) and has yet to
606 * One big difference: Sections 17.12 and 17.17, there are only two possible
607 predication registers in RVV "Base". Through the "indirect" method,
608 Simple-V provides a key-value CSR table that allows (arbitrarily)
609 up to 16 (TBD) of either the floating-point or integer registers to
610 be marked as "predicated" (key), and if so, which integer register to
611 use as the predication mask (value).
615 # Implementing P (renamed to DSP) on top of Simple-V
617 * Implementors indicate chosen bitwidth support in Vector-bitwidth CSR
618 (caveat: anything not specified drops through to software-emulation / traps)
623 ## V-Extension to Simple-V Comparative Analysis
625 This section has been moved to its own page [[v_comparative_analysis]]
629 This section has been moved to its own page [[p_comparative_analysis]]
631 ## Comparison of "Traditional" SIMD, Alt-RVP, Simple-V and RVV Proposals <a name="parallelism_comparisons"></a>
633 This section compares the various parallelism proposals as they stand,
634 including traditional SIMD, in terms of features, ease of implementation,
635 complexity, flexibility, and die area.
637 ### [[harmonised_rvv_rvp]]
639 This is an interesting proposal under development to retro-fit the AndesStar
644 Primary benefit of Alt-RVP is the simplicity with which parallelism
645 may be introduced (effective multiplication of regfiles and associated ALUs).
647 * plus: the simplicity of the lanes (combined with the regularity of
648 allocating identical opcodes multiple independent registers) meaning
649 that SRAM or 2R1W can be used for entire regfile (potentially).
650 * minus: a more complex instruction set where the parallelism is much
651 more explicitly directly specified in the instruction and
652 * minus: if you *don't* have an explicit instruction (opcode) and you
653 need one, the only place it can be added is... in the vector unit and
654 * minus: opcode functions (and associated ALUs) duplicated in Alt-RVP are
655 not useable or accessible in other Extensions.
656 * plus-and-minus: Lanes may be utilised for high-speed context-switching
657 but with the down-side that they're an all-or-nothing part of the Extension.
658 No Alt-RVP: no fast register-bank switching.
659 * plus: Lane-switching would mean that complex operations not suited to
660 parallelisation can be carried out, followed by further parallel Lane-based
661 work, without moving register contents down to memory (and back)
662 * minus: Access to registers across multiple lanes is challenging. "Solution"
663 is to drop data into memory and immediately back in again (like MMX).
667 Primary benefit of Simple-V is the OO abstraction of parallel principles
668 from actual (internal) parallel hardware. It's an API in effect that's
669 designed to be slotted in to an existing implementation (just after
670 instruction decode) with minimum disruption and effort.
672 * minus: the complexity (if full parallelism is to be exploited)
673 of having to use register renames, OoO, VLIW, register file cacheing,
674 all of which has been done before but is a pain
675 * plus: transparent re-use of existing opcodes as-is just indirectly
676 saying "this register's now a vector" which
677 * plus: means that future instructions also get to be inherently
678 parallelised because there's no "separate vector opcodes"
679 * plus: Compressed instructions may also be (indirectly) parallelised
680 * minus: the indirect nature of Simple-V means that setup (setting
681 a CSR register to indicate vector length, a separate one to indicate
682 that it is a predicate register and so on) means a little more setup
683 time than Alt-RVP or RVV's "direct and within the (longer) instruction"
685 * plus: shared register file meaning that, like Alt-RVP, complex
686 operations not suited to parallelisation may be carried out interleaved
687 between parallelised instructions *without* requiring data to be dropped
688 down to memory and back (into a separate vectorised register engine).
689 * plus-and-maybe-minus: re-use of integer and floating-point 32-wide register
690 files means that huge parallel workloads would use up considerable
691 chunks of the register file. However in the case of RV64 and 32-bit
692 operations, that effectively means 64 slots are available for parallel
694 * plus: inherent parallelism (actual parallel ALUs) doesn't actually need to
695 be added, yet the instruction opcodes remain unchanged (and still appear
696 to be parallel). consistent "API" regardless of actual internal parallelism:
697 even an in-order single-issue implementation with a single ALU would still
698 appear to have parallel vectoristion.
699 * hard-to-judge: if actual inherent underlying ALU parallelism is added it's
700 hard to say if there would be pluses or minuses (on die area). At worse it
701 would be "no worse" than existing register renaming, OoO, VLIW and register
702 file cacheing schemes.
704 ### RVV (as it stands, Draft 0.4 Section 17, RISC-V ISA V2.3-Draft)
706 RVV is extremely well-designed and has some amazing features, including
707 2D reorganisation of memory through LOAD/STORE "strides".
709 * plus: regular predictable workload means that implementations may
710 streamline effects on L1/L2 Cache.
711 * plus: regular and clear parallel workload also means that lanes
712 (similar to Alt-RVP) may be used as an implementation detail,
713 using either SRAM or 2R1W registers.
714 * plus: separate engine with no impact on the rest of an implementation
715 * minus: separate *complex* engine with no RTL (ALUs, Pipeline stages) reuse
717 * minus: no ISA abstraction or re-use either: additions to other Extensions
718 do not gain parallelism, resulting in prolific duplication of functionality
719 inside RVV *and out*.
720 * minus: when operations require a different approach (scalar operations
721 using the standard integer or FP regfile) an entire vector must be
722 transferred out to memory, into standard regfiles, then back to memory,
723 then back to the vector unit, this to occur potentially multiple times.
724 * minus: will never fit into Compressed instruction space (as-is. May
725 be able to do so if "indirect" features of Simple-V are partially adopted).
726 * plus-and-slight-minus: extended variants may address up to 256
727 vectorised registers (requires 48/64-bit opcodes to do it).
728 * minus-and-partial-plus: separate engine plus complexity increases
729 implementation time and die area, meaning that adoption is likely only
730 to be in high-performance specialist supercomputing (where it will
731 be absolutely superb).
735 The only really good things about SIMD are how easy it is to implement and
736 get good performance. Unfortunately that makes it quite seductive...
738 * plus: really straightforward, ALU basically does several packed operations
739 at once. Parallelism is inherent at the ALU, making the addition of
740 SIMD-style parallelism an easy decision that has zero significant impact
741 on the rest of any given architectural design and layout.
742 * plus (continuation): SIMD in simple in-order single-issue designs can
743 therefore result in superb throughput, easily achieved even with a very
744 simple execution model.
745 * minus: ridiculously complex setup and corner-cases that disproportionately
746 increase instruction count on what would otherwise be a "simple loop",
747 should the number of elements in an array not happen to exactly match
748 the SIMD group width.
749 * minus: getting data usefully out of registers (if separate regfiles
750 are used) means outputting to memory and back.
751 * minus: quite a lot of supplementary instructions for bit-level manipulation
752 are needed in order to efficiently extract (or prepare) SIMD operands.
753 * minus: MASSIVE proliferation of ISA both in terms of opcodes in one
754 dimension and parallelism (width): an at least O(N^2) and quite probably
755 O(N^3) ISA proliferation that often results in several thousand
756 separate instructions. all requiring separate and distinct corner-case
758 * minus: EVEN BIGGER proliferation of SIMD ISA if the functionality of
759 8, 16, 32 or 64-bit reordering is built-in to the SIMD instruction.
760 For example: add (high|low) 16-bits of r1 to (low|high) of r2 requires
761 four separate and distinct instructions: one for (r1:low r2:high),
762 one for (r1:high r2:low), one for (r1:high r2:high) and one for
763 (r1:low r2:low) *per function*.
764 * minus: EVEN BIGGER proliferation of SIMD ISA if there is a mismatch
765 between operand and result bit-widths. In combination with high/low
766 proliferation the situation is made even worse.
767 * minor-saving-grace: some implementations *may* have predication masks
768 that allow control over individual elements within the SIMD block.
770 ## Comparison *to* Traditional SIMD: Alt-RVP, Simple-V and RVV Proposals <a name="simd_comparison"></a>
772 This section compares the various parallelism proposals as they stand,
773 *against* traditional SIMD as opposed to *alongside* SIMD. In other words,
774 the question is asked "How can each of the proposals effectively implement
775 (or replace) SIMD, and how effective would they be"?
779 * Alt-RVP would not actually replace SIMD but would augment it: just as with
780 a SIMD architecture where the ALU becomes responsible for the parallelism,
781 Alt-RVP ALUs would likewise be so responsible... with *additional*
782 (lane-based) parallelism on top.
783 * Thus at least some of the downsides of SIMD ISA O(N^5) proliferation by
784 at least one dimension are avoided (architectural upgrades introducing
785 128-bit then 256-bit then 512-bit variants of the exact same 64-bit
787 * Thus, unfortunately, Alt-RVP would suffer the same inherent proliferation
788 of instructions as SIMD, albeit not quite as badly (due to Lanes).
789 * In the same discussion for Alt-RVP, an additional proposal was made to
790 be able to subdivide the bits of each register lane (columns) down into
791 arbitrary bit-lengths (RGB 565 for example).
792 * A recommendation was given instead to make the subdivisions down to 32-bit,
793 16-bit or even 8-bit, effectively dividing the registerfile into
794 Lane0(H), Lane0(L), Lane1(H) ... LaneN(L) or further. If inter-lane
795 "swapping" instructions were then introduced, some of the disadvantages
796 of SIMD could be mitigated.
800 * RVV is designed to replace SIMD with a better paradigm: arbitrary-length
802 * However whilst SIMD is usually designed for single-issue in-order simple
803 DSPs with a focus on Multimedia (Audio, Video and Image processing),
804 RVV's primary focus appears to be on Supercomputing: optimisation of
805 mathematical operations that fit into the OpenCL space.
806 * Adding functions (operations) that would normally fit (in parallel)
807 into a SIMD instruction requires an equivalent to be added to the
808 RVV Extension, if one does not exist. Given the specialist nature of
809 some SIMD instructions (8-bit or 16-bit saturated or halving add),
810 this possibility seems extremely unlikely to occur, even if the
811 implementation overhead of RVV were acceptable (compared to
812 normal SIMD/DSP-style single-issue in-order simplicity).
816 * Simple-V borrows hugely from RVV as it is intended to be easy to
817 topologically transplant every single instruction from RVV (as
818 designed) into Simple-V equivalents, with *zero loss of functionality
820 * With the "parallelism" abstracted out, a hypothetical SIMD-less "DSP"
821 Extension which contained the basic primitives (non-parallelised
822 8, 16 or 32-bit SIMD operations) inherently *become* parallel,
824 * Additionally, standard operations (ADD, MUL) that would normally have
825 to have special SIMD-parallel opcodes added need no longer have *any*
826 of the length-dependent variants (2of 32-bit ADDs in a 64-bit register,
827 4of 32-bit ADDs in a 128-bit register) because Simple-V takes the
828 *standard* RV opcodes (present and future) and automatically parallelises
830 * By inheriting the RVV feature of arbitrary vector-length, then just as
831 with RVV the corner-cases and ISA proliferation of SIMD is avoided.
832 * Whilst not entirely finalised, registers are expected to be
833 capable of being subdivided down to an implementor-chosen bitwidth
834 in the underlying hardware (r1 becomes r1[31..24] r1[23..16] r1[15..8]
835 and r1[7..0], or just r1[31..16] r1[15..0]) where implementors can
836 choose to have separate independent 8-bit ALUs or dual-SIMD 16-bit
837 ALUs that perform twin 8-bit operations as they see fit, or anything
838 else including no subdivisions at all.
839 * Even though implementors have that choice even to have full 64-bit
840 (with RV64) SIMD, they *must* provide predication that transparently
841 switches off appropriate units on the last loop, thus neatly fitting
842 underlying SIMD ALU implementations *into* the arbitrary vector-length
843 RVV paradigm, keeping the uniform consistent API that is a key strategic
845 * With Simple-V fitting into the standard register files, certain classes
846 of SIMD operations such as High/Low arithmetic (r1[31..16] + r2[15..0])
847 can be done by applying *Parallelised* Bit-manipulation operations
848 followed by parallelised *straight* versions of element-to-element
849 arithmetic operations, even if the bit-manipulation operations require
850 changing the bitwidth of the "vectors" to do so. Predication can
851 be utilised to skip high words (or low words) in source or destination.
852 * In essence, the key downside of SIMD - massive duplication of
853 identical functions over time as an architecture evolves from 32-bit
854 wide SIMD all the way up to 512-bit, is avoided with Simple-V, through
855 vector-style parallelism being dropped on top of 8-bit or 16-bit
856 operations, all the while keeping a consistent ISA-level "API" irrespective
857 of implementor design choices (or indeed actual implementations).
859 ### Example Instruction translation: <a name="example_translation"></a>
861 Instructions "ADD r7 r4 r4" would result in three instructions being
862 generated and placed into the FIFO. r7 and r4 are marked as "vectorised":
868 Instructions "ADD r7 r4 r1" would result in three instructions being
869 generated and placed into the FIFO. r7 and r1 are marked as "vectorised"
876 ## Example of vector / vector, vector / scalar, scalar / scalar => vector add
878 function op_add(rd, rs1, rs2) # add not VADD!
879 int i, id=0, irs1=0, irs2=0;
880 rd = int_vec[rd ].isvector ? int_vec[rd ].regidx : rd;
881 rs1 = int_vec[rs1].isvector ? int_vec[rs1].regidx : rs1;
882 rs2 = int_vec[rs2].isvector ? int_vec[rs2].regidx : rs2;
883 predval = get_pred_val(FALSE, rd);
884 for (i = 0; i < VL; i++)
885 if (predval & 1<<i) # predication uses intregs
886 ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
887 if (int_vec[rd ].isvector) { id += 1; }
888 if (int_vec[rs1].isvector) { irs1 += 1; }
889 if (int_vec[rs2].isvector) { irs2 += 1; }
891 ## Retro-fitting Predication into branch-explicit ISA <a name="predication_retrofit"></a>
893 One of the goals of this parallelism proposal is to avoid instruction
894 duplication. However, with the base ISA having been designed explictly
895 to *avoid* condition-codes entirely, shoe-horning predication into it
896 bcomes quite challenging.
898 However what if all branch instructions, if referencing a vectorised
899 register, were instead given *completely new analogous meanings* that
900 resulted in a parallel bit-wise predication register being set? This
901 would have to be done for both C.BEQZ and C.BNEZ, as well as BEQ, BNE,
904 We might imagine that FEQ, FLT and FLT would also need to be converted,
905 however these are effectively *already* in the precise form needed and
906 do not need to be converted *at all*! The difference is that FEQ, FLT
907 and FLE *specifically* write a 1 to an integer register if the condition
908 holds, and 0 if not. All that needs to be done here is to say, "if
909 the integer register is tagged with a bit that says it is a predication
910 register, the **bit** in the integer register is set based on the
911 current vector index" instead.
913 There is, in the standard Conditional Branch instruction, more than
914 adequate space to interpret it in a similar fashion:
917 31 |30 ..... 25 |24..20|19..15| 14...12| 11.....8 | 7 | 6....0 |
918 imm[12] | imm[10:5] |rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode |
919 1 | 6 | 5 | 5 | 3 | 4 | 1 | 7 |
920 offset[12,10:5] || src2 | src1 | BEQ | offset[11,4:1] || BRANCH |
926 31 | 30 .. 25 |24 ... 20 | 19 15 | 14 12 | 11 .. 8 | 7 | 6 ... 0 |
927 imm[12] | imm[10:5]| rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode |
928 1 | 6 | 5 | 5 | 3 | 4 | 1 | 7 |
929 reserved || src2 | src1 | BEQ | predicate rs3 || BRANCH |
932 Similarly the C.BEQZ and C.BNEZ instruction format may be retro-fitted,
933 with the interesting side-effect that there is space within what is presently
934 the "immediate offset" field to reinterpret that to add in not only a bit
935 field to distinguish between floating-point compare and integer compare,
936 not only to add in a second source register, but also use some of the bits as
937 a predication target as well.
940 15..13 | 12 ....... 10 | 9...7 | 6 ......... 2 | 1 .. 0 |
941 funct3 | imm | rs10 | imm | op |
943 C.BEQZ | offset[8,4:3] | src | offset[7:6,2:1,5] | C1 |
946 Now uses the CS format:
949 15..13 | 12 . 10 | 9 .. 7 | 6 .. 5 | 4..2 | 1 .. 0 |
950 funct3 | imm | rs10 | imm | | op |
951 3 | 3 | 3 | 2 | 3 | 2 |
952 C.BEQZ | pred rs3 | src1 | I/F B | src2 | C1 |
955 Bit 6 would be decoded as "operation refers to Integer or Float" including
956 interpreting src1 and src2 accordingly as outlined in Table 12.2 of the
957 "C" Standard, version 2.0,
958 whilst Bit 5 would allow the operation to be extended, in combination with
959 funct3 = 110 or 111: a combination of four distinct (predicated) comparison
960 operators. In both floating-point and integer cases those could be
961 EQ/NEQ/LT/LE (with GT and GE being synthesised by inverting src1 and src2).
963 ## Register reordering <a name="register_reordering"></a>
982 May not be an actual CSR: may be generated from Vector Length CSR:
983 single-bit is less burdensome on instruction decode phase.
985 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
986 | - | - | - | - | - | - | - | - |
987 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
989 ### Vector Length CSR
1002 ### Virtual Register Reordering
1004 This example assumes the above Vector Length CSR table
1006 | Reg Num | Bits (0) | Bits (1) | Bits (2) |
1007 | ------- | -------- | -------- | -------- |
1008 | r0 | (32..0) | (32..0) |
1011 | r4 | (32..0) | (32..0) | (32..0) |
1014 ### Bitwidth Virtual Register Reordering
1016 This example goes a little further and illustrates the effect that a
1017 bitwidth CSR has been set on a register. Preconditions:
1020 * CSRintbitwidth[2] = 010 # integer r2 is 16-bit
1021 * CSRintvlength[2] = 3 # integer r2 is a vector of length 3
1022 * vsetl rs1, 5 # set the vector length to 5
1024 This is interpreted as follows:
1026 * Given that the context is RV32, ELEN=32.
1027 * With ELEN=32 and bitwidth=16, the number of SIMD elements is 2
1028 * Therefore the actual vector length is up to *six* elements
1029 * However vsetl sets a length 5 therefore the last "element" is skipped
1031 So when using an operation that uses r2 as a source (or destination)
1032 the operation is carried out as follows:
1034 * 16-bit operation on r2(15..0) - vector element index 0
1035 * 16-bit operation on r2(31..16) - vector element index 1
1036 * 16-bit operation on r3(15..0) - vector element index 2
1037 * 16-bit operation on r3(31..16) - vector element index 3
1038 * 16-bit operation on r4(15..0) - vector element index 4
1039 * 16-bit operation on r4(31..16) **NOT** carried out due to length being 5
1041 Predication has been left out of the above example for simplicity, however
1042 predication is ANDed with the latter stages (vsetl not equal to maximum
1045 Note also that it is entirely an implementor's choice as to whether to have
1046 actual separate ALUs down to the minimum bitwidth, or whether to have something
1047 more akin to traditional SIMD (at any level of subdivision: 8-bit SIMD
1048 operations carried out 32-bits at a time is perfectly acceptable, as is
1049 8-bit SIMD operations carried out 16-bits at a time requiring two ALUs).
1050 Regardless of the internal parallelism choice, *predication must
1051 still be respected*, making Simple-V in effect the "consistent public API".
1053 vew may be one of the following (giving a table "bytestable", used below):
1055 | vew | bitwidth | bytestable |
1056 | --- | -------- | ---------- |
1057 | 000 | default | XLEN/8 |
1063 | 110 | rsvd | rsvd |
1064 | 111 | rsvd | rsvd |
1066 Pseudocode for vector length taking CSR SIMD-bitwidth into account:
1068 vew = CSRbitwidth[rs1]
1070 bytesperreg = (XLEN/8) # or FLEN as appropriate
1072 bytesperreg = bytestable[vew] # 1 2 4 8 16
1073 simdmult = (XLEN/8) / bytesperreg # or FLEN as appropriate
1074 vlen = CSRvectorlen[rs1] * simdmult
1076 To index an element in a register rnum where the vector element index is i:
1078 function regoffs(rnum, i):
1079 regidx = floor(i / simdmult) # integer-div rounded down
1080 byteidx = i % simdmult # integer-remainder
1081 return rnum + regidx, # actual real register
1083 byteidx * 8 + (vew-1), # high
1087 SIMD register file splitting still to consider. For RV64, benefits of doubling
1088 (quadrupling in the case of Half-Precision IEEE754 FP) the apparent
1089 size of the floating point register file to 64 (128 in the case of HP)
1090 seem pretty clear and worth the complexity.
1092 64 virtual 32-bit F.P. registers and given that 32-bit FP operations are
1093 done on 64-bit registers it's not so conceptually difficult. May even
1094 be achieved by *actually* splitting the regfile into 64 virtual 32-bit
1095 registers such that a 64-bit FP scalar operation is dropped into (r0.H
1096 r0.L) tuples. Implementation therefore hidden through register renaming.
1098 Implementations intending to introduce VLIW, OoO and parallelism
1099 (even without Simple-V) would then find that the instructions are
1100 generated quicker (or in a more compact fashion that is less heavy
1101 on caches). Interestingly we observe then that Simple-V is about
1102 "consolidation of instruction generation", where actual parallelism
1103 of underlying hardware is an implementor-choice that could just as
1104 equally be applied *without* Simple-V even being implemented.
1106 ## Analysis of CSR decoding on latency <a name="csr_decoding_analysis"></a>
1108 It could indeed have been logically deduced (or expected), that there
1109 would be additional decode latency in this proposal, because if
1110 overloading the opcodes to have different meanings, there is guaranteed
1111 to be some state, some-where, directly related to registers.
1113 There are several cases:
1115 * All operands vector-length=1 (scalars), all operands
1116 packed-bitwidth="default": instructions are passed through direct as if
1117 Simple-V did not exist. Simple-V is, in effect, completely disabled.
1118 * At least one operand vector-length > 1, all operands
1119 packed-bitwidth="default": any parallel vector ALUs placed on "alert",
1120 virtual parallelism looping may be activated.
1121 * All operands vector-length=1 (scalars), at least one
1122 operand packed-bitwidth != default: degenerate case of SIMD,
1123 implementation-specific complexity here (packed decode before ALUs or
1125 * At least one operand vector-length > 1, at least one operand
1126 packed-bitwidth != default: parallel vector ALUs (if any)
1127 placed on "alert", virtual parallelsim looping may be activated,
1128 implementation-specific SIMD complexity kicks in (packed decode before
1131 Bear in mind that the proposal includes that the decision whether
1132 to parallelise in hardware or whether to virtual-parallelise (to
1133 dramatically simplify compilers and also not to run into the SIMD
1134 instruction proliferation nightmare) *or* a transprent combination
1135 of both, be done on a *per-operand basis*, so that implementors can
1136 specifically choose to create an application-optimised implementation
1137 that they believe (or know) will sell extremely well, without having
1138 "Extra Standards-Mandated Baggage" that would otherwise blow their area
1139 or power budget completely out the window.
1141 Additionally, two possible CSR schemes have been proposed, in order to
1142 greatly reduce CSR space:
1144 * per-register CSRs (vector-length and packed-bitwidth)
1145 * a smaller number of CSRs with the same information but with an *INDEX*
1146 specifying WHICH register in one of three regfiles (vector, fp, int)
1147 the length and bitwidth applies to.
1149 (See "CSR vector-length and CSR SIMD packed-bitwidth" section for details)
1151 In addition, LOAD/STORE has its own associated proposed CSRs that
1152 mirror the STRIDE (but not yet STRIDE-SEGMENT?) functionality of
1155 Also bear in mind that, for reasons of simplicity for implementors,
1156 I was coming round to the idea of permitting implementors to choose
1157 exactly which bitwidths they would like to support in hardware and which
1158 to allow to fall through to software-trap emulation.
1160 So the question boils down to:
1162 * whether either (or both) of those two CSR schemes have significant
1163 latency that could even potentially require an extra pipeline decode stage
1164 * whether there are implementations that can be thought of which do *not*
1165 introduce significant latency
1166 * whether it is possible to explicitly (through quite simply
1167 disabling Simple-V-Ext) or implicitly (detect the case all-vlens=1,
1168 all-simd-bitwidths=default) switch OFF any decoding, perhaps even to
1169 the extreme of skipping an entire pipeline stage (if one is needed)
1170 * whether packed bitwidth and associated regfile splitting is so complex
1171 that it should definitely, definitely be made mandatory that implementors
1172 move regfile splitting into the ALU, and what are the implications of that
1173 * whether even if that *is* made mandatory, is software-trapped
1174 "unsupported bitwidths" still desirable, on the basis that SIMD is such
1175 a complete nightmare that *even* having a software implementation is
1176 better, making Simple-V have more in common with a software API than
1179 Whilst the above may seem to be severe minuses, there are some strong
1182 * Significant reduction of V's opcode space: over 95%.
1183 * Smaller reduction of P's opcode space: around 10%.
1184 * The potential to use Compressed instructions in both Vector and SIMD
1185 due to the overloading of register meaning (implicit vectorisation,
1187 * Not only present but also future extensions automatically gain parallelism.
1188 * Already mentioned but worth emphasising: the simplification to compiler
1189 writers and assembly-level writers of having the same consistent ISA
1190 regardless of whether the internal level of parallelism (number of
1191 parallel ALUs) is only equal to one ("virtual" parallelism), or is
1192 greater than one, should not be underestimated.
1194 ## Reducing Register Bank porting
1196 This looks quite reasonable.
1197 <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>
1199 The main details are outlined on page 4. They propose a 2-level register
1200 cache hierarchy, note that registers are typically only read once, that
1201 you never write back from upper to lower cache level but always go in a
1202 cycle lower -> upper -> ALU -> lower, and at the top of page 5 propose
1203 a scheme where you look ahead by only 2 instructions to determine which
1204 registers to bring into the cache.
1206 The nice thing about a vector architecture is that you *know* that
1207 *even more* registers are going to be pulled in: Hwacha uses this fact
1208 to optimise L1/L2 cache-line usage (avoid thrashing), strangely enough
1209 by *introducing* deliberate latency into the execution phase.
1211 ## Overflow registers in combination with predication
1213 **TODO**: propose overflow registers be actually one of the integer regs
1214 (flowing to multiple regs).
1216 **TODO**: propose "mask" (predication) registers likewise. combination with
1217 standard RV instructions and overflow registers extremely powerful, see
1220 When integer overflow is stored in an easily-accessible bit (or another
1221 register), parallelisation turns this into a group of bits which can
1222 potentially be interacted with in predication, in interesting and powerful
1223 ways. For example, by taking the integer-overflow result as a predication
1224 field and shifting it by one, a predicated vectorised "add one" can emulate
1225 "carry" on arbitrary (unlimited) length addition.
1227 However despite RVV having made room for floating-point exceptions, neither
1228 RVV nor base RV have taken integer-overflow (carry) into account, which
1229 makes proposing it quite challenging given that the relevant (Base) RV
1230 sections are frozen. Consequently it makes sense to forgo this feature.
1232 ## Context Switch Example <a name="context_switch"></a>
1234 An unusual side-effect of Simple-V mapping onto the standard register files
1235 is that LOAD-multiple and STORE-multiple are accidentally available, as long
1236 as it is acceptable that the register(s) to be loaded/stored are contiguous
1237 (per instruction). An additional accidental benefit is that Compressed LD/ST
1240 To illustrate how this works, here is some example code from FreeRTOS
1241 (GPLv2 licensed, portasm.S):
1243 /* Macro for saving task context */
1244 .macro portSAVE_CONTEXT
1245 .global pxCurrentTCB
1246 /* make room in stack */
1247 addi sp, sp, -REGBYTES * 32
1251 STORE x2, 1 * REGBYTES(sp)
1252 STORE x3, 2 * REGBYTES(sp)
1255 STORE x30, 29 * REGBYTES(sp)
1256 STORE x31, 30 * REGBYTES(sp)
1258 /* Store current stackpointer in task control block (TCB) */
1259 LOAD t0, pxCurrentTCB //pointer
1263 /* Saves current error program counter (EPC) as task program counter */
1266 STORE t0, 31 * REGBYTES(sp)
1269 /* Saves current return adress (RA) as task program counter */
1271 STORE ra, 31 * REGBYTES(sp)
1274 /* Macro for restoring task context */
1275 .macro portRESTORE_CONTEXT
1277 .global pxCurrentTCB
1278 /* Load stack pointer from the current TCB */
1279 LOAD sp, pxCurrentTCB
1282 /* Load task program counter */
1283 LOAD t0, 31 * REGBYTES(sp)
1286 /* Run in machine mode */
1290 /* Restore registers,
1291 Skip global pointer because that does not change */
1293 LOAD x4, 3 * REGBYTES(sp)
1294 LOAD x5, 4 * REGBYTES(sp)
1297 LOAD x30, 29 * REGBYTES(sp)
1298 LOAD x31, 30 * REGBYTES(sp)
1300 addi sp, sp, REGBYTES * 32
1304 The important bits are the Load / Save context, which may be replaced
1305 with firstly setting up the Vectors and secondly using a *single* STORE
1306 (or LOAD) including using C.ST or C.LD, to indicate that the entire
1307 bank of registers is to be loaded/saved:
1309 /* a few things are assumed here: (a) that when switching to
1310 M-Mode an entirely different set of CSRs is used from that
1311 which is used in U-Mode and (b) that the M-Mode x1 and x4
1312 vectors are also not used anywhere else in M-Mode, consequently
1313 only need to be set up just the once.
1316 MVECTORCSRx1 = 31, defaultlen
1317 MVECTORCSRx4 = 28, defaultlen
1320 SETVL x0, x0, 31 /* x0 ignored silently */
1321 STORE x1, 0x0(sp) // x1 marked as 31-long vector of default bitwidth
1323 /* Restore registers,
1324 Skip global pointer because that does not change */
1326 SETVL x0, x0, 28 /* x0 ignored silently */
1327 LOAD x4, 3 * REGBYTES(sp) // x4 marked as 28-long default bitwidth
1329 Note that although it may just be a bug in portasm.S, x2 and x3 appear not
1330 to be being restored. If however this is a bug and they *do* need to be
1331 restored, then the SETVL call may be moved to *outside* the Save / Restore
1332 Context assembly code, into the macroVectorSetup, as long as vectors are
1333 never used anywhere else (i.e. VL is never altered by M-Mode).
1335 In effect the entire bank of repeated LOAD / STORE instructions is replaced
1336 by one single (compressed if it is available) instruction.
1338 ## Virtual Memory page-faults on LOAD/STORE
1341 ### Notes from conversations
1343 > I was going through the C.LOAD / C.STORE section 12.3 of V2.3-Draft
1344 > riscv-isa-manual in order to work out how to re-map RVV onto the standard
1345 > ISA, and came across an interesting comments at the bottom of pages 75
1348 > " A common mechanism used in other ISAs to further reduce save/restore
1349 > code size is load- multiple and store-multiple instructions. "
1351 > Fascinatingly, due to Simple-V proposing to use the *standard* register
1352 > file, both C.LOAD / C.STORE *and* LOAD / STORE would in effect be exactly
1353 > that: load-multiple and store-multiple instructions. Which brings us
1354 > on to this comment:
1356 > "For virtual memory systems, some data accesses could be resident in
1357 > physical memory and
1358 > some could not, which requires a new restart mechanism for partially
1359 > executed instructions."
1361 > Which then of course brings us to the interesting question: how does RVV
1362 > cope with the scenario when, particularly with LD.X (Indexed / indirect
1363 > loads), part-way through the loading a page fault occurs?
1365 > Has this been noted or discussed before?
1367 For applications-class platforms, the RVV exception model is
1368 element-precise (that is, if an exception occurs on element j of a
1369 vector instruction, elements 0..j-1 have completed execution and elements
1370 j+1..vl-1 have not executed).
1372 Certain classes of embedded platforms where exceptions are always fatal
1373 might choose to offer resumable/swappable interrupts but not precise
1377 > Is RVV designed in any way to be re-entrant?
1382 > What would the implications be for instructions that were in a FIFO at
1383 > the time, in out-of-order and VLIW implementations, where partial decode
1386 The usual bag of tricks for maintaining precise exceptions applies to
1387 vector machines as well. Register renaming makes the job easier, and
1388 it's relatively cheaper for vectors, since the control cost is amortized
1389 over longer registers.
1392 > Would it be reasonable at least to say *bypass* (and freeze) the
1393 > instruction FIFO (drop down to a single-issue execution model temporarily)
1394 > for the purposes of executing the instructions in the interrupt (whilst
1395 > setting up the VM page), then re-continue the instruction with all
1398 This approach has been done successfully, but it's desirable to be
1399 able to swap out the vector unit state to support context switches on
1400 exceptions that result in long-latency I/O.
1403 > Or would it be better to switch to an entirely separate secondary
1404 > hyperthread context?
1406 > Does anyone have any ideas or know if there is any academic literature
1407 > on solutions to this problem?
1409 The Vector VAX offered imprecise but restartable and swappable exceptions:
1410 http://mprc.pku.edu.cn/~liuxianhua/chn/corpus/Notes/articles/isca/1990/VAX%20vector%20architecture.pdf
1412 Sec. 4.6 of Krste's dissertation assesses some of
1413 the tradeoffs and references a bunch of related work:
1414 http://people.eecs.berkeley.edu/~krste/thesis.pdf
1419 Started reading section 4.6 of Krste's thesis, noted the "IEE85 F.P
1420 exceptions" and thought, "hmmm that could go into a CSR, must re-read
1421 the section on FP state CSRs in RVV 0.4-Draft again" then i suddenly
1422 thought, "ah ha! what if the memory exceptions were, instead of having
1423 an immediate exception thrown, were simply stored in a type of predication
1424 bit-field with a flag "error this element failed"?
1426 Then, *after* the vector load (or store, or even operation) was
1427 performed, you could *then* raise an exception, at which point it
1428 would be possible (yes in software... I know....) to go "hmmm, these
1429 indexed operations didn't work, let's get them into memory by triggering
1430 page-loads", then *re-run the entire instruction* but this time with a
1431 "memory-predication CSR" that stops the already-performed operations
1432 (whether they be loads, stores or an arithmetic / FP operation) from
1433 being carried out a second time.
1435 This theoretically could end up being done multiple times in an SMP
1436 environment, and also for LD.X there would be the remote outside annoying
1437 possibility that the indexed memory address could end up being modified.
1439 The advantage would be that the order of execution need not be
1440 sequential, which potentially could have some big advantages.
1441 Am still thinking through the implications as any dependent operations
1442 (particularly ones already decoded and moved into the execution FIFO)
1443 would still be there (and stalled). hmmm.
1447 > > # assume internal parallelism of 8 and MAXVECTORLEN of 8
1452 > > x3[1]: exception
1458 > > what happens to result elements 2-7? those may be *big* results
1460 > > or in the RVV-Extended may be arbitrary bit-widths far greater.
1466 discussion then led to the question of OoO architectures
1468 > The costs of the imprecise-exception model are greater than the benefit.
1469 > Software doesn't want to cope with it. It's hard to debug. You can't
1470 > migrate state between different microarchitectures--unless you force all
1471 > implementations to support the same imprecise-exception model, which would
1472 > greatly limit implementation flexibility. (Less important, but still
1473 > relevant, is that the imprecise model increases the size of the context
1474 > structure, as the microarchitectural guts have to be spilled to memory.)
1476 ## Zero/Non-zero Predication
1478 >> > it just occurred to me that there's another reason why the data
1479 >> > should be left instead of zeroed. if the standard register file is
1480 >> > used, such that vectorised operations are translated to mean "please
1481 >> > insert multiple register-contiguous operations into the instruction
1482 >> > FIFO" and predication is used to *skip* some of those, then if the
1483 >> > next "vector" operation uses the (standard) registers that were masked
1484 >> > *out* of the previous operation it may proceed without blocking.
1486 >> > if however zeroing is made mandatory then that optimisation becomes
1487 >> > flat-out impossible to deploy.
1489 >> > whilst i haven't fully thought through the full implications, i
1490 >> > suspect RVV might also be able to benefit by being able to fit more
1491 >> > overlapping operations into the available SRAM by doing something
1495 > Luke, this is called density time masking. It doesn’t apply to only your
1496 > model with the “standard register file” is used. it applies to any
1497 > architecture that attempts to speed up by skipping computation and writeback
1498 > of masked elements.
1500 > That said, the writing of zeros need not be explicit. It is possible to add
1501 > a “zero bit” per element that, when set, forces a zero to be read from the
1502 > vector (although the underlying storage may have old data). In this case,
1503 > there may be a way to implement DTM as well.
1506 ## Implementation detail for scalar-only op detection <a name="scalar_detection"></a>
1508 Note 1: this idea is a pipeline-bypass concept, which may *or may not* be
1511 Note 2: this is just one possible implementation. Another implementation
1512 may choose to treat *all* operations as vectorised (including treating
1513 scalars as vectors of length 1), choosing to add an extra pipeline stage
1514 dedicated to *all* instructions.
1516 This section *specifically* covers the implementor's freedom to choose
1517 that they wish to minimise disruption to an existing design by detecting
1518 "scalar-only operations", bypassing the vectorisation phase (which may
1519 or may not require an additional pipeline stage)
1521 [[scalardetect.png]]
1523 >> For scalar ops an implementation may choose to compare 2-3 bits through an
1524 >> AND gate: are src & dest scalar? Yep, ok send straight to ALU (or instr
1527 > Those bits cannot be known until after the registers are decoded from the
1528 > instruction and a lookup in the "vector length table" has completed.
1529 > Considering that one of the reasons RISC-V keeps registers in invariant
1530 > positions across all instructions is to simplify register decoding, I expect
1531 > that inserting an SRAM read would lengthen the critical path in most
1536 > briefly: the trick i mentioned about ANDing bits together to check if
1537 > an op was fully-scalar or not was to be read out of a single 32-bit
1538 > 3R1W SRAM (64-bit if FPU exists). the 32/64-bit SRAM contains 1 bit per
1539 > register indicating "is register vectorised yes no". 3R because you need
1540 > to check src1, src2 and dest simultaneously. the entries are *generated*
1541 > from the CSRs and are an optimisation that on slower embedded systems
1542 > would likely not be needed.
1544 > is there anything unreasonable that anyone can foresee about that?
1545 > what are the down-sides?
1547 ## C.MV predicated src, predicated dest
1549 > Can this be usefully defined in such a way that it is
1550 > equivalent to vector gather-scatter on each source, followed by a
1551 > non-predicated vector-compare, followed by vector gather-scatter on the
1554 ## element width conversion: restrict or remove?
1556 summary: don't restrict / remove. it's fine.
1558 > > it has virtually no cost/overhead as long as you specify
1559 > > that inputs can only upconvert, and operations are always done at the
1560 > > largest size, and downconversion only happens at the output.
1562 > okaaay. so that's a really good piece of implementation advice.
1563 > algorithms do require data size conversion, so at some point you need to
1564 > introduce the feature of upconverting and downconverting.
1566 > > for int and uint, this is dead simple and fits well within the RVV pipeline
1567 > > without any critical path, pipeline depth, or area implications.
1569 <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/g3feFnAoKIM>
1571 ## Under review / discussion: remove CSR vector length, use VSETVL <a name="vsetvl"></a>
1573 **DECISION: 11jun2018 - CSR vector length removed, VSETVL determines
1574 length on all regs**. This section kept for historical reasons.
1576 So the issue is as follows:
1578 * CSRs are used to set the "span" of a vector (how many of the standard
1579 register file to contiguously use)
1580 * VSETVL in RVV works as follows: it sets the vector length (copy of which
1581 is placed in a dest register), and if the "required" length is longer
1582 than the *available* length, the dest reg is set to the MIN of those
1584 * **HOWEVER**... in SV, *EVERY* vector register has its own separate
1585 length and thus there is no way (at the time that VSETVL is called) to
1586 know what to set the vector length *to*.
1587 * At first glance it seems that it would be perfectly fine to just limit
1588 the vector operation to the length specified in the destination
1589 register's CSR, at the time that each instruction is issued...
1590 except that that cannot possibly be guaranteed to match
1591 with the value *already loaded into the target register from VSETVL*.
1593 Therefore a different approach is needed.
1595 Possible options include:
1597 * Removing the CSR "Vector Length" and always using the value from
1598 VSETVL. "VSETVL destreg, counterreg, #lenimmed" will set VL *and*
1599 destreg equal to MIN(counterreg, lenimmed), with register-based
1600 variant "VSETVL destreg, counterreg, lenreg" doing the same.
1601 * Keeping the CSR "Vector Length" and having the lenreg version have
1602 a "twist": "if lengreg is vectorised, read the length from the CSR"
1605 The first option (of the ones brainstormed so far) is a lot simpler.
1606 It does however mean that the length set in VSETVL will apply across-the-board
1607 to all src1, src2 and dest vectorised registers until it is otherwise changed
1608 (by another VSETVL call). This is probably desirable behaviour.
1610 ## Implementation Paradigms <a name="implementation_paradigms"></a>
1612 TODO: assess various implementation paradigms. These are listed roughly
1613 in order of simplicity (minimum compliance, for ultra-light-weight
1614 embedded systems or to reduce design complexity and the burden of
1615 design implementation and compliance, in non-critical areas), right the
1616 way to high-performance systems.
1618 * Full (or partial) software-emulated (via traps): full support for CSRs
1619 required, however when a register is used that is detected (in hardware)
1620 to be vectorised, an exception is thrown.
1621 * Single-issue In-order, reduced pipeline depth (traditional SIMD / DSP)
1622 * In-order 5+ stage pipelines with instruction FIFOs and mild register-renaming
1623 * Out-of-order with instruction FIFOs and aggressive register-renaming
1626 Also to be taken into consideration:
1628 * "Virtual" vectorisation: single-issue loop, no internal ALU parallelism
1629 * Comphrensive vectorisation: FIFOs and internal parallelism
1630 * Hybrid Parallelism
1632 ### Full or partial software-emulation
1634 The absolute, absolute minimal implementation is to provide the full
1635 set of CSRs and detection logic for when any of the source or destination
1636 registers are vectorised. On detection, a trap is thrown, whether it's
1637 a branch, LOAD, STORE, or an arithmetic operation.
1639 Implementors are entirely free to choose whether to allow absolutely every
1640 single operation to be software-emulated, or whether to provide some emulation
1641 and some hardware support. In particular, for an RV32E implementation
1642 where fast context-switching is a requirement (see "Context Switch Example"),
1643 it makes no sense to allow Vectorised-LOAD/STORE to be implemented as an
1644 exception, as every context-switch will result in double-traps.
1648 > For great floating point DSPs check TI’s C3x, C4X, and C6xx DSPs
1650 Idea: basic simple butterfly swap on a few element indices, primarily targetted
1651 at SIMD / DSP. High-byte low-byte swapping, high-word low-word swapping,
1652 perhaps allow reindexing of permutations up to 4 elements? 8? Reason:
1653 such operations are less costly than a full indexed-shuffle, which requires
1654 a separate instruction cycle.
1656 Predication "all zeros" needs to be "leave alone". Detection of
1657 ADD r1, rs1, rs0 cases result in nop on predication index 0, whereas
1658 ADD r0, rs1, rs2 is actually a desirable copy from r2 into r0.
1659 Destruction of destination indices requires a copy of the entire vector
1660 in advance to avoid.
1662 TBD: floating-point compare and other exception handling
1668 Please don't try to use the L1 itself.
1670 Use the Load and Store buffers which capture instruction state prior
1671 to being accessed in the L1 (and prior to data arriving in the case of
1674 Also, use the L1 Miss buffers as these already HAVE to be snooped by
1675 coherence traffic. These are used to monitor that all participating
1676 cache lines remain interference free, and amalgamate same into a CPU
1677 signal accessible ia branch or predicate.
1679 The Load buffers manage inbound traffic
1680 The Store buffers manage outbound traffic.
1682 Done properly, the participating cache lines can exceed the associativity
1683 of the L1 cache without architectural harm (may incur additional latency).
1685 <https://groups.google.com/d/msg/comp.arch/QVl3c9vVDj0/ol_232-pAQAJ>
1687 > > > so, let's say instead of another LR *cancelling* the load
1688 > > > reservation, the SMP core / hardware thread *blocks* for
1689 > > > up to 63 further instructions, waiting for the reservation
1692 > > Can you explain what you mean by this paragraph?
1694 > best put in sequential events, probably.
1696 > <core1> LR <-- 64-instruction countdown starts here
1699 > <core2> LR same address <--- notes that core1 is on 61,
1700 > so pauses for **UP TO** 61 cycles
1702 > <core1> SC <- core1 didn't reach zero, therefore valid, therefore
1703 > core2 is now **UNBLOCKED**, is granted the
1704 > load-reservation (and begins its **own** 64-cycle
1705 > LR instruction countdown)
1710 > <core2> SC <- also valid
1712 Looks to me that you could effect the same functionality by simply
1713 holding onto the cache line in core 1 preventing core 2 from
1714 <architecturally> getting past the LR.
1716 On the other hand, the freeze is similar to how the MP CRAYs did
1721 * SIMD considered harmful <https://www.sigarch.org/simd-instructions-considered-harmful/>
1722 * Link to first proposal <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/GuukrSjgBH8>
1723 * Recommendation by Jacob Bachmeyer to make zero-overhead loop an
1724 "implicit program-counter" <https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/vYVi95gF2Mo/SHz6a4_lAgAJ>
1725 * Re-continuing P-Extension proposal <https://groups.google.com/a/groups.riscv.org/forum/#!msg/isa-dev/IkLkQn3HvXQ/SEMyC9IlAgAJ>
1726 * First Draft P-SIMD (DSP) proposal <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/vYVi95gF2Mo>
1727 * B-Extension discussion <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/zi_7B15kj6s>
1728 * Broadcom VideoCore-IV <https://docs.broadcom.com/docs/12358545>
1729 Figure 2 P17 and Section 3 on P16.
1730 * Hwacha <https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-262.html>
1731 * Hwacha <https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-263.html>
1732 * Vector Workshop <http://riscv.org/wp-content/uploads/2015/06/riscv-vector-workshop-june2015.pdf>
1733 * Predication <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/XoP4BfYSLXA>
1734 * Branch Divergence <https://jbush001.github.io/2014/12/07/branch-divergence-in-parallel-kernels.html>
1735 * Life of Triangles (3D) <https://jbush001.github.io/2016/02/27/life-of-triangle.html>
1736 * Videocore-IV <https://github.com/hermanhermitage/videocoreiv/wiki/VideoCore-IV-3d-Graphics-Pipeline>
1737 * Discussion proposing CSRs that change ISA definition
1738 <https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/InzQ1wr_3Ak>
1739 * Zero-overhead loops <https://pdfs.semanticscholar.org/dbaa/66985cc730d4b44d79f519e96ec9c43ab5b7.pdf>
1740 * Multi-ported VLIW Register File Implementation <https://ce-publications.et.tudelft.nl/publications/1517_multiple_contexts_in_a_multiported_vliw_register_file_impl.pdf>
1741 * Fast context save/restore proposal <https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/57F823FA.6030701%40gmail.com>
1742 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>
1743 * Expired Patent on Vector Virtual Memory solutions
1744 <https://patentimages.storage.googleapis.com/fc/f6/e2/2cbee92fcd8743/US5895501.pdf>
1745 * Discussion on RVV "re-entrant" capabilities allowing operations to be
1746 restarted if an exception occurs (VM page-table miss)
1747 <https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/IuNFitTw9fM/CCKBUlzsAAAJ>
1748 * Dot Product Vector <https://people.eecs.berkeley.edu/~biancolin/papers/arith17.pdf>
1749 * RVV slides 2017 <https://content.riscv.org/wp-content/uploads/2017/12/Wed-1330-RISCVRogerEspasaVEXT-v4.pdf>
1750 * Wavefront skipping using BRAMS <http://www.ece.ubc.ca/~lemieux/publications/severance-fpga2015.pdf>
1751 * Streaming Pipelines <http://www.ece.ubc.ca/~lemieux/publications/severance-fpga2014.pdf>
1752 * Barcelona SIMD Presentation <https://content.riscv.org/wp-content/uploads/2018/05/09.05.2018-9.15-9.30am-RISCV201805-Andes-proposed-P-extension.pdf>
1753 * <http://www.ece.ubc.ca/~lemieux/publications/severance-fpga2015.pdf>
1754 * Full Description (last page) of RVV instructions
1755 <https://inst.eecs.berkeley.edu/~cs152/sp18/handouts/lab4-1.0.pdf>
1756 * PULP Low-energy Cluster Vector Processor
1757 <http://iis-projects.ee.ethz.ch/index.php/Low-Energy_Cluster-Coupled_Vector_Coprocessor_for_Special-Purpose_PULP_Acceleration>