08736f01a3bdc1e22165f9efaacdd9f02cff5788
[gem5.git] / site_scons / site_tools / default.py
1 # Copyright (c) 2013, 2015-2017 ARM Limited
2 # All rights reserved.
3 #
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
12 #
13 # Copyright (c) 2011 Advanced Micro Devices, Inc.
14 # Copyright (c) 2009 The Hewlett-Packard Development Company
15 # Copyright (c) 2004-2005 The Regents of The University of Michigan
16 # All rights reserved.
17 #
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
21 # notice, this list of conditions and the following disclaimer;
22 # redistributions in binary form must reproduce the above copyright
23 # notice, this list of conditions and the following disclaimer in the
24 # documentation and/or other materials provided with the distribution;
25 # neither the name of the copyright holders nor the names of its
26 # contributors may be used to endorse or promote products derived from
27 # this software without specific prior written permission.
28 #
29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40
41 import os
42 import sys
43
44 import SCons.Tool
45 import SCons.Tool.default
46
47 from gem5_python_paths import extra_python_paths
48
49 def common_config(env):
50 # export TERM so that clang reports errors in color
51 use_vars = set([ 'AS', 'AR', 'CC', 'CXX', 'HOME', 'LD_LIBRARY_PATH',
52 'LIBRARY_PATH', 'PATH', 'PKG_CONFIG_PATH', 'PROTOC',
53 'PYTHONPATH', 'RANLIB', 'TERM' ])
54
55 use_prefixes = [
56 "ASAN_", # address sanitizer symbolizer path and settings
57 "CCACHE_", # ccache (caching compiler wrapper) configuration
58 "CCC_", # clang static analyzer configuration
59 "DISTCC_", # distcc (distributed compiler wrapper) config
60 "INCLUDE_SERVER_", # distcc pump server settings
61 "M5", # M5 configuration (e.g., path to kernels)
62 ]
63
64 for key,val in sorted(os.environ.items()):
65 if key in use_vars or \
66 any([key.startswith(prefix) for prefix in use_prefixes]):
67 env['ENV'][key] = val
68
69 # Tell scons to avoid implicit command dependencies to avoid issues
70 # with the param wrappes being compiled twice (see
71 # http://scons.tigris.org/issues/show_bug.cgi?id=2811)
72 env['IMPLICIT_COMMAND_DEPENDENCIES'] = 0
73 env.Decider('MD5-timestamp')
74 env.root = env.Dir('#')
75 env.srcdir = env.root.Dir('src')
76
77 # add useful python code PYTHONPATH so it can be used by subprocesses
78 # as well
79 env.AppendENVPath('PYTHONPATH', extra_python_paths)
80
81 gem5_tool_list = [
82 'git',
83 'mercurial',
84 ]
85
86 def generate(env):
87 common_config(env)
88 SCons.Tool.default.generate(env)
89 for tool in gem5_tool_list:
90 SCons.Tool.Tool(tool)(env)
91
92 def exists(env):
93 return 1