soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5 use std.textio.all;
   6 use std.env.stop;
   7
   8 library work;
   9 use work.common.all;
  10 use work.wishbone_types.all;
  11
  12
  13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
  14 --
  15 -- Main bus:
  16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
  17 -- 0x40000000: DRAM (when present)
  18 -- 0x80000000: Block RAM (aliased & repeated)
  19
  20 -- IO Bus:
  21 -- 0xc0000000: SYSCON
  22 -- 0xc0002000: UART0
  23 -- 0xc0003000: UART1 (if any)
  24 -- 0xc0004000: XICS ICP
  25 -- 0xc0005000: XICS ICS
  26 -- 0xc0006000: SPI Flash controller
  27 -- 0xc0007000: GPIO controller
  28 -- 0xc8nnnnnn: External IO bus
  29 -- 0xf0000000: Flash "ROM" mapping
  30 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
  31
  32 -- External IO bus:
  33 -- 0xc8000000: LiteDRAM control (CSRs)
  34 -- 0xc8020000: LiteEth CSRs (*)
  35 -- 0xc8030000: LiteEth MMIO (*)
  36
  37 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
  38 --     are actually decoded as a single wishbone which LiteEth will
  39 --     internally split based on bit 16.
  40
  41 -- (**) DRAM init code is currently special and goes to the external
  42 --      IO bus, this will be fixed when it's moved out of litedram and
  43 --      into the main SoC once we have a common "firmware".
  44
  45 -- Interrupt numbers:
  46 --
  47 --   0  : UART0
  48 --   1  : Ethernet
  49
  50 entity soc is
  51     generic (
  52         MEMORY_SIZE        : natural;
  53         RAM_INIT_FILE      : string;
  54         CLK_FREQ           : positive;
  55         SIM                : boolean;
  56         HAS_FPU            : boolean := true;
  57         HAS_BTC            : boolean := true;
  58         DISABLE_FLATTEN_CORE : boolean := false;
  59         HAS_DRAM           : boolean  := false;
  60         DRAM_SIZE          : integer := 0;
  61         DRAM_INIT_SIZE     : integer := 0;
  62         HAS_SPI_FLASH      : boolean := false;
  63         SPI_FLASH_DLINES   : positive := 1;
  64         SPI_FLASH_OFFSET   : integer := 0;
  65         SPI_FLASH_DEF_CKDV : natural := 2;
  66         SPI_FLASH_DEF_QUAD : boolean := false;
  67         LOG_LENGTH         : natural := 512;
  68         HAS_LITEETH        : boolean := false;
  69         UART0_IS_16550     : boolean := true;
  70         HAS_UART1          : boolean := false;
  71         NGPIO              : natural := 0
  72         );
  73     port(
  74         rst          : in  std_ulogic;
  75         system_clk   : in  std_ulogic;
  76
  77         -- "Large" (64-bit) DRAM wishbone
  78         wb_dram_in       : out wishbone_master_out;
  79         wb_dram_out      : in wishbone_slave_out := wishbone_slave_out_init;
  80
  81         -- "Small" (32-bit) external IO wishbone
  82         wb_ext_io_in         : out wb_io_master_out;
  83         wb_ext_io_out        : in wb_io_slave_out := wb_io_slave_out_init;
  84         wb_ext_is_dram_csr   : out std_ulogic;
  85         wb_ext_is_dram_init  : out std_ulogic;
  86         wb_ext_is_eth        : out std_ulogic;
  87
  88         -- External interrupts
  89         ext_irq_eth          : in std_ulogic := '0';
  90
  91         -- UART0 signals:
  92         uart0_txd    : out std_ulogic;
  93         uart0_rxd    : in  std_ulogic := '0';
  94
  95         -- UART1 signals:
  96         uart1_txd    : out std_ulogic;
  97         uart1_rxd    : in  std_ulogic := '0';
  98
  99         -- SPI Flash signals
 100         spi_flash_sck     : out std_ulogic;
 101         spi_flash_cs_n    : out std_ulogic;
 102         spi_flash_sdat_o  : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
 103         spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
 104         spi_flash_sdat_i  : in  std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
 105
 106         -- GPIO signals
 107         gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0);
 108         gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0);
 109         gpio_in  : in  std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
 110
 111         -- DRAM controller signals
 112         alt_reset    : in std_ulogic := '0'
 113         );
 114 end entity soc;
 115
 116 architecture behaviour of soc is
 117
 118     -- Wishbone master signals:
 119     signal wishbone_dcore_in  : wishbone_slave_out;
 120     signal wishbone_dcore_out : wishbone_master_out;
 121     signal wishbone_icore_in  : wishbone_slave_out;
 122     signal wishbone_icore_out : wishbone_master_out;
 123     signal wishbone_debug_in : wishbone_slave_out;
 124     signal wishbone_debug_out : wishbone_master_out;
 125
 126     -- Arbiter array (ghdl doesnt' support assigning the array
 127     -- elements in the entity instantiation)
 128     constant NUM_WB_MASTERS : positive := 3;
 129     signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
 130     signal wb_masters_in  : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
 131
 132     -- Wishbone master (output of arbiter):
 133     signal wb_master_in       : wishbone_slave_out;
 134     signal wb_master_out      : wishbone_master_out;
 135
 136     -- Main "IO" bus, from main slave decoder to the latch
 137     signal wb_io_in     : wishbone_master_out;
 138     signal wb_io_out    : wishbone_slave_out;
 139
 140     -- Secondary (smaller) IO bus after the IO bus latch
 141     signal wb_sio_out    : wb_io_master_out;
 142     signal wb_sio_in     : wb_io_slave_out;
 143
 144     -- Syscon signals
 145     signal dram_at_0     : std_ulogic;
 146     signal do_core_reset    : std_ulogic;
 147     signal wb_syscon_in  : wb_io_master_out;
 148     signal wb_syscon_out : wb_io_slave_out;
 149
 150     -- UART0 signals:
 151     signal wb_uart0_in   : wb_io_master_out;
 152     signal wb_uart0_out  : wb_io_slave_out;
 153     signal uart0_dat8    : std_ulogic_vector(7 downto 0);
 154     signal uart0_irq     : std_ulogic;
 155
 156     -- UART1 signals:
 157     signal wb_uart1_in   : wb_io_master_out;
 158     signal wb_uart1_out  : wb_io_slave_out;
 159     signal uart1_dat8    : std_ulogic_vector(7 downto 0);
 160     signal uart1_irq     : std_ulogic;
 161
 162     -- SPI Flash controller signals:
 163     signal wb_spiflash_in     : wb_io_master_out;
 164     signal wb_spiflash_out    : wb_io_slave_out;
 165     signal wb_spiflash_is_reg : std_ulogic;
 166     signal wb_spiflash_is_map : std_ulogic;
 167
 168     -- XICS signals:
 169     signal wb_xics_icp_in   : wb_io_master_out;
 170     signal wb_xics_icp_out  : wb_io_slave_out;
 171     signal wb_xics_ics_in   : wb_io_master_out;
 172     signal wb_xics_ics_out  : wb_io_slave_out;
 173     signal int_level_in     : std_ulogic_vector(15 downto 0);
 174     signal ics_to_icp       : ics_to_icp_t;
 175     signal core_ext_irq     : std_ulogic;
 176
 177     -- GPIO signals:
 178     signal wb_gpio_in    : wb_io_master_out;
 179     signal wb_gpio_out   : wb_io_slave_out;
 180     signal gpio_intr     : std_ulogic := '0';
 181
 182     -- Main memory signals:
 183     signal wb_bram_in     : wishbone_master_out;
 184     signal wb_bram_out    : wishbone_slave_out;
 185
 186     -- DMI debug bus signals
 187     signal dmi_addr     : std_ulogic_vector(7 downto 0);
 188     signal dmi_din      : std_ulogic_vector(63 downto 0);
 189     signal dmi_dout     : std_ulogic_vector(63 downto 0);
 190     signal dmi_req      : std_ulogic;
 191     signal dmi_wr       : std_ulogic;
 192     signal dmi_ack      : std_ulogic;
 193
 194     -- Per slave DMI signals
 195     signal dmi_wb_dout  : std_ulogic_vector(63 downto 0);
 196     signal dmi_wb_req   : std_ulogic;
 197     signal dmi_wb_ack   : std_ulogic;
 198     signal dmi_core_dout  : std_ulogic_vector(63 downto 0);
 199     signal dmi_core_req   : std_ulogic;
 200     signal dmi_core_ack   : std_ulogic;
 201
 202     -- Delayed/latched resets and alt_reset
 203     signal rst_core    : std_ulogic := '1';
 204     signal rst_uart    : std_ulogic := '1';
 205     signal rst_xics    : std_ulogic := '1';
 206     signal rst_spi     : std_ulogic := '1';
 207     signal rst_gpio    : std_ulogic := '1';
 208     signal rst_bram    : std_ulogic := '1';
 209     signal rst_dtm     : std_ulogic := '1';
 210     signal rst_wbar    : std_ulogic := '1';
 211     signal rst_wbdb    : std_ulogic := '1';
 212     signal alt_reset_d : std_ulogic;
 213
 214     -- IO branch split:
 215     type slave_io_type is (SLAVE_IO_SYSCON,
 216                            SLAVE_IO_UART,
 217                            SLAVE_IO_ICP,
 218                            SLAVE_IO_ICS,
 219                            SLAVE_IO_UART1,
 220                            SLAVE_IO_SPI_FLASH_REG,
 221                            SLAVE_IO_SPI_FLASH_MAP,
 222                            SLAVE_IO_GPIO,
 223                            SLAVE_IO_EXTERNAL,
 224                            SLAVE_IO_NONE);
 225     signal slave_io_dbg : slave_io_type;
 226
 227     -- This is the component exported by the 16550 compatible
 228     -- UART from FuseSoC.
 229     --
 230     component uart_top port (
 231         wb_clk_i    : in std_ulogic;
 232         wb_rst_i    : in std_ulogic;
 233         wb_adr_i    : in std_ulogic_vector(2 downto 0);
 234         wb_dat_i    : in std_ulogic_vector(7 downto 0);
 235         wb_dat_o    : out std_ulogic_vector(7 downto 0);
 236         wb_we_i     : in std_ulogic;
 237         wb_stb_i    : in std_ulogic;
 238         wb_cyc_i    : in std_ulogic;
 239         wb_ack_o    : out std_ulogic;
 240         int_o       : out std_ulogic;
 241         stx_pad_o   : out std_ulogic;
 242         srx_pad_i   : in std_ulogic;
 243         rts_pad_o   : out std_ulogic;
 244         cts_pad_i   : in std_ulogic;
 245         dtr_pad_o   : out std_ulogic;
 246         dsr_pad_i   : in std_ulogic;
 247         ri_pad_i    : in std_ulogic;
 248         dcd_pad_i   : in std_ulogic
 249         );
 250     end component;
 251 begin
 252
 253     resets: process(system_clk)
 254     begin
 255         if rising_edge(system_clk) then
 256             rst_core    <= rst or do_core_reset;
 257             rst_uart    <= rst;
 258             rst_spi     <= rst;
 259             rst_xics    <= rst;
 260             rst_gpio    <= rst;
 261             rst_bram    <= rst;
 262             rst_dtm     <= rst;
 263             rst_wbar    <= rst;
 264             rst_wbdb    <= rst;
 265             alt_reset_d <= alt_reset;
 266         end if;
 267     end process;
 268
 269     -- Processor core
 270     processor: entity work.core
 271         generic map(
 272             SIM => SIM,
 273             HAS_FPU => HAS_FPU,
 274             HAS_BTC => HAS_BTC,
 275             DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
 276             ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
 277             LOG_LENGTH => LOG_LENGTH
 278             )
 279         port map(
 280             clk => system_clk,
 281             rst => rst_core,
 282             alt_reset => alt_reset_d,
 283             wishbone_insn_in => wishbone_icore_in,
 284             wishbone_insn_out => wishbone_icore_out,
 285             wishbone_data_in => wishbone_dcore_in,
 286             wishbone_data_out => wishbone_dcore_out,
 287             dmi_addr => dmi_addr(3 downto 0),
 288             dmi_dout => dmi_core_dout,
 289             dmi_din => dmi_dout,
 290             dmi_wr => dmi_wr,
 291             dmi_ack => dmi_core_ack,
 292             dmi_req => dmi_core_req,
 293             ext_irq => core_ext_irq
 294             );
 295
 296     -- Wishbone bus master arbiter & mux
 297     wb_masters_out <= (0 => wishbone_dcore_out,
 298                        1 => wishbone_icore_out,
 299                        2 => wishbone_debug_out);
 300     wishbone_dcore_in <= wb_masters_in(0);
 301     wishbone_icore_in <= wb_masters_in(1);
 302     wishbone_debug_in <= wb_masters_in(2);
 303     wishbone_arbiter_0: entity work.wishbone_arbiter
 304         generic map(
 305             NUM_MASTERS => NUM_WB_MASTERS
 306             )
 307         port map(
 308             clk => system_clk,
 309             rst => rst_wbar,
 310             wb_masters_in => wb_masters_out,
 311             wb_masters_out => wb_masters_in,
 312             wb_slave_out => wb_master_out,
 313             wb_slave_in => wb_master_in
 314             );
 315
 316     -- Top level Wishbone slaves address decoder & mux
 317     --
 318     -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
 319     -- 0000  - BRAM
 320     -- 0001  - DRAM
 321     -- 01xx  - DRAM
 322     -- 10xx  - BRAM
 323     -- 11xx  - IO
 324     --
 325     slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
 326         type slave_top_type is (SLAVE_TOP_BRAM,
 327                                 SLAVE_TOP_DRAM,
 328                                 SLAVE_TOP_IO);
 329         variable slave_top : slave_top_type;
 330         variable top_decode : std_ulogic_vector(3 downto 0);
 331     begin
 332         -- Top-level address decoder
 333         top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
 334         slave_top := SLAVE_TOP_BRAM;
 335         if    std_match(top_decode, "0000") then
 336             slave_top := SLAVE_TOP_BRAM;
 337         elsif std_match(top_decode, "0001") then
 338             slave_top := SLAVE_TOP_DRAM;
 339         elsif std_match(top_decode, "01--") then
 340             slave_top := SLAVE_TOP_DRAM;
 341         elsif std_match(top_decode, "10--") then
 342             slave_top := SLAVE_TOP_BRAM;
 343         elsif std_match(top_decode, "11--") then
 344             slave_top := SLAVE_TOP_IO;
 345         end if;
 346
 347         -- Top level wishbone muxing.
 348         wb_bram_in <= wb_master_out;
 349         wb_bram_in.cyc  <= '0';
 350         wb_dram_in <= wb_master_out;
 351         wb_dram_in.cyc  <= '0';
 352         wb_io_in <= wb_master_out;
 353         wb_io_in.cyc  <= '0';
 354         case slave_top is
 355         when SLAVE_TOP_BRAM =>
 356             wb_bram_in.cyc <= wb_master_out.cyc;
 357             wb_master_in <= wb_bram_out;
 358         when SLAVE_TOP_DRAM =>
 359             if HAS_DRAM then
 360                 wb_dram_in.cyc <= wb_master_out.cyc;
 361                 wb_master_in <= wb_dram_out;
 362             else
 363                 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
 364                 wb_master_in.dat <= (others => '1');
 365                 wb_master_in.stall <= '0';
 366             end if;
 367         when SLAVE_TOP_IO =>
 368             wb_io_in.cyc <= wb_master_out.cyc;
 369             wb_master_in <= wb_io_out;
 370         end case;
 371
 372     end process slave_top_intercon;
 373
 374     -- IO wishbone slave 64->32 bits converter
 375     --
 376     -- For timing reasons, this adds a one cycle latch on the way both
 377     -- in and out. This relaxes timing and routing pressure on the "main"
 378     -- memory bus by moving all simple IOs to a slower 32-bit bus.
 379     --
 380     -- This implementation is rather dumb at the moment, no stash buffer,
 381     -- so we stall whenever that latch is busy. This can be improved.
 382     --
 383     slave_io_latch: process(system_clk)
 384         -- State
 385         type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
 386         variable state : state_t;
 387
 388         -- Misc
 389         variable has_top : boolean;
 390         variable has_bot : boolean;
 391     begin
 392         if rising_edge(system_clk) then
 393             if (rst) then
 394                 state := IDLE;
 395                 wb_io_out.ack <= '0';
 396                 wb_io_out.stall <= '0';
 397                 wb_sio_out.cyc <= '0';
 398                 wb_sio_out.stb <= '0';
 399                 has_top := false;
 400                 has_bot := false;
 401             else
 402                 case state is
 403                 when IDLE =>
 404                     -- Clear ACK in case it was set
 405                     wb_io_out.ack <= '0';
 406
 407                     -- Do we have a cycle ?
 408                     if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
 409                         -- Stall master until we are done, we are't (yet) pipelining
 410                         -- this, it's all slow IOs.
 411                         wb_io_out.stall <= '1';
 412
 413                         -- Start cycle downstream
 414                         wb_sio_out.cyc <= '1';
 415                         wb_sio_out.stb <= '1';
 416
 417                         -- Copy write enable to IO out, copy address as well
 418                         wb_sio_out.we <= wb_io_in.we;
 419                         wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
 420
 421                         -- Do we have a top word and/or a bottom word ?
 422                         has_top := wb_io_in.sel(7 downto 4) /= "0000";
 423                         has_bot := wb_io_in.sel(3 downto 0) /= "0000";
 424
 425                         -- If we have a bottom word, handle it first, otherwise
 426                         -- send the top word down. XXX Split the actual mux out
 427                         -- and only generate a control signal.
 428                         if has_bot then
 429                             if wb_io_in.we = '1' then
 430                                 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
 431                             end if;
 432                             wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
 433
 434                             -- Wait for ack
 435                             state := WAIT_ACK_BOT;
 436                         else
 437                             if wb_io_in.we = '1' then
 438                                 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 439                             end if;
 440                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 441
 442                             -- Bump address
 443                             wb_sio_out.adr(2) <= '1';
 444
 445                             -- Wait for ack
 446                             state := WAIT_ACK_TOP;
 447                         end if;
 448                     end if;
 449                 when WAIT_ACK_BOT =>
 450                     -- If we aren't stalled by the device, clear stb
 451                     if wb_sio_in.stall = '0' then
 452                         wb_sio_out.stb <= '0';
 453                     end if;
 454
 455                     -- Handle ack
 456                     if wb_sio_in.ack = '1' then
 457                         -- If it's a read, latch the data
 458                         if wb_sio_out.we = '0' then
 459                             wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
 460                         end if;
 461
 462                         -- Do we have a "top" part as well ?
 463                         if has_top then
 464                             -- Latch data & sel
 465                             if wb_io_in.we = '1' then
 466                                 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 467                             end if;
 468                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 469
 470                             -- Bump address and set STB
 471                             wb_sio_out.adr(2) <= '1';
 472                             wb_sio_out.stb <= '1';
 473
 474                             -- Wait for new ack
 475                             state := WAIT_ACK_TOP;
 476                         else
 477                             -- We are done, ack up, clear cyc downstram
 478                             wb_sio_out.cyc <= '0';
 479
 480                             -- And ack & unstall upstream
 481                             wb_io_out.ack <= '1';
 482                             wb_io_out.stall <= '0';
 483
 484                             -- Wait for next one
 485                             state := IDLE;
 486                         end if;
 487                     end if;
 488                 when WAIT_ACK_TOP =>
 489                     -- If we aren't stalled by the device, clear stb
 490                     if wb_sio_in.stall = '0' then
 491                         wb_sio_out.stb <= '0';
 492                     end if;
 493
 494                     -- Handle ack
 495                     if wb_sio_in.ack = '1' then
 496                         -- If it's a read, latch the data
 497                         if wb_sio_out.we = '0' then
 498                             wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
 499                         end if;
 500
 501                         -- We are done, ack up, clear cyc downstram
 502                         wb_sio_out.cyc <= '0';
 503
 504                         -- And ack & unstall upstream
 505                         wb_io_out.ack <= '1';
 506                         wb_io_out.stall <= '0';
 507
 508                         -- Wait for next one
 509                         state := IDLE;
 510                     end if;
 511                 end case;
 512             end if;
 513         end if;
 514     end process;
 515
 516     -- IO wishbone slave intercon.
 517     --
 518     slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
 519                                wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
 520                                wb_spiflash_out)
 521         variable slave_io : slave_io_type;
 522
 523         variable match : std_ulogic_vector(31 downto 12);
 524         variable ext_valid : boolean;
 525     begin
 526
 527         -- Simple address decoder.
 528         slave_io := SLAVE_IO_NONE;
 529         match := "11" & wb_sio_out.adr(29 downto 12);
 530         if    std_match(match, x"FF---") and HAS_DRAM then
 531             slave_io := SLAVE_IO_EXTERNAL;
 532         elsif std_match(match, x"F----") then
 533             slave_io := SLAVE_IO_SPI_FLASH_MAP;
 534         elsif std_match(match, x"C0000") then
 535             slave_io := SLAVE_IO_SYSCON;
 536         elsif std_match(match, x"C0002") then
 537             slave_io := SLAVE_IO_UART;
 538         elsif std_match(match, x"C0003") then
 539             slave_io := SLAVE_IO_UART1;
 540         elsif std_match(match, x"C8---") then
 541             slave_io := SLAVE_IO_EXTERNAL;
 542         elsif std_match(match, x"C0004") then
 543             slave_io := SLAVE_IO_ICP;
 544         elsif std_match(match, x"C0005") then
 545             slave_io := SLAVE_IO_ICS;
 546         elsif std_match(match, x"C0006") then
 547             slave_io := SLAVE_IO_SPI_FLASH_REG;
 548         elsif std_match(match, x"C0007") then
 549             slave_io := SLAVE_IO_GPIO;
 550         end if;
 551         slave_io_dbg <= slave_io;
 552         wb_uart0_in <= wb_sio_out;
 553         wb_uart0_in.cyc <= '0';
 554         wb_uart1_in <= wb_sio_out;
 555         wb_uart1_in.cyc <= '0';
 556         wb_spiflash_in <= wb_sio_out;
 557         wb_spiflash_in.cyc <= '0';
 558         wb_spiflash_is_reg <= '0';
 559         wb_spiflash_is_map <= '0';
 560         wb_gpio_in <= wb_sio_out;
 561         wb_gpio_in.cyc <= '0';
 562
 563          -- Only give xics 8 bits of wb addr (for now...)
 564         wb_xics_icp_in <= wb_sio_out;
 565         wb_xics_icp_in.adr <= (others => '0');
 566         wb_xics_icp_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
 567         wb_xics_icp_in.cyc  <= '0';
 568         wb_xics_ics_in <= wb_sio_out;
 569         wb_xics_ics_in.adr <= (others => '0');
 570         wb_xics_ics_in.adr(11 downto 0) <= wb_sio_out.adr(11 downto 0);
 571         wb_xics_ics_in.cyc  <= '0';
 572
 573         wb_ext_io_in <= wb_sio_out;
 574         wb_ext_io_in.cyc <= '0';
 575
 576         wb_syscon_in <= wb_sio_out;
 577         wb_syscon_in.cyc <= '0';
 578
 579         wb_ext_is_dram_csr   <= '0';
 580         wb_ext_is_dram_init  <= '0';
 581         wb_ext_is_eth        <= '0';
 582
 583         -- Default response, ack & return all 1's
 584         wb_sio_in.dat <= (others => '1');
 585         wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
 586         wb_sio_in.stall <= '0';
 587
 588         case slave_io is
 589         when SLAVE_IO_EXTERNAL =>
 590             -- Ext IO "chip selects"
 591             --
 592             -- DRAM init is special at 0xFF* so we just test the top
 593             -- bit. Everything else is at 0xC8* so we test only bits
 594             -- 23 downto 16.
 595             --
 596             ext_valid := false;
 597             if wb_sio_out.adr(29) = '1' and HAS_DRAM then  -- DRAM init is special
 598                 wb_ext_is_dram_init <= '1';
 599                 ext_valid := true;
 600             elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
 601                 wb_ext_is_dram_csr  <= '1';
 602                 ext_valid := true;
 603             elsif wb_sio_out.adr(23 downto 16) = x"02" and HAS_LITEETH then
 604                 wb_ext_is_eth       <= '1';
 605                 ext_valid := true;
 606             elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then
 607                 wb_ext_is_eth       <= '1';
 608                 ext_valid := true;
 609             end if;
 610             if ext_valid then
 611                 wb_ext_io_in.cyc <= wb_sio_out.cyc;
 612                 wb_sio_in <= wb_ext_io_out;
 613             end if;
 614
 615         when SLAVE_IO_SYSCON =>
 616             wb_syscon_in.cyc <= wb_sio_out.cyc;
 617             wb_sio_in <= wb_syscon_out;
 618         when SLAVE_IO_UART =>
 619             wb_uart0_in.cyc <= wb_sio_out.cyc;
 620             wb_sio_in <= wb_uart0_out;
 621         when SLAVE_IO_ICP =>
 622             wb_xics_icp_in.cyc <= wb_sio_out.cyc;
 623             wb_sio_in <= wb_xics_icp_out;
 624         when SLAVE_IO_ICS =>
 625             wb_xics_ics_in.cyc <= wb_sio_out.cyc;
 626             wb_sio_in <= wb_xics_ics_out;
 627         when SLAVE_IO_UART1 =>
 628             wb_uart1_in.cyc <= wb_sio_out.cyc;
 629             wb_sio_in <= wb_uart1_out;
 630         when SLAVE_IO_SPI_FLASH_MAP =>
 631             -- Clear top bits so they don't make their way to the
 632             -- fash chip.
 633             wb_spiflash_in.adr(29 downto 28) <= "00";
 634             wb_spiflash_in.cyc <= wb_sio_out.cyc;
 635             wb_sio_in <= wb_spiflash_out;
 636             wb_spiflash_is_map <= '1';
 637         when SLAVE_IO_SPI_FLASH_REG =>
 638             wb_spiflash_in.cyc <= wb_sio_out.cyc;
 639             wb_sio_in <= wb_spiflash_out;
 640             wb_spiflash_is_reg <= '1';
 641         when SLAVE_IO_GPIO =>
 642             wb_gpio_in.cyc <= wb_sio_out.cyc;
 643             wb_sio_in <= wb_gpio_out;
 644         when others =>
 645         end case;
 646
 647     end process;
 648
 649     -- Syscon slave
 650     syscon0: entity work.syscon
 651         generic map(
 652             HAS_UART => true,
 653             HAS_DRAM => HAS_DRAM,
 654             BRAM_SIZE => MEMORY_SIZE,
 655             DRAM_SIZE => DRAM_SIZE,
 656             DRAM_INIT_SIZE => DRAM_INIT_SIZE,
 657             CLK_FREQ => CLK_FREQ,
 658             HAS_SPI_FLASH => HAS_SPI_FLASH,
 659             SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
 660             HAS_LITEETH => HAS_LITEETH,
 661             UART0_IS_16550 => UART0_IS_16550,
 662             HAS_UART1 => HAS_UART1
 663         )
 664         port map(
 665             clk => system_clk,
 666             rst => rst,
 667             wishbone_in => wb_syscon_in,
 668             wishbone_out => wb_syscon_out,
 669             dram_at_0 => dram_at_0,
 670             core_reset => do_core_reset,
 671             soc_reset => open -- XXX TODO
 672             );
 673
 674     --
 675     -- UART0
 676     --
 677     -- Either potato (legacy) or 16550
 678     --
 679     uart0_pp: if not UART0_IS_16550 generate
 680         uart0: entity work.pp_soc_uart
 681             generic map(
 682                 FIFO_DEPTH => 32
 683                 )
 684             port map(
 685                 clk => system_clk,
 686                 reset => rst_uart,
 687                 txd => uart0_txd,
 688                 rxd => uart0_rxd,
 689                 irq => uart0_irq,
 690                 wb_adr_in => wb_uart0_in.adr(11 downto 0),
 691                 wb_dat_in => wb_uart0_in.dat(7 downto 0),
 692                 wb_dat_out => uart0_dat8,
 693                 wb_cyc_in => wb_uart0_in.cyc,
 694                 wb_stb_in => wb_uart0_in.stb,
 695                 wb_we_in => wb_uart0_in.we,
 696                 wb_ack_out => wb_uart0_out.ack
 697                 );
 698     end generate;
 699
 700     uart0_16550 : if UART0_IS_16550 generate
 701         signal irq_l : std_ulogic;
 702     begin
 703         uart0: uart_top
 704             port map (
 705                 wb_clk_i   => system_clk,
 706                 wb_rst_i   => rst_uart,
 707                 wb_adr_i   => wb_uart0_in.adr(4 downto 2),
 708                 wb_dat_i   => wb_uart0_in.dat(7 downto 0),
 709                 wb_dat_o   => uart0_dat8,
 710                 wb_we_i    => wb_uart0_in.we,
 711                 wb_stb_i   => wb_uart0_in.stb,
 712                 wb_cyc_i   => wb_uart0_in.cyc,
 713                 wb_ack_o   => wb_uart0_out.ack,
 714                 int_o      => irq_l,
 715                 stx_pad_o  => uart0_txd,
 716                 srx_pad_i  => uart0_rxd,
 717                 rts_pad_o  => open,
 718                 cts_pad_i  => '1',
 719                 dtr_pad_o  => open,
 720                 dsr_pad_i  => '1',
 721                 ri_pad_i   => '0',
 722                 dcd_pad_i  => '1'
 723                 );
 724
 725         -- Add a register on the irq out, helps timing
 726         uart0_irq_latch: process(system_clk)
 727         begin
 728             if rising_edge(system_clk) then
 729                 uart0_irq <= irq_l;
 730             end if;
 731         end process;
 732     end generate;
 733
 734     wb_uart0_out.dat <= x"000000" & uart0_dat8;
 735     wb_uart0_out.stall <= not wb_uart0_out.ack;
 736
 737     --
 738     -- UART1
 739     --
 740     -- Always 16550 if it exists
 741     --
 742     uart1: if HAS_UART1 generate
 743         signal irq_l : std_ulogic;
 744     begin
 745         uart1: uart_top
 746             port map (
 747                 wb_clk_i   => system_clk,
 748                 wb_rst_i   => rst_uart,
 749                 wb_adr_i   => wb_uart1_in.adr(4 downto 2),
 750                 wb_dat_i   => wb_uart1_in.dat(7 downto 0),
 751                 wb_dat_o   => uart1_dat8,
 752                 wb_we_i    => wb_uart1_in.we,
 753                 wb_stb_i   => wb_uart1_in.stb,
 754                 wb_cyc_i   => wb_uart1_in.cyc,
 755                 wb_ack_o   => wb_uart1_out.ack,
 756                 int_o      => irq_l,
 757                 stx_pad_o  => uart1_txd,
 758                 srx_pad_i  => uart1_rxd,
 759                 rts_pad_o  => open,
 760                 cts_pad_i  => '1',
 761                 dtr_pad_o  => open,
 762                 dsr_pad_i  => '1',
 763                 ri_pad_i   => '0',
 764                 dcd_pad_i  => '1'
 765                 );
 766         -- Add a register on the irq out, helps timing
 767         uart0_irq_latch: process(system_clk)
 768         begin
 769             if rising_edge(system_clk) then
 770                 uart1_irq <= irq_l;
 771             end if;
 772         end process;
 773         wb_uart1_out.dat <= x"000000" & uart1_dat8;
 774         wb_uart1_out.stall <= not wb_uart1_out.ack;
 775     end generate;
 776
 777     no_uart1 : if not HAS_UART1 generate
 778         wb_uart1_out.dat <= x"00000000";
 779         wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
 780         wb_uart1_out.stall <= '0';
 781         uart1_irq <= '0';
 782     end generate;
 783
 784     spiflash_gen: if HAS_SPI_FLASH generate
 785         spiflash: entity work.spi_flash_ctrl
 786             generic map (
 787                 DATA_LINES    => SPI_FLASH_DLINES,
 788                 DEF_CLK_DIV   => SPI_FLASH_DEF_CKDV,
 789                 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD
 790                 )
 791             port map(
 792                 rst => rst_spi,
 793                 clk => system_clk,
 794                 wb_in => wb_spiflash_in,
 795                 wb_out => wb_spiflash_out,
 796                 wb_sel_reg => wb_spiflash_is_reg,
 797                 wb_sel_map => wb_spiflash_is_map,
 798                 sck => spi_flash_sck,
 799                 cs_n => spi_flash_cs_n,
 800                 sdat_o => spi_flash_sdat_o,
 801                 sdat_oe => spi_flash_sdat_oe,
 802                 sdat_i => spi_flash_sdat_i
 803                 );
 804     end generate;
 805
 806     no_spi0_gen: if not HAS_SPI_FLASH generate
 807         wb_spiflash_out.dat   <= (others => '1');
 808         wb_spiflash_out.ack   <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
 809         wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
 810     end generate;
 811
 812     xics_icp: entity work.xics_icp
 813         port map(
 814             clk => system_clk,
 815             rst => rst_xics,
 816             wb_in => wb_xics_icp_in,
 817             wb_out => wb_xics_icp_out,
 818             ics_in => ics_to_icp,
 819             core_irq_out => core_ext_irq
 820             );
 821
 822     xics_ics: entity work.xics_ics
 823         generic map(
 824             SRC_NUM   => 16,
 825             PRIO_BITS => 3
 826             )
 827         port map(
 828             clk => system_clk,
 829             rst => rst_xics,
 830             wb_in => wb_xics_ics_in,
 831             wb_out => wb_xics_ics_out,
 832             int_level_in => int_level_in,
 833             icp_out => ics_to_icp
 834             );
 835
 836     gpio : entity work.gpio
 837         generic map(
 838             NGPIO => NGPIO
 839             )
 840         port map(
 841             clk      => system_clk,
 842             rst      => rst_gpio,
 843             wb_in    => wb_gpio_in,
 844             wb_out   => wb_gpio_out,
 845             gpio_in  => gpio_in,
 846             gpio_out => gpio_out,
 847             gpio_dir => gpio_dir,
 848             intr     => gpio_intr
 849             );
 850
 851     -- Assign external interrupts
 852     interrupts: process(all)
 853     begin
 854         int_level_in <= (others => '0');
 855         int_level_in(0) <= uart0_irq;
 856         int_level_in(1) <= ext_irq_eth;
 857         int_level_in(2) <= uart1_irq;
 858         int_level_in(3) <= gpio_intr;
 859     end process;
 860
 861     -- BRAM Memory slave
 862     bram: if MEMORY_SIZE /= 0 generate
 863         bram0: entity work.wishbone_bram_wrapper
 864             generic map(
 865                 MEMORY_SIZE   => MEMORY_SIZE,
 866                 RAM_INIT_FILE => RAM_INIT_FILE
 867                 )
 868             port map(
 869                 clk => system_clk,
 870                 rst => rst_bram,
 871                 wishbone_in => wb_bram_in,
 872                 wishbone_out => wb_bram_out
 873                 );
 874     end generate;
 875
 876     no_bram: if MEMORY_SIZE = 0 generate
 877         wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
 878         wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
 879         wb_bram_out.stall <= not wb_bram_out.ack;
 880     end generate;
 881
 882     -- DMI(debug bus) <-> JTAG bridge
 883     dtm: entity work.dmi_dtm
 884         generic map(
 885             ABITS => 8,
 886             DBITS => 64
 887             )
 888         port map(
 889             sys_clk     => system_clk,
 890             sys_reset   => rst_dtm,
 891             dmi_addr    => dmi_addr,
 892             dmi_din     => dmi_din,
 893             dmi_dout    => dmi_dout,
 894             dmi_req     => dmi_req,
 895             dmi_wr      => dmi_wr,
 896             dmi_ack     => dmi_ack
 897             );
 898
 899     -- DMI interconnect
 900     dmi_intercon: process(dmi_addr, dmi_req,
 901                           dmi_wb_ack, dmi_wb_dout,
 902                           dmi_core_ack, dmi_core_dout)
 903
 904         -- DMI address map (each address is a full 64-bit register)
 905         --
 906         -- Offset:   Size:    Slave:
 907         --  0         4       Wishbone
 908         -- 10        16       Core
 909
 910         type slave_type is (SLAVE_WB,
 911                             SLAVE_CORE,
 912                             SLAVE_NONE);
 913         variable slave : slave_type;
 914     begin
 915         -- Simple address decoder
 916         slave := SLAVE_NONE;
 917         if std_match(dmi_addr, "000000--") then
 918             slave := SLAVE_WB;
 919         elsif std_match(dmi_addr, "0001----") then
 920             slave := SLAVE_CORE;
 921         end if;
 922
 923         -- DMI muxing
 924         dmi_wb_req <= '0';
 925         dmi_core_req <= '0';
 926         case slave is
 927         when SLAVE_WB =>
 928             dmi_wb_req <= dmi_req;
 929             dmi_ack <= dmi_wb_ack;
 930             dmi_din <= dmi_wb_dout;
 931         when SLAVE_CORE =>
 932             dmi_core_req <= dmi_req;
 933             dmi_ack <= dmi_core_ack;
 934             dmi_din <= dmi_core_dout;
 935         when others =>
 936             dmi_ack <= dmi_req;
 937             dmi_din <= (others => '1');
 938         end case;
 939
 940         -- SIM magic exit
 941         if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
 942             stop;
 943         end if;
 944     end process;
 945
 946     -- Wishbone debug master (TODO: Add a DMI address decoder)
 947     wishbone_debug: entity work.wishbone_debug_master
 948         port map(clk => system_clk,
 949                  rst => rst_wbdb,
 950                  dmi_addr => dmi_addr(1 downto 0),
 951                  dmi_dout => dmi_wb_dout,
 952                  dmi_din => dmi_dout,
 953                  dmi_wr => dmi_wr,
 954                  dmi_ack => dmi_wb_ack,
 955                  dmi_req => dmi_wb_req,
 956                  wb_in => wishbone_debug_in,
 957                  wb_out => wishbone_debug_out);
 958
 959 --pragma synthesis_off
 960     wb_x_state: process(system_clk)
 961     begin
 962         if rising_edge(system_clk) then
 963             if not rst then
 964                 -- Wishbone arbiter
 965                 assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure;
 966                 assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure;
 967                 assert not(is_x(wb_masters_out(2).cyc)) and not(is_x(wb_masters_out(2).stb)) severity failure;
 968                 assert not(is_x(wb_masters_in(0).ack)) severity failure;
 969                 assert not(is_x(wb_masters_in(1).ack)) severity failure;
 970                 assert not(is_x(wb_masters_in(2).ack)) severity failure;
 971
 972                 -- Main memory wishbones
 973                 assert not(is_x(wb_bram_in.cyc)) and not (is_x(wb_bram_in.stb)) severity failure;
 974                 assert not(is_x(wb_dram_in.cyc)) and not (is_x(wb_dram_in.stb)) severity failure;
 975                 assert not(is_x(wb_io_in.cyc)) and not (is_x(wb_io_in.stb)) severity failure;
 976                 assert not(is_x(wb_bram_out.ack)) severity failure;
 977                 assert not(is_x(wb_dram_out.ack)) severity failure;
 978                 assert not(is_x(wb_io_out.ack)) severity failure;
 979
 980                 -- I/O wishbones
 981                 assert not(is_x(wb_uart0_in.cyc)) and not(is_x(wb_uart0_in.stb)) severity failure;
 982                 assert not(is_x(wb_uart1_in.cyc)) and not(is_x(wb_uart1_in.stb)) severity failure;
 983                 assert not(is_x(wb_spiflash_in.cyc)) and not(is_x(wb_spiflash_in.stb)) severity failure;
 984                 assert not(is_x(wb_xics_icp_in.cyc)) and not(is_x(wb_xics_icp_in.stb)) severity failure;
 985                 assert not(is_x(wb_xics_ics_in.cyc)) and not(is_x(wb_xics_ics_in.stb)) severity failure;
 986                 assert not(is_x(wb_ext_io_in.cyc)) and not(is_x(wb_ext_io_in.stb)) severity failure;
 987                 assert not(is_x(wb_syscon_in.cyc)) and not(is_x(wb_syscon_in.stb)) severity failure;
 988                 assert not(is_x(wb_uart0_out.ack)) severity failure;
 989                 assert not(is_x(wb_uart1_out.ack)) severity failure;
 990                 assert not(is_x(wb_spiflash_out.ack)) severity failure;
 991                 assert not(is_x(wb_xics_icp_out.ack)) severity failure;
 992                 assert not(is_x(wb_xics_ics_out.ack)) severity failure;
 993                 assert not(is_x(wb_ext_io_out.ack)) severity failure;
 994                 assert not(is_x(wb_syscon_out.ack)) severity failure;
 995             end if;
 996         end if;
 997     end process;
 998 --pragma synthesis_on
 999
1000 end architecture behaviour;